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0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/delay.h>
0013 #include <linux/bitfield.h>
0014 #include <linux/phy.h>
0015
0016 #include "aquantia.h"
0017
0018 #define PHY_ID_AQ1202 0x03a1b445
0019 #define PHY_ID_AQ2104 0x03a1b460
0020 #define PHY_ID_AQR105 0x03a1b4a2
0021 #define PHY_ID_AQR106 0x03a1b4d0
0022 #define PHY_ID_AQR107 0x03a1b4e0
0023 #define PHY_ID_AQCS109 0x03a1b5c2
0024 #define PHY_ID_AQR405 0x03a1b4b0
0025 #define PHY_ID_AQR113C 0x31c31c12
0026
0027 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
0028 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
0029 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
0030 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
0031 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
0032 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
0033 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
0034
0035 #define MDIO_AN_VEND_PROV 0xc400
0036 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
0037 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
0038 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
0039 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
0040 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
0041 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
0042 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
0043
0044 #define MDIO_AN_TX_VEND_STATUS1 0xc800
0045 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
0046 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0
0047 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
0048 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
0049 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
0050 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
0051 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
0052 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
0053
0054 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
0055 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
0056
0057 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
0058 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
0059
0060 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401
0061 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
0062
0063 #define MDIO_AN_RX_LP_STAT1 0xe820
0064 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
0065 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
0066 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
0067 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
0068 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
0069
0070 #define MDIO_AN_RX_LP_STAT4 0xe823
0071 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
0072 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
0073
0074 #define MDIO_AN_RX_VEND_STAT3 0xe832
0075 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
0076
0077
0078 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
0079 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
0080 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
0081 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
0082 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
0083 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
0084 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
0085 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
0086 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
0087 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
0088
0089
0090 #define VEND1_GLOBAL_FW_ID 0x0020
0091 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
0092 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
0093
0094 #define VEND1_GLOBAL_GEN_STAT2 0xc831
0095 #define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
0096
0097 #define VEND1_GLOBAL_RSVD_STAT1 0xc885
0098 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
0099 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
0100
0101 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d
0102 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
0103 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
0104
0105 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
0106 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
0107
0108 #define VEND1_GLOBAL_INT_STD_MASK 0xff00
0109 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
0110 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
0111 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
0112 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
0113 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
0114 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
0115 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
0116 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
0117 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
0118 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
0119 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
0120
0121 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01
0122 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
0123 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
0124 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
0125 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
0126 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
0127 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
0128 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
0129 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
0130
0131
0132
0133
0134 #define AQR107_OP_IN_PROG_SLEEP 1000
0135 #define AQR107_OP_IN_PROG_TIMEOUT 100000
0136
0137 struct aqr107_hw_stat {
0138 const char *name;
0139 int reg;
0140 int size;
0141 };
0142
0143 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
0144 static const struct aqr107_hw_stat aqr107_hw_stats[] = {
0145 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
0146 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
0147 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
0148 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
0149 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
0150 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
0151 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
0152 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
0153 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
0154 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
0155 };
0156 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
0157
0158 struct aqr107_priv {
0159 u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
0160 };
0161
0162 static int aqr107_get_sset_count(struct phy_device *phydev)
0163 {
0164 return AQR107_SGMII_STAT_SZ;
0165 }
0166
0167 static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
0168 {
0169 int i;
0170
0171 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
0172 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
0173 ETH_GSTRING_LEN);
0174 }
0175
0176 static u64 aqr107_get_stat(struct phy_device *phydev, int index)
0177 {
0178 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
0179 int len_l = min(stat->size, 16);
0180 int len_h = stat->size - len_l;
0181 u64 ret;
0182 int val;
0183
0184 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
0185 if (val < 0)
0186 return U64_MAX;
0187
0188 ret = val & GENMASK(len_l - 1, 0);
0189 if (len_h) {
0190 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
0191 if (val < 0)
0192 return U64_MAX;
0193
0194 ret += (val & GENMASK(len_h - 1, 0)) << 16;
0195 }
0196
0197 return ret;
0198 }
0199
0200 static void aqr107_get_stats(struct phy_device *phydev,
0201 struct ethtool_stats *stats, u64 *data)
0202 {
0203 struct aqr107_priv *priv = phydev->priv;
0204 u64 val;
0205 int i;
0206
0207 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
0208 val = aqr107_get_stat(phydev, i);
0209 if (val == U64_MAX)
0210 phydev_err(phydev, "Reading HW Statistics failed for %s\n",
0211 aqr107_hw_stats[i].name);
0212 else
0213 priv->sgmii_stats[i] += val;
0214
0215 data[i] = priv->sgmii_stats[i];
0216 }
0217 }
0218
0219 static int aqr_config_aneg(struct phy_device *phydev)
0220 {
0221 bool changed = false;
0222 u16 reg;
0223 int ret;
0224
0225 if (phydev->autoneg == AUTONEG_DISABLE)
0226 return genphy_c45_pma_setup_forced(phydev);
0227
0228 ret = genphy_c45_an_config_aneg(phydev);
0229 if (ret < 0)
0230 return ret;
0231 if (ret > 0)
0232 changed = true;
0233
0234
0235
0236
0237 reg = 0;
0238 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
0239 phydev->advertising))
0240 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
0241
0242 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
0243 phydev->advertising))
0244 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
0245
0246
0247 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
0248 phydev->advertising))
0249 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
0250
0251 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
0252 phydev->advertising))
0253 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
0254
0255 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
0256 MDIO_AN_VEND_PROV_1000BASET_HALF |
0257 MDIO_AN_VEND_PROV_1000BASET_FULL |
0258 MDIO_AN_VEND_PROV_2500BASET_FULL |
0259 MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
0260 if (ret < 0)
0261 return ret;
0262 if (ret > 0)
0263 changed = true;
0264
0265 return genphy_c45_check_and_restart_aneg(phydev, changed);
0266 }
0267
0268 static int aqr_config_intr(struct phy_device *phydev)
0269 {
0270 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
0271 int err;
0272
0273 if (en) {
0274
0275 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
0276 if (err < 0)
0277 return err;
0278 }
0279
0280 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
0281 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
0282 if (err < 0)
0283 return err;
0284
0285 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
0286 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
0287 if (err < 0)
0288 return err;
0289
0290 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
0291 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
0292 VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
0293 if (err < 0)
0294 return err;
0295
0296 if (!en) {
0297
0298 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
0299 if (err < 0)
0300 return err;
0301 }
0302
0303 return 0;
0304 }
0305
0306 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
0307 {
0308 int irq_status;
0309
0310 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
0311 MDIO_AN_TX_VEND_INT_STATUS2);
0312 if (irq_status < 0) {
0313 phy_error(phydev);
0314 return IRQ_NONE;
0315 }
0316
0317 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
0318 return IRQ_NONE;
0319
0320 phy_trigger_machine(phydev);
0321
0322 return IRQ_HANDLED;
0323 }
0324
0325 static int aqr_read_status(struct phy_device *phydev)
0326 {
0327 int val;
0328
0329 if (phydev->autoneg == AUTONEG_ENABLE) {
0330 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
0331 if (val < 0)
0332 return val;
0333
0334 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
0335 phydev->lp_advertising,
0336 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
0337 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
0338 phydev->lp_advertising,
0339 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
0340 }
0341
0342 return genphy_c45_read_status(phydev);
0343 }
0344
0345 static int aqr107_read_rate(struct phy_device *phydev)
0346 {
0347 int val;
0348
0349 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
0350 if (val < 0)
0351 return val;
0352
0353 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
0354 case MDIO_AN_TX_VEND_STATUS1_10BASET:
0355 phydev->speed = SPEED_10;
0356 break;
0357 case MDIO_AN_TX_VEND_STATUS1_100BASETX:
0358 phydev->speed = SPEED_100;
0359 break;
0360 case MDIO_AN_TX_VEND_STATUS1_1000BASET:
0361 phydev->speed = SPEED_1000;
0362 break;
0363 case MDIO_AN_TX_VEND_STATUS1_2500BASET:
0364 phydev->speed = SPEED_2500;
0365 break;
0366 case MDIO_AN_TX_VEND_STATUS1_5000BASET:
0367 phydev->speed = SPEED_5000;
0368 break;
0369 case MDIO_AN_TX_VEND_STATUS1_10GBASET:
0370 phydev->speed = SPEED_10000;
0371 break;
0372 default:
0373 phydev->speed = SPEED_UNKNOWN;
0374 break;
0375 }
0376
0377 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
0378 phydev->duplex = DUPLEX_FULL;
0379 else
0380 phydev->duplex = DUPLEX_HALF;
0381
0382 return 0;
0383 }
0384
0385 static int aqr107_read_status(struct phy_device *phydev)
0386 {
0387 int val, ret;
0388
0389 ret = aqr_read_status(phydev);
0390 if (ret)
0391 return ret;
0392
0393 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
0394 return 0;
0395
0396 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
0397 if (val < 0)
0398 return val;
0399
0400 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
0401 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
0402 phydev->interface = PHY_INTERFACE_MODE_10GKR;
0403 break;
0404 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
0405 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
0406 break;
0407 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
0408 phydev->interface = PHY_INTERFACE_MODE_USXGMII;
0409 break;
0410 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
0411 phydev->interface = PHY_INTERFACE_MODE_SGMII;
0412 break;
0413 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
0414 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
0415 break;
0416 default:
0417 phydev->interface = PHY_INTERFACE_MODE_NA;
0418 break;
0419 }
0420
0421
0422 return aqr107_read_rate(phydev);
0423 }
0424
0425 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
0426 {
0427 int val, cnt, enable;
0428
0429 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
0430 if (val < 0)
0431 return val;
0432
0433 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
0434 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
0435
0436 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
0437
0438 return 0;
0439 }
0440
0441 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
0442 {
0443 int val = 0;
0444
0445 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
0446 return -E2BIG;
0447
0448 if (cnt != DOWNSHIFT_DEV_DISABLE) {
0449 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
0450 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
0451 }
0452
0453 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
0454 MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
0455 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
0456 }
0457
0458 static int aqr107_get_tunable(struct phy_device *phydev,
0459 struct ethtool_tunable *tuna, void *data)
0460 {
0461 switch (tuna->id) {
0462 case ETHTOOL_PHY_DOWNSHIFT:
0463 return aqr107_get_downshift(phydev, data);
0464 default:
0465 return -EOPNOTSUPP;
0466 }
0467 }
0468
0469 static int aqr107_set_tunable(struct phy_device *phydev,
0470 struct ethtool_tunable *tuna, const void *data)
0471 {
0472 switch (tuna->id) {
0473 case ETHTOOL_PHY_DOWNSHIFT:
0474 return aqr107_set_downshift(phydev, *(const u8 *)data);
0475 default:
0476 return -EOPNOTSUPP;
0477 }
0478 }
0479
0480
0481
0482
0483
0484
0485
0486
0487 static int aqr107_wait_reset_complete(struct phy_device *phydev)
0488 {
0489 int val;
0490
0491 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
0492 VEND1_GLOBAL_FW_ID, val, val != 0,
0493 20000, 2000000, false);
0494 }
0495
0496 static void aqr107_chip_info(struct phy_device *phydev)
0497 {
0498 u8 fw_major, fw_minor, build_id, prov_id;
0499 int val;
0500
0501 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
0502 if (val < 0)
0503 return;
0504
0505 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
0506 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
0507
0508 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
0509 if (val < 0)
0510 return;
0511
0512 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
0513 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
0514
0515 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
0516 fw_major, fw_minor, build_id, prov_id);
0517 }
0518
0519 static int aqr107_config_init(struct phy_device *phydev)
0520 {
0521 int ret;
0522
0523
0524 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
0525 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
0526 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
0527 phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
0528 phydev->interface != PHY_INTERFACE_MODE_10GKR &&
0529 phydev->interface != PHY_INTERFACE_MODE_10GBASER)
0530 return -ENODEV;
0531
0532 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
0533 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
0534
0535 ret = aqr107_wait_reset_complete(phydev);
0536 if (!ret)
0537 aqr107_chip_info(phydev);
0538
0539 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
0540 }
0541
0542 static int aqcs109_config_init(struct phy_device *phydev)
0543 {
0544 int ret;
0545
0546
0547 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
0548 phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
0549 return -ENODEV;
0550
0551 ret = aqr107_wait_reset_complete(phydev);
0552 if (!ret)
0553 aqr107_chip_info(phydev);
0554
0555
0556
0557
0558
0559 phy_set_max_speed(phydev, SPEED_2500);
0560
0561 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
0562 }
0563
0564 static void aqr107_link_change_notify(struct phy_device *phydev)
0565 {
0566 u8 fw_major, fw_minor;
0567 bool downshift, short_reach, afr;
0568 int mode, val;
0569
0570 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
0571 return;
0572
0573 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
0574
0575 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
0576 return;
0577
0578 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
0579 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
0580
0581 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
0582 if (val < 0)
0583 return;
0584
0585 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
0586 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
0587
0588 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
0589 if (val < 0)
0590 return;
0591
0592 afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
0593
0594 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
0595 fw_major, fw_minor,
0596 short_reach ? ", short reach mode" : "",
0597 downshift ? ", fast-retrain downshift advertised" : "",
0598 afr ? ", fast reframe advertised" : "");
0599
0600 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
0601 if (val < 0)
0602 return;
0603
0604 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
0605 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
0606 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
0607 }
0608
0609 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
0610 {
0611 int val, err;
0612
0613
0614
0615
0616
0617
0618 usleep_range(1000, 5000);
0619
0620 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
0621 VEND1_GLOBAL_GEN_STAT2, val,
0622 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
0623 AQR107_OP_IN_PROG_SLEEP,
0624 AQR107_OP_IN_PROG_TIMEOUT, false);
0625 if (err) {
0626 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
0627 return err;
0628 }
0629
0630 return 0;
0631 }
0632
0633 static int aqr107_suspend(struct phy_device *phydev)
0634 {
0635 int err;
0636
0637 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
0638 MDIO_CTRL1_LPOWER);
0639 if (err)
0640 return err;
0641
0642 return aqr107_wait_processor_intensive_op(phydev);
0643 }
0644
0645 static int aqr107_resume(struct phy_device *phydev)
0646 {
0647 int err;
0648
0649 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
0650 MDIO_CTRL1_LPOWER);
0651 if (err)
0652 return err;
0653
0654 return aqr107_wait_processor_intensive_op(phydev);
0655 }
0656
0657 static int aqr107_probe(struct phy_device *phydev)
0658 {
0659 phydev->priv = devm_kzalloc(&phydev->mdio.dev,
0660 sizeof(struct aqr107_priv), GFP_KERNEL);
0661 if (!phydev->priv)
0662 return -ENOMEM;
0663
0664 return aqr_hwmon_probe(phydev);
0665 }
0666
0667 static struct phy_driver aqr_driver[] = {
0668 {
0669 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
0670 .name = "Aquantia AQ1202",
0671 .config_aneg = aqr_config_aneg,
0672 .config_intr = aqr_config_intr,
0673 .handle_interrupt = aqr_handle_interrupt,
0674 .read_status = aqr_read_status,
0675 },
0676 {
0677 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
0678 .name = "Aquantia AQ2104",
0679 .config_aneg = aqr_config_aneg,
0680 .config_intr = aqr_config_intr,
0681 .handle_interrupt = aqr_handle_interrupt,
0682 .read_status = aqr_read_status,
0683 },
0684 {
0685 PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
0686 .name = "Aquantia AQR105",
0687 .config_aneg = aqr_config_aneg,
0688 .config_intr = aqr_config_intr,
0689 .handle_interrupt = aqr_handle_interrupt,
0690 .read_status = aqr_read_status,
0691 .suspend = aqr107_suspend,
0692 .resume = aqr107_resume,
0693 },
0694 {
0695 PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
0696 .name = "Aquantia AQR106",
0697 .config_aneg = aqr_config_aneg,
0698 .config_intr = aqr_config_intr,
0699 .handle_interrupt = aqr_handle_interrupt,
0700 .read_status = aqr_read_status,
0701 },
0702 {
0703 PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
0704 .name = "Aquantia AQR107",
0705 .probe = aqr107_probe,
0706 .config_init = aqr107_config_init,
0707 .config_aneg = aqr_config_aneg,
0708 .config_intr = aqr_config_intr,
0709 .handle_interrupt = aqr_handle_interrupt,
0710 .read_status = aqr107_read_status,
0711 .get_tunable = aqr107_get_tunable,
0712 .set_tunable = aqr107_set_tunable,
0713 .suspend = aqr107_suspend,
0714 .resume = aqr107_resume,
0715 .get_sset_count = aqr107_get_sset_count,
0716 .get_strings = aqr107_get_strings,
0717 .get_stats = aqr107_get_stats,
0718 .link_change_notify = aqr107_link_change_notify,
0719 },
0720 {
0721 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
0722 .name = "Aquantia AQCS109",
0723 .probe = aqr107_probe,
0724 .config_init = aqcs109_config_init,
0725 .config_aneg = aqr_config_aneg,
0726 .config_intr = aqr_config_intr,
0727 .handle_interrupt = aqr_handle_interrupt,
0728 .read_status = aqr107_read_status,
0729 .get_tunable = aqr107_get_tunable,
0730 .set_tunable = aqr107_set_tunable,
0731 .suspend = aqr107_suspend,
0732 .resume = aqr107_resume,
0733 .get_sset_count = aqr107_get_sset_count,
0734 .get_strings = aqr107_get_strings,
0735 .get_stats = aqr107_get_stats,
0736 .link_change_notify = aqr107_link_change_notify,
0737 },
0738 {
0739 PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
0740 .name = "Aquantia AQR405",
0741 .config_aneg = aqr_config_aneg,
0742 .config_intr = aqr_config_intr,
0743 .handle_interrupt = aqr_handle_interrupt,
0744 .read_status = aqr_read_status,
0745 },
0746 {
0747 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
0748 .name = "Aquantia AQR113C",
0749 .probe = aqr107_probe,
0750 .config_init = aqr107_config_init,
0751 .config_aneg = aqr_config_aneg,
0752 .config_intr = aqr_config_intr,
0753 .handle_interrupt = aqr_handle_interrupt,
0754 .read_status = aqr107_read_status,
0755 .get_tunable = aqr107_get_tunable,
0756 .set_tunable = aqr107_set_tunable,
0757 .suspend = aqr107_suspend,
0758 .resume = aqr107_resume,
0759 .get_sset_count = aqr107_get_sset_count,
0760 .get_strings = aqr107_get_strings,
0761 .get_stats = aqr107_get_stats,
0762 .link_change_notify = aqr107_link_change_notify,
0763 },
0764 };
0765
0766 module_phy_driver(aqr_driver);
0767
0768 static struct mdio_device_id __maybe_unused aqr_tbl[] = {
0769 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
0770 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
0771 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
0772 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
0773 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
0774 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
0775 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
0776 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
0777 { }
0778 };
0779
0780 MODULE_DEVICE_TABLE(mdio, aqr_tbl);
0781
0782 MODULE_DESCRIPTION("Aquantia PHY driver");
0783 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
0784 MODULE_LICENSE("GPL v2");
