net/pcs/pcs-xpcs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
0004  * Synopsys DesignWare XPCS helpers
0005  *
0006  * Author: Jose Abreu <Jose.Abreu@synopsys.com>
0007  */
0008
0009 #define SYNOPSYS_XPCS_ID        0x7996ced0
0010 #define SYNOPSYS_XPCS_MASK      0xffffffff
0011
0012 /* Vendor regs access */
0013 #define DW_VENDOR           BIT(15)
0014
0015 /* VR_XS_PCS */
0016 #define DW_USXGMII_RST          BIT(10)
0017 #define DW_USXGMII_EN           BIT(9)
0018 #define DW_VR_XS_PCS_DIG_STS        0x0010
0019 #define DW_RXFIFO_ERR           GENMASK(6, 5)
0020
0021 /* SR_MII */
0022 #define DW_USXGMII_FULL         BIT(8)
0023 #define DW_USXGMII_SS_MASK      (BIT(13) | BIT(6) | BIT(5))
0024 #define DW_USXGMII_10000        (BIT(13) | BIT(6))
0025 #define DW_USXGMII_5000         (BIT(13) | BIT(5))
0026 #define DW_USXGMII_2500         (BIT(5))
0027 #define DW_USXGMII_1000         (BIT(6))
0028 #define DW_USXGMII_100          (BIT(13))
0029 #define DW_USXGMII_10           (0)
0030
0031 /* SR_AN */
0032 #define DW_SR_AN_ADV1           0x10
0033 #define DW_SR_AN_ADV2           0x11
0034 #define DW_SR_AN_ADV3           0x12
0035 #define DW_SR_AN_LP_ABL1        0x13
0036 #define DW_SR_AN_LP_ABL2        0x14
0037 #define DW_SR_AN_LP_ABL3        0x15
0038
0039 /* Clause 73 Defines */
0040 /* AN_LP_ABL1 */
0041 #define DW_C73_PAUSE            BIT(10)
0042 #define DW_C73_ASYM_PAUSE       BIT(11)
0043 #define DW_C73_AN_ADV_SF        0x1
0044 /* AN_LP_ABL2 */
0045 #define DW_C73_1000KX           BIT(5)
0046 #define DW_C73_10000KX4         BIT(6)
0047 #define DW_C73_10000KR          BIT(7)
0048 /* AN_LP_ABL3 */
0049 #define DW_C73_2500KX           BIT(0)
0050 #define DW_C73_5000KR           BIT(1)
0051
0052 /* Clause 37 Defines */
0053 /* VR MII MMD registers offsets */
0054 #define DW_VR_MII_MMD_CTRL      0x0000
0055 #define DW_VR_MII_DIG_CTRL1     0x8000
0056 #define DW_VR_MII_AN_CTRL       0x8001
0057 #define DW_VR_MII_AN_INTR_STS       0x8002
0058 /* Enable 2.5G Mode */
0059 #define DW_VR_MII_DIG_CTRL1_2G5_EN  BIT(2)
0060 /* EEE Mode Control Register */
0061 #define DW_VR_MII_EEE_MCTRL0        0x8006
0062 #define DW_VR_MII_EEE_MCTRL1        0x800b
0063 #define DW_VR_MII_DIG_CTRL2     0x80e1
0064
0065 /* VR_MII_DIG_CTRL1 */
0066 #define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW     BIT(9)
0067
0068 /* VR_MII_DIG_CTRL2 */
0069 #define DW_VR_MII_DIG_CTRL2_TX_POL_INV      BIT(4)
0070 #define DW_VR_MII_DIG_CTRL2_RX_POL_INV      BIT(0)
0071
0072 /* VR_MII_AN_CTRL */
0073 #define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT   3
0074 #define DW_VR_MII_TX_CONFIG_MASK        BIT(3)
0075 #define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII  0x1
0076 #define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII  0x0
0077 #define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT    1
0078 #define DW_VR_MII_PCS_MODE_MASK         GENMASK(2, 1)
0079 #define DW_VR_MII_PCS_MODE_C37_1000BASEX    0x0
0080 #define DW_VR_MII_PCS_MODE_C37_SGMII        0x2
0081
0082 /* VR_MII_AN_INTR_STS */
0083 #define DW_VR_MII_AN_STS_C37_ANSGM_FD       BIT(1)
0084 #define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT 2
0085 #define DW_VR_MII_AN_STS_C37_ANSGM_SP       GENMASK(3, 2)
0086 #define DW_VR_MII_C37_ANSGM_SP_10       0x0
0087 #define DW_VR_MII_C37_ANSGM_SP_100      0x1
0088 #define DW_VR_MII_C37_ANSGM_SP_1000     0x2
0089 #define DW_VR_MII_C37_ANSGM_SP_LNKSTS       BIT(4)
0090
0091 /* SR MII MMD Control defines */
0092 #define AN_CL37_EN          BIT(12) /* Enable Clause 37 auto-nego */
0093 #define SGMII_SPEED_SS13        BIT(13) /* SGMII speed along with SS6 */
0094 #define SGMII_SPEED_SS6         BIT(6)  /* SGMII speed along with SS13 */
0095
0096 /* VR MII EEE Control 0 defines */
0097 #define DW_VR_MII_EEE_LTX_EN            BIT(0)  /* LPI Tx Enable */
0098 #define DW_VR_MII_EEE_LRX_EN            BIT(1)  /* LPI Rx Enable */
0099 #define DW_VR_MII_EEE_TX_QUIET_EN       BIT(2)  /* Tx Quiet Enable */
0100 #define DW_VR_MII_EEE_RX_QUIET_EN       BIT(3)  /* Rx Quiet Enable */
0101 #define DW_VR_MII_EEE_TX_EN_CTRL        BIT(4)  /* Tx Control Enable */
0102 #define DW_VR_MII_EEE_RX_EN_CTRL        BIT(7)  /* Rx Control Enable */
0103
0104 #define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT 8
0105 #define DW_VR_MII_EEE_MULT_FACT_100NS       GENMASK(11, 8)
0106
0107 /* VR MII EEE Control 1 defines */
0108 #define DW_VR_MII_EEE_TRN_LPI       BIT(0)  /* Transparent Mode Enable */
0109
0110 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg);
0111 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val);
0112 int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs);
0113 int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs);
0114 int nxp_sja1110_2500basex_pma_config(struct dw_xpcs *xpcs);