net/pcs/pcs-rzn1-miic.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2022 Schneider Electric
0004  *
0005  * Clément Léger <clement.leger@bootlin.com>
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/device.h>
0010 #include <linux/mdio.h>
0011 #include <linux/of.h>
0012 #include <linux/of_platform.h>
0013 #include <linux/pcs-rzn1-miic.h>
0014 #include <linux/phylink.h>
0015 #include <linux/pm_runtime.h>
0016 #include <dt-bindings/net/pcs-rzn1-miic.h>
0017
0018 #define MIIC_PRCMD          0x0
0019 #define MIIC_ESID_CODE          0x4
0020
0021 #define MIIC_MODCTRL            0x20
0022 #define MIIC_MODCTRL_SW_MODE        GENMASK(4, 0)
0023
0024 #define MIIC_CONVCTRL(port)     (0x100 + (port) * 4)
0025
0026 #define MIIC_CONVCTRL_CONV_SPEED    GENMASK(1, 0)
0027 #define CONV_MODE_10MBPS        0
0028 #define CONV_MODE_100MBPS       1
0029 #define CONV_MODE_1000MBPS      2
0030
0031 #define MIIC_CONVCTRL_CONV_MODE     GENMASK(3, 2)
0032 #define CONV_MODE_MII           0
0033 #define CONV_MODE_RMII          1
0034 #define CONV_MODE_RGMII         2
0035
0036 #define MIIC_CONVCTRL_FULLD     BIT(8)
0037 #define MIIC_CONVCTRL_RGMII_LINK    BIT(12)
0038 #define MIIC_CONVCTRL_RGMII_DUPLEX  BIT(13)
0039 #define MIIC_CONVCTRL_RGMII_SPEED   GENMASK(15, 14)
0040
0041 #define MIIC_CONVRST            0x114
0042 #define MIIC_CONVRST_PHYIF_RST(port)    BIT(port)
0043 #define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0)
0044
0045 #define MIIC_SWCTRL         0x304
0046 #define MIIC_SWDUPC         0x308
0047
0048 #define MIIC_MAX_NR_PORTS       5
0049
0050 #define MIIC_MODCTRL_CONF_CONV_NUM  6
0051 #define MIIC_MODCTRL_CONF_NONE      -1
0052
0053 /**
0054  * struct modctrl_match - Matching table entry for  convctrl configuration
0055  *            See section 8.2.1 of manual.
0056  * @mode_cfg: Configuration value for convctrl
0057  * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN,
0058  *    then index 1 - 5 are CONV1 - CONV5.
0059  */
0060 struct modctrl_match {
0061     u32 mode_cfg;
0062     u8 conv[MIIC_MODCTRL_CONF_CONV_NUM];
0063 };
0064
0065 static struct modctrl_match modctrl_match_table[] = {
0066     {0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0067            MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
0068     {0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0069            MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
0070     {0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0071            MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
0072     {0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0073            MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
0074
0075     {0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0076            MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
0077     {0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0078            MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
0079     {0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0080            MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
0081     {0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0082            MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
0083
0084     {0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0085         MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
0086     {0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0087         MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
0088     {0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0089         MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
0090     {0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
0091         MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}
0092 };
0093
0094 static const char * const conf_to_string[] = {
0095     [MIIC_GMAC1_PORT]   = "GMAC1_PORT",
0096     [MIIC_GMAC2_PORT]   = "GMAC2_PORT",
0097     [MIIC_RTOS_PORT]    = "RTOS_PORT",
0098     [MIIC_SERCOS_PORTA] = "SERCOS_PORTA",
0099     [MIIC_SERCOS_PORTB] = "SERCOS_PORTB",
0100     [MIIC_ETHERCAT_PORTA]   = "ETHERCAT_PORTA",
0101     [MIIC_ETHERCAT_PORTB]   = "ETHERCAT_PORTB",
0102     [MIIC_ETHERCAT_PORTC]   = "ETHERCAT_PORTC",
0103     [MIIC_SWITCH_PORTA] = "SWITCH_PORTA",
0104     [MIIC_SWITCH_PORTB] = "SWITCH_PORTB",
0105     [MIIC_SWITCH_PORTC] = "SWITCH_PORTC",
0106     [MIIC_SWITCH_PORTD] = "SWITCH_PORTD",
0107     [MIIC_HSR_PORTA]    = "HSR_PORTA",
0108     [MIIC_HSR_PORTB]    = "HSR_PORTB",
0109 };
0110
0111 static const char *index_to_string[MIIC_MODCTRL_CONF_CONV_NUM] = {
0112     "SWITCH_PORTIN",
0113     "CONV1",
0114     "CONV2",
0115     "CONV3",
0116     "CONV4",
0117     "CONV5",
0118 };
0119
0120 /**
0121  * struct miic - MII converter structure
0122  * @base: base address of the MII converter
0123  * @dev: Device associated to the MII converter
0124  * @clks: Clocks used for this device
0125  * @nclk: Number of clocks
0126  * @lock: Lock used for read-modify-write access
0127  */
0128 struct miic {
0129     void __iomem *base;
0130     struct device *dev;
0131     struct clk_bulk_data *clks;
0132     int nclk;
0133     spinlock_t lock;
0134 };
0135
0136 /**
0137  * struct miic_port - Per port MII converter struct
0138  * @miic: backiling to MII converter structure
0139  * @pcs: PCS structure associated to the port
0140  * @port: port number
0141  * @interface: interface mode of the port
0142  */
0143 struct miic_port {
0144     struct miic *miic;
0145     struct phylink_pcs pcs;
0146     int port;
0147     phy_interface_t interface;
0148 };
0149
0150 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs)
0151 {
0152     return container_of(pcs, struct miic_port, pcs);
0153 }
0154
0155 static void miic_reg_writel(struct miic *miic, int offset, u32 value)
0156 {
0157     writel(value, miic->base + offset);
0158 }
0159
0160 static u32 miic_reg_readl(struct miic *miic, int offset)
0161 {
0162     return readl(miic->base + offset);
0163 }
0164
0165 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val)
0166 {
0167     u32 reg;
0168
0169     spin_lock(&miic->lock);
0170
0171     reg = miic_reg_readl(miic, offset);
0172     reg &= ~mask;
0173     reg |= val;
0174     miic_reg_writel(miic, offset, reg);
0175
0176     spin_unlock(&miic->lock);
0177 }
0178
0179 static void miic_converter_enable(struct miic *miic, int port, int enable)
0180 {
0181     u32 val = 0;
0182
0183     if (enable)
0184         val = MIIC_CONVRST_PHYIF_RST(port);
0185
0186     miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val);
0187 }
0188
0189 static int miic_config(struct phylink_pcs *pcs, unsigned int mode,
0190                phy_interface_t interface,
0191                const unsigned long *advertising, bool permit)
0192 {
0193     struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
0194     struct miic *miic = miic_port->miic;
0195     u32 speed, conv_mode, val, mask;
0196     int port = miic_port->port;
0197
0198     switch (interface) {
0199     case PHY_INTERFACE_MODE_RMII:
0200         conv_mode = CONV_MODE_RMII;
0201         speed = CONV_MODE_100MBPS;
0202         break;
0203     case PHY_INTERFACE_MODE_RGMII:
0204     case PHY_INTERFACE_MODE_RGMII_ID:
0205     case PHY_INTERFACE_MODE_RGMII_TXID:
0206     case PHY_INTERFACE_MODE_RGMII_RXID:
0207         conv_mode = CONV_MODE_RGMII;
0208         speed = CONV_MODE_1000MBPS;
0209         break;
0210     case PHY_INTERFACE_MODE_MII:
0211         conv_mode = CONV_MODE_MII;
0212         /* When in MII mode, speed should be set to 0 (which is actually
0213          * CONV_MODE_10MBPS)
0214          */
0215         speed = CONV_MODE_10MBPS;
0216         break;
0217     default:
0218         return -EOPNOTSUPP;
0219     }
0220
0221     val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode);
0222     mask = MIIC_CONVCTRL_CONV_MODE;
0223
0224     /* Update speed only if we are going to change the interface because
0225      * the link might already be up and it would break it if the speed is
0226      * changed.
0227      */
0228     if (interface != miic_port->interface) {
0229         val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed);
0230         mask |= MIIC_CONVCTRL_CONV_SPEED;
0231         miic_port->interface = interface;
0232     }
0233
0234     miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val);
0235     miic_converter_enable(miic_port->miic, miic_port->port, 1);
0236
0237     return 0;
0238 }
0239
0240 static void miic_link_up(struct phylink_pcs *pcs, unsigned int mode,
0241              phy_interface_t interface, int speed, int duplex)
0242 {
0243     struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
0244     struct miic *miic = miic_port->miic;
0245     u32 conv_speed = 0, val = 0;
0246     int port = miic_port->port;
0247
0248     if (duplex == DUPLEX_FULL)
0249         val |= MIIC_CONVCTRL_FULLD;
0250
0251     /* No speed in MII through-mode */
0252     if (interface != PHY_INTERFACE_MODE_MII) {
0253         switch (speed) {
0254         case SPEED_1000:
0255             conv_speed = CONV_MODE_1000MBPS;
0256             break;
0257         case SPEED_100:
0258             conv_speed = CONV_MODE_100MBPS;
0259             break;
0260         case SPEED_10:
0261             conv_speed = CONV_MODE_10MBPS;
0262             break;
0263         default:
0264             return;
0265         }
0266     }
0267
0268     val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed);
0269
0270     miic_reg_rmw(miic, MIIC_CONVCTRL(port),
0271              (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val);
0272 }
0273
0274 static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported,
0275              const struct phylink_link_state *state)
0276 {
0277     if (phy_interface_mode_is_rgmii(state->interface) ||
0278         state->interface == PHY_INTERFACE_MODE_RMII ||
0279         state->interface == PHY_INTERFACE_MODE_MII)
0280         return 1;
0281
0282     return -EINVAL;
0283 }
0284
0285 static const struct phylink_pcs_ops miic_phylink_ops = {
0286     .pcs_validate = miic_validate,
0287     .pcs_config = miic_config,
0288     .pcs_link_up = miic_link_up,
0289 };
0290
0291 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)
0292 {
0293     struct platform_device *pdev;
0294     struct miic_port *miic_port;
0295     struct device_node *pcs_np;
0296     struct miic *miic;
0297     u32 port;
0298
0299     if (!of_device_is_available(np))
0300         return ERR_PTR(-ENODEV);
0301
0302     if (of_property_read_u32(np, "reg", &port))
0303         return ERR_PTR(-EINVAL);
0304
0305     if (port > MIIC_MAX_NR_PORTS || port < 1)
0306         return ERR_PTR(-EINVAL);
0307
0308     /* The PCS pdev is attached to the parent node */
0309     pcs_np = of_get_parent(np);
0310     if (!pcs_np)
0311         return ERR_PTR(-ENODEV);
0312
0313     if (!of_device_is_available(pcs_np)) {
0314         of_node_put(pcs_np);
0315         return ERR_PTR(-ENODEV);
0316     }
0317
0318     pdev = of_find_device_by_node(pcs_np);
0319     of_node_put(pcs_np);
0320     if (!pdev || !platform_get_drvdata(pdev))
0321         return ERR_PTR(-EPROBE_DEFER);
0322
0323     miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL);
0324     if (!miic_port)
0325         return ERR_PTR(-ENOMEM);
0326
0327     miic = platform_get_drvdata(pdev);
0328     device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
0329
0330     miic_port->miic = miic;
0331     miic_port->port = port - 1;
0332     miic_port->pcs.ops = &miic_phylink_ops;
0333
0334     return &miic_port->pcs;
0335 }
0336 EXPORT_SYMBOL(miic_create);
0337
0338 void miic_destroy(struct phylink_pcs *pcs)
0339 {
0340     struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
0341
0342     miic_converter_enable(miic_port->miic, miic_port->port, 0);
0343     kfree(miic_port);
0344 }
0345 EXPORT_SYMBOL(miic_destroy);
0346
0347 static int miic_init_hw(struct miic *miic, u32 cfg_mode)
0348 {
0349     int port;
0350
0351     /* Unlock write access to accessory registers (cf datasheet). If this
0352      * is going to be used in conjunction with the Cortex-M3, this sequence
0353      * will have to be moved in register write
0354      */
0355     miic_reg_writel(miic, MIIC_PRCMD, 0x00A5);
0356     miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
0357     miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE);
0358     miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
0359
0360     miic_reg_writel(miic, MIIC_MODCTRL,
0361             FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
0362
0363     for (port = 0; port < MIIC_MAX_NR_PORTS; port++) {
0364         miic_converter_enable(miic, port, 0);
0365         /* Disable speed/duplex control from these registers, datasheet
0366          * says switch registers should be used to setup switch port
0367          * speed and duplex.
0368          */
0369         miic_reg_writel(miic, MIIC_SWCTRL, 0x0);
0370         miic_reg_writel(miic, MIIC_SWDUPC, 0x0);
0371     }
0372
0373     return 0;
0374 }
0375
0376 static bool miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM],
0377                    s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM])
0378 {
0379     int i;
0380
0381     for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) {
0382         if (dt_val[i] == MIIC_MODCTRL_CONF_NONE)
0383             continue;
0384
0385         if (dt_val[i] != table_val[i])
0386             return false;
0387     }
0388
0389     return true;
0390 }
0391
0392 static void miic_dump_conf(struct device *dev,
0393                s8 conf[MIIC_MODCTRL_CONF_CONV_NUM])
0394 {
0395     const char *conf_name;
0396     int i;
0397
0398     for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) {
0399         if (conf[i] != MIIC_MODCTRL_CONF_NONE)
0400             conf_name = conf_to_string[conf[i]];
0401         else
0402             conf_name = "NONE";
0403
0404         dev_err(dev, "%s: %s\n", index_to_string[i], conf_name);
0405     }
0406 }
0407
0408 static int miic_match_dt_conf(struct device *dev,
0409                   s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM],
0410                   u32 *mode_cfg)
0411 {
0412     struct modctrl_match *table_entry;
0413     int i;
0414
0415     for (i = 0; i < ARRAY_SIZE(modctrl_match_table); i++) {
0416         table_entry = &modctrl_match_table[i];
0417
0418         if (miic_modctrl_match(table_entry->conv, dt_val)) {
0419             *mode_cfg = table_entry->mode_cfg;
0420             return 0;
0421         }
0422     }
0423
0424     dev_err(dev, "Failed to apply requested configuration\n");
0425     miic_dump_conf(dev, dt_val);
0426
0427     return -EINVAL;
0428 }
0429
0430 static int miic_parse_dt(struct device *dev, u32 *mode_cfg)
0431 {
0432     s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM];
0433     struct device_node *np = dev->of_node;
0434     struct device_node *conv;
0435     u32 conf;
0436     int port;
0437
0438     memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(dt_val));
0439
0440     if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0)
0441         dt_val[0] = conf;
0442
0443     for_each_child_of_node(np, conv) {
0444         if (of_property_read_u32(conv, "reg", &port))
0445             continue;
0446
0447         if (!of_device_is_available(conv))
0448             continue;
0449
0450         if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0)
0451             dt_val[port] = conf;
0452     }
0453
0454     return miic_match_dt_conf(dev, dt_val, mode_cfg);
0455 }
0456
0457 static int miic_probe(struct platform_device *pdev)
0458 {
0459     struct device *dev = &pdev->dev;
0460     struct miic *miic;
0461     u32 mode_cfg;
0462     int ret;
0463
0464     ret = miic_parse_dt(dev, &mode_cfg);
0465     if (ret < 0)
0466         return ret;
0467
0468     miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL);
0469     if (!miic)
0470         return -ENOMEM;
0471
0472     spin_lock_init(&miic->lock);
0473     miic->dev = dev;
0474     miic->base = devm_platform_ioremap_resource(pdev, 0);
0475     if (IS_ERR(miic->base))
0476         return PTR_ERR(miic->base);
0477
0478     ret = devm_pm_runtime_enable(dev);
0479     if (ret < 0)
0480         return ret;
0481
0482     ret = pm_runtime_resume_and_get(dev);
0483     if (ret < 0)
0484         return ret;
0485
0486     ret = miic_init_hw(miic, mode_cfg);
0487     if (ret)
0488         goto disable_runtime_pm;
0489
0490     /* miic_create() relies on that fact that data are attached to the
0491      * platform device to determine if the driver is ready so this needs to
0492      * be the last thing to be done after everything is initialized
0493      * properly.
0494      */
0495     platform_set_drvdata(pdev, miic);
0496
0497     return 0;
0498
0499 disable_runtime_pm:
0500     pm_runtime_put(dev);
0501
0502     return ret;
0503 }
0504
0505 static int miic_remove(struct platform_device *pdev)
0506 {
0507     pm_runtime_put(&pdev->dev);
0508
0509     return 0;
0510 }
0511
0512 static const struct of_device_id miic_of_mtable[] = {
0513     { .compatible = "renesas,rzn1-miic" },
0514     { /* sentinel */ },
0515 };
0516 MODULE_DEVICE_TABLE(of, miic_of_mtable);
0517
0518 static struct platform_driver miic_driver = {
0519     .driver = {
0520         .name    = "rzn1_miic",
0521         .suppress_bind_attrs = true,
0522         .of_match_table = miic_of_mtable,
0523     },
0524     .probe = miic_probe,
0525     .remove = miic_remove,
0526 };
0527 module_platform_driver(miic_driver);
0528
0529 MODULE_LICENSE("GPL");
0530 MODULE_DESCRIPTION("Renesas MII converter PCS driver");
0531 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>");