net/mdio/mdio-mux-meson-g12a.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (c) 2019 Baylibre, SAS.
0003  * Author: Jerome Brunet <jbrunet@baylibre.com>
0004  */
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/device.h>
0010 #include <linux/io.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/mdio-mux.h>
0013 #include <linux/module.h>
0014 #include <linux/phy.h>
0015 #include <linux/platform_device.h>
0016
0017 #define ETH_PLL_STS     0x40
0018 #define ETH_PLL_CTL0        0x44
0019 #define  PLL_CTL0_LOCK_DIG  BIT(30)
0020 #define  PLL_CTL0_RST       BIT(29)
0021 #define  PLL_CTL0_EN        BIT(28)
0022 #define  PLL_CTL0_SEL       BIT(23)
0023 #define  PLL_CTL0_N     GENMASK(14, 10)
0024 #define  PLL_CTL0_M     GENMASK(8, 0)
0025 #define  PLL_LOCK_TIMEOUT   1000000
0026 #define  PLL_MUX_NUM_PARENT 2
0027 #define ETH_PLL_CTL1        0x48
0028 #define ETH_PLL_CTL2        0x4c
0029 #define ETH_PLL_CTL3        0x50
0030 #define ETH_PLL_CTL4        0x54
0031 #define ETH_PLL_CTL5        0x58
0032 #define ETH_PLL_CTL6        0x5c
0033 #define ETH_PLL_CTL7        0x60
0034
0035 #define ETH_PHY_CNTL0       0x80
0036 #define   EPHY_G12A_ID      0x33010180
0037 #define ETH_PHY_CNTL1       0x84
0038 #define  PHY_CNTL1_ST_MODE  GENMASK(2, 0)
0039 #define  PHY_CNTL1_ST_PHYADD    GENMASK(7, 3)
0040 #define   EPHY_DFLT_ADD     8
0041 #define  PHY_CNTL1_MII_MODE GENMASK(15, 14)
0042 #define   EPHY_MODE_RMII    0x1
0043 #define  PHY_CNTL1_CLK_EN   BIT(16)
0044 #define  PHY_CNTL1_CLKFREQ  BIT(17)
0045 #define  PHY_CNTL1_PHY_ENB  BIT(18)
0046 #define ETH_PHY_CNTL2       0x88
0047 #define  PHY_CNTL2_USE_INTERNAL BIT(5)
0048 #define  PHY_CNTL2_SMI_SRC_MAC  BIT(6)
0049 #define  PHY_CNTL2_RX_CLK_EPHY  BIT(9)
0050
0051 #define MESON_G12A_MDIO_EXTERNAL_ID 0
0052 #define MESON_G12A_MDIO_INTERNAL_ID 1
0053
0054 struct g12a_mdio_mux {
0055     bool pll_is_enabled;
0056     void __iomem *regs;
0057     void *mux_handle;
0058     struct clk *pclk;
0059     struct clk *pll;
0060 };
0061
0062 struct g12a_ephy_pll {
0063     void __iomem *base;
0064     struct clk_hw hw;
0065 };
0066
0067 #define g12a_ephy_pll_to_dev(_hw)           \
0068     container_of(_hw, struct g12a_ephy_pll, hw)
0069
0070 static unsigned long g12a_ephy_pll_recalc_rate(struct clk_hw *hw,
0071                            unsigned long parent_rate)
0072 {
0073     struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
0074     u32 val, m, n;
0075
0076     val = readl(pll->base + ETH_PLL_CTL0);
0077     m = FIELD_GET(PLL_CTL0_M, val);
0078     n = FIELD_GET(PLL_CTL0_N, val);
0079
0080     return parent_rate * m / n;
0081 }
0082
0083 static int g12a_ephy_pll_enable(struct clk_hw *hw)
0084 {
0085     struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
0086     u32 val = readl(pll->base + ETH_PLL_CTL0);
0087
0088     /* Apply both enable an reset */
0089     val |= PLL_CTL0_RST | PLL_CTL0_EN;
0090     writel(val, pll->base + ETH_PLL_CTL0);
0091
0092     /* Clear the reset to let PLL lock */
0093     val &= ~PLL_CTL0_RST;
0094     writel(val, pll->base + ETH_PLL_CTL0);
0095
0096     /* Poll on the digital lock instead of the usual analog lock
0097      * This is done because bit 31 is unreliable on some SoC. Bit
0098      * 31 may indicate that the PLL is not lock even though the clock
0099      * is actually running
0100      */
0101     return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val,
0102                   val & PLL_CTL0_LOCK_DIG, 0, PLL_LOCK_TIMEOUT);
0103 }
0104
0105 static void g12a_ephy_pll_disable(struct clk_hw *hw)
0106 {
0107     struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
0108     u32 val;
0109
0110     val = readl(pll->base + ETH_PLL_CTL0);
0111     val &= ~PLL_CTL0_EN;
0112     val |= PLL_CTL0_RST;
0113     writel(val, pll->base + ETH_PLL_CTL0);
0114 }
0115
0116 static int g12a_ephy_pll_is_enabled(struct clk_hw *hw)
0117 {
0118     struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
0119     unsigned int val;
0120
0121     val = readl(pll->base + ETH_PLL_CTL0);
0122
0123     return (val & PLL_CTL0_LOCK_DIG) ? 1 : 0;
0124 }
0125
0126 static int g12a_ephy_pll_init(struct clk_hw *hw)
0127 {
0128     struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
0129
0130     /* Apply PLL HW settings */
0131     writel(0x29c0040a, pll->base + ETH_PLL_CTL0);
0132     writel(0x927e0000, pll->base + ETH_PLL_CTL1);
0133     writel(0xac5f49e5, pll->base + ETH_PLL_CTL2);
0134     writel(0x00000000, pll->base + ETH_PLL_CTL3);
0135     writel(0x00000000, pll->base + ETH_PLL_CTL4);
0136     writel(0x20200000, pll->base + ETH_PLL_CTL5);
0137     writel(0x0000c002, pll->base + ETH_PLL_CTL6);
0138     writel(0x00000023, pll->base + ETH_PLL_CTL7);
0139
0140     return 0;
0141 }
0142
0143 static const struct clk_ops g12a_ephy_pll_ops = {
0144     .recalc_rate    = g12a_ephy_pll_recalc_rate,
0145     .is_enabled = g12a_ephy_pll_is_enabled,
0146     .enable     = g12a_ephy_pll_enable,
0147     .disable    = g12a_ephy_pll_disable,
0148     .init       = g12a_ephy_pll_init,
0149 };
0150
0151 static int g12a_enable_internal_mdio(struct g12a_mdio_mux *priv)
0152 {
0153     int ret;
0154
0155     /* Enable the phy clock */
0156     if (!priv->pll_is_enabled) {
0157         ret = clk_prepare_enable(priv->pll);
0158         if (ret)
0159             return ret;
0160     }
0161
0162     priv->pll_is_enabled = true;
0163
0164     /* Initialize ephy control */
0165     writel(EPHY_G12A_ID, priv->regs + ETH_PHY_CNTL0);
0166     writel(FIELD_PREP(PHY_CNTL1_ST_MODE, 3) |
0167            FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) |
0168            FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) |
0169            PHY_CNTL1_CLK_EN |
0170            PHY_CNTL1_CLKFREQ |
0171            PHY_CNTL1_PHY_ENB,
0172            priv->regs + ETH_PHY_CNTL1);
0173     writel(PHY_CNTL2_USE_INTERNAL |
0174            PHY_CNTL2_SMI_SRC_MAC |
0175            PHY_CNTL2_RX_CLK_EPHY,
0176            priv->regs + ETH_PHY_CNTL2);
0177
0178     return 0;
0179 }
0180
0181 static int g12a_enable_external_mdio(struct g12a_mdio_mux *priv)
0182 {
0183     /* Reset the mdio bus mux */
0184     writel_relaxed(0x0, priv->regs + ETH_PHY_CNTL2);
0185
0186     /* Disable the phy clock if enabled */
0187     if (priv->pll_is_enabled) {
0188         clk_disable_unprepare(priv->pll);
0189         priv->pll_is_enabled = false;
0190     }
0191
0192     return 0;
0193 }
0194
0195 static int g12a_mdio_switch_fn(int current_child, int desired_child,
0196                    void *data)
0197 {
0198     struct g12a_mdio_mux *priv = dev_get_drvdata(data);
0199
0200     if (current_child == desired_child)
0201         return 0;
0202
0203     switch (desired_child) {
0204     case MESON_G12A_MDIO_EXTERNAL_ID:
0205         return g12a_enable_external_mdio(priv);
0206     case MESON_G12A_MDIO_INTERNAL_ID:
0207         return g12a_enable_internal_mdio(priv);
0208     default:
0209         return -EINVAL;
0210     }
0211 }
0212
0213 static const struct of_device_id g12a_mdio_mux_match[] = {
0214     { .compatible = "amlogic,g12a-mdio-mux", },
0215     {},
0216 };
0217 MODULE_DEVICE_TABLE(of, g12a_mdio_mux_match);
0218
0219 static int g12a_ephy_glue_clk_register(struct device *dev)
0220 {
0221     struct g12a_mdio_mux *priv = dev_get_drvdata(dev);
0222     const char *parent_names[PLL_MUX_NUM_PARENT];
0223     struct clk_init_data init;
0224     struct g12a_ephy_pll *pll;
0225     struct clk_mux *mux;
0226     struct clk *clk;
0227     char *name;
0228     int i;
0229
0230     /* get the mux parents */
0231     for (i = 0; i < PLL_MUX_NUM_PARENT; i++) {
0232         char in_name[8];
0233
0234         snprintf(in_name, sizeof(in_name), "clkin%d", i);
0235         clk = devm_clk_get(dev, in_name);
0236         if (IS_ERR(clk)) {
0237             if (PTR_ERR(clk) != -EPROBE_DEFER)
0238                 dev_err(dev, "Missing clock %s\n", in_name);
0239             return PTR_ERR(clk);
0240         }
0241
0242         parent_names[i] = __clk_get_name(clk);
0243     }
0244
0245     /* create the input mux */
0246     mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
0247     if (!mux)
0248         return -ENOMEM;
0249
0250     name = kasprintf(GFP_KERNEL, "%s#mux", dev_name(dev));
0251     if (!name)
0252         return -ENOMEM;
0253
0254     init.name = name;
0255     init.ops = &clk_mux_ro_ops;
0256     init.flags = 0;
0257     init.parent_names = parent_names;
0258     init.num_parents = PLL_MUX_NUM_PARENT;
0259
0260     mux->reg = priv->regs + ETH_PLL_CTL0;
0261     mux->shift = __ffs(PLL_CTL0_SEL);
0262     mux->mask = PLL_CTL0_SEL >> mux->shift;
0263     mux->hw.init = &init;
0264
0265     clk = devm_clk_register(dev, &mux->hw);
0266     kfree(name);
0267     if (IS_ERR(clk)) {
0268         dev_err(dev, "failed to register input mux\n");
0269         return PTR_ERR(clk);
0270     }
0271
0272     /* create the pll */
0273     pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
0274     if (!pll)
0275         return -ENOMEM;
0276
0277     name = kasprintf(GFP_KERNEL, "%s#pll", dev_name(dev));
0278     if (!name)
0279         return -ENOMEM;
0280
0281     init.name = name;
0282     init.ops = &g12a_ephy_pll_ops;
0283     init.flags = 0;
0284     parent_names[0] = __clk_get_name(clk);
0285     init.parent_names = parent_names;
0286     init.num_parents = 1;
0287
0288     pll->base = priv->regs;
0289     pll->hw.init = &init;
0290
0291     clk = devm_clk_register(dev, &pll->hw);
0292     kfree(name);
0293     if (IS_ERR(clk)) {
0294         dev_err(dev, "failed to register input mux\n");
0295         return PTR_ERR(clk);
0296     }
0297
0298     priv->pll = clk;
0299
0300     return 0;
0301 }
0302
0303 static int g12a_mdio_mux_probe(struct platform_device *pdev)
0304 {
0305     struct device *dev = &pdev->dev;
0306     struct g12a_mdio_mux *priv;
0307     int ret;
0308
0309     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0310     if (!priv)
0311         return -ENOMEM;
0312
0313     platform_set_drvdata(pdev, priv);
0314
0315     priv->regs = devm_platform_ioremap_resource(pdev, 0);
0316     if (IS_ERR(priv->regs))
0317         return PTR_ERR(priv->regs);
0318
0319     priv->pclk = devm_clk_get(dev, "pclk");
0320     if (IS_ERR(priv->pclk)) {
0321         ret = PTR_ERR(priv->pclk);
0322         if (ret != -EPROBE_DEFER)
0323             dev_err(dev, "failed to get peripheral clock\n");
0324         return ret;
0325     }
0326
0327     /* Make sure the device registers are clocked */
0328     ret = clk_prepare_enable(priv->pclk);
0329     if (ret) {
0330         dev_err(dev, "failed to enable peripheral clock");
0331         return ret;
0332     }
0333
0334     /* Register PLL in CCF */
0335     ret = g12a_ephy_glue_clk_register(dev);
0336     if (ret)
0337         goto err;
0338
0339     ret = mdio_mux_init(dev, dev->of_node, g12a_mdio_switch_fn,
0340                 &priv->mux_handle, dev, NULL);
0341     if (ret) {
0342         if (ret != -EPROBE_DEFER)
0343             dev_err(dev, "mdio multiplexer init failed: %d", ret);
0344         goto err;
0345     }
0346
0347     return 0;
0348
0349 err:
0350     clk_disable_unprepare(priv->pclk);
0351     return ret;
0352 }
0353
0354 static int g12a_mdio_mux_remove(struct platform_device *pdev)
0355 {
0356     struct g12a_mdio_mux *priv = platform_get_drvdata(pdev);
0357
0358     mdio_mux_uninit(priv->mux_handle);
0359
0360     if (priv->pll_is_enabled)
0361         clk_disable_unprepare(priv->pll);
0362
0363     clk_disable_unprepare(priv->pclk);
0364
0365     return 0;
0366 }
0367
0368 static struct platform_driver g12a_mdio_mux_driver = {
0369     .probe      = g12a_mdio_mux_probe,
0370     .remove     = g12a_mdio_mux_remove,
0371     .driver     = {
0372         .name   = "g12a-mdio_mux",
0373         .of_match_table = g12a_mdio_mux_match,
0374     },
0375 };
0376 module_platform_driver(g12a_mdio_mux_driver);
0377
0378 MODULE_DESCRIPTION("Amlogic G12a MDIO multiplexer driver");
0379 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
0380 MODULE_LICENSE("GPL v2");