net/mdio/mdio-mscc-miim.c

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003  * Driver for the MDIO interface of Microsemi network switches.
0004  *
0005  * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
0006  * Copyright (c) 2017 Microsemi Corporation
0007  */
0008
0009 #include <linux/bitops.h>
0010 #include <linux/clk.h>
0011 #include <linux/io.h>
0012 #include <linux/iopoll.h>
0013 #include <linux/kernel.h>
0014 #include <linux/mdio/mdio-mscc-miim.h>
0015 #include <linux/module.h>
0016 #include <linux/of_mdio.h>
0017 #include <linux/phy.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/property.h>
0020 #include <linux/regmap.h>
0021
0022 #define MSCC_MIIM_REG_STATUS        0x0
0023 #define     MSCC_MIIM_STATUS_STAT_PENDING   BIT(2)
0024 #define     MSCC_MIIM_STATUS_STAT_BUSY  BIT(3)
0025 #define MSCC_MIIM_REG_CMD       0x8
0026 #define     MSCC_MIIM_CMD_OPR_WRITE     BIT(1)
0027 #define     MSCC_MIIM_CMD_OPR_READ      BIT(2)
0028 #define     MSCC_MIIM_CMD_WRDATA_SHIFT  4
0029 #define     MSCC_MIIM_CMD_REGAD_SHIFT   20
0030 #define     MSCC_MIIM_CMD_PHYAD_SHIFT   25
0031 #define     MSCC_MIIM_CMD_VLD       BIT(31)
0032 #define MSCC_MIIM_REG_DATA      0xC
0033 #define     MSCC_MIIM_DATA_ERROR        (BIT(16) | BIT(17))
0034 #define MSCC_MIIM_REG_CFG       0x10
0035 #define     MSCC_MIIM_CFG_PRESCALE_MASK GENMASK(7, 0)
0036
0037 #define MSCC_PHY_REG_PHY_CFG    0x0
0038 #define     PHY_CFG_PHY_ENA     (BIT(0) | BIT(1) | BIT(2) | BIT(3))
0039 #define     PHY_CFG_PHY_COMMON_RESET BIT(4)
0040 #define     PHY_CFG_PHY_RESET   (BIT(5) | BIT(6) | BIT(7) | BIT(8))
0041 #define MSCC_PHY_REG_PHY_STATUS 0x4
0042
0043 #define LAN966X_CUPHY_COMMON_CFG    0x0
0044 #define     CUPHY_COMMON_CFG_RESET_N    BIT(0)
0045
0046 struct mscc_miim_info {
0047     unsigned int phy_reset_offset;
0048     unsigned int phy_reset_bits;
0049 };
0050
0051 struct mscc_miim_dev {
0052     struct regmap *regs;
0053     int mii_status_offset;
0054     struct regmap *phy_regs;
0055     const struct mscc_miim_info *info;
0056     struct clk *clk;
0057     u32 bus_freq;
0058 };
0059
0060 /* When high resolution timers aren't built-in: we can't use usleep_range() as
0061  * we would sleep way too long. Use udelay() instead.
0062  */
0063 #define mscc_readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us)\
0064 ({                                    \
0065     if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS))              \
0066         readx_poll_timeout_atomic(op, addr, val, cond, delay_us,  \
0067                       timeout_us);            \
0068     readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us);    \
0069 })
0070
0071 static int mscc_miim_status(struct mii_bus *bus)
0072 {
0073     struct mscc_miim_dev *miim = bus->priv;
0074     int val, ret;
0075
0076     ret = regmap_read(miim->regs,
0077               MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val);
0078     if (ret < 0) {
0079         WARN_ONCE(1, "mscc miim status read error %d\n", ret);
0080         return ret;
0081     }
0082
0083     return val;
0084 }
0085
0086 static int mscc_miim_wait_ready(struct mii_bus *bus)
0087 {
0088     u32 val;
0089
0090     return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
0091                        !(val & MSCC_MIIM_STATUS_STAT_BUSY), 50,
0092                        10000);
0093 }
0094
0095 static int mscc_miim_wait_pending(struct mii_bus *bus)
0096 {
0097     u32 val;
0098
0099     return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
0100                        !(val & MSCC_MIIM_STATUS_STAT_PENDING),
0101                        50, 10000);
0102 }
0103
0104 static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
0105 {
0106     struct mscc_miim_dev *miim = bus->priv;
0107     u32 val;
0108     int ret;
0109
0110     if (regnum & MII_ADDR_C45)
0111         return -EOPNOTSUPP;
0112
0113     ret = mscc_miim_wait_pending(bus);
0114     if (ret)
0115         goto out;
0116
0117     ret = regmap_write(miim->regs,
0118                MSCC_MIIM_REG_CMD + miim->mii_status_offset,
0119                MSCC_MIIM_CMD_VLD |
0120                (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
0121                (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
0122                MSCC_MIIM_CMD_OPR_READ);
0123
0124     if (ret < 0) {
0125         WARN_ONCE(1, "mscc miim write cmd reg error %d\n", ret);
0126         goto out;
0127     }
0128
0129     ret = mscc_miim_wait_ready(bus);
0130     if (ret)
0131         goto out;
0132
0133     ret = regmap_read(miim->regs,
0134               MSCC_MIIM_REG_DATA + miim->mii_status_offset, &val);
0135     if (ret < 0) {
0136         WARN_ONCE(1, "mscc miim read data reg error %d\n", ret);
0137         goto out;
0138     }
0139
0140     if (val & MSCC_MIIM_DATA_ERROR) {
0141         ret = -EIO;
0142         goto out;
0143     }
0144
0145     ret = val & 0xFFFF;
0146 out:
0147     return ret;
0148 }
0149
0150 static int mscc_miim_write(struct mii_bus *bus, int mii_id,
0151                int regnum, u16 value)
0152 {
0153     struct mscc_miim_dev *miim = bus->priv;
0154     int ret;
0155
0156     if (regnum & MII_ADDR_C45)
0157         return -EOPNOTSUPP;
0158
0159     ret = mscc_miim_wait_pending(bus);
0160     if (ret < 0)
0161         goto out;
0162
0163     ret = regmap_write(miim->regs,
0164                MSCC_MIIM_REG_CMD + miim->mii_status_offset,
0165                MSCC_MIIM_CMD_VLD |
0166                (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
0167                (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
0168                (value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
0169                MSCC_MIIM_CMD_OPR_WRITE);
0170
0171     if (ret < 0)
0172         WARN_ONCE(1, "mscc miim write error %d\n", ret);
0173 out:
0174     return ret;
0175 }
0176
0177 static int mscc_miim_reset(struct mii_bus *bus)
0178 {
0179     struct mscc_miim_dev *miim = bus->priv;
0180     unsigned int offset, bits;
0181     int ret;
0182
0183     if (!miim->phy_regs)
0184         return 0;
0185
0186     offset = miim->info->phy_reset_offset;
0187     bits = miim->info->phy_reset_bits;
0188
0189     ret = regmap_update_bits(miim->phy_regs, offset, bits, 0);
0190     if (ret < 0) {
0191         WARN_ONCE(1, "mscc reset set error %d\n", ret);
0192         return ret;
0193     }
0194
0195     ret = regmap_update_bits(miim->phy_regs, offset, bits, bits);
0196     if (ret < 0) {
0197         WARN_ONCE(1, "mscc reset clear error %d\n", ret);
0198         return ret;
0199     }
0200
0201     mdelay(500);
0202
0203     return 0;
0204 }
0205
0206 static const struct regmap_config mscc_miim_regmap_config = {
0207     .reg_bits   = 32,
0208     .val_bits   = 32,
0209     .reg_stride = 4,
0210 };
0211
0212 static const struct regmap_config mscc_miim_phy_regmap_config = {
0213     .reg_bits   = 32,
0214     .val_bits   = 32,
0215     .reg_stride = 4,
0216     .name       = "phy",
0217 };
0218
0219 int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name,
0220             struct regmap *mii_regmap, int status_offset)
0221 {
0222     struct mscc_miim_dev *miim;
0223     struct mii_bus *bus;
0224
0225     bus = devm_mdiobus_alloc_size(dev, sizeof(*miim));
0226     if (!bus)
0227         return -ENOMEM;
0228
0229     bus->name = name;
0230     bus->read = mscc_miim_read;
0231     bus->write = mscc_miim_write;
0232     bus->reset = mscc_miim_reset;
0233     snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev));
0234     bus->parent = dev;
0235
0236     miim = bus->priv;
0237
0238     *pbus = bus;
0239
0240     miim->regs = mii_regmap;
0241     miim->mii_status_offset = status_offset;
0242
0243     *pbus = bus;
0244
0245     return 0;
0246 }
0247 EXPORT_SYMBOL(mscc_miim_setup);
0248
0249 static int mscc_miim_clk_set(struct mii_bus *bus)
0250 {
0251     struct mscc_miim_dev *miim = bus->priv;
0252     unsigned long rate;
0253     u32 div;
0254
0255     /* Keep the current settings */
0256     if (!miim->bus_freq)
0257         return 0;
0258
0259     rate = clk_get_rate(miim->clk);
0260
0261     div = DIV_ROUND_UP(rate, 2 * miim->bus_freq) - 1;
0262     if (div == 0 || div & ~MSCC_MIIM_CFG_PRESCALE_MASK) {
0263         dev_err(&bus->dev, "Incorrect MDIO clock frequency\n");
0264         return -EINVAL;
0265     }
0266
0267     return regmap_update_bits(miim->regs, MSCC_MIIM_REG_CFG,
0268                   MSCC_MIIM_CFG_PRESCALE_MASK, div);
0269 }
0270
0271 static int mscc_miim_probe(struct platform_device *pdev)
0272 {
0273     struct regmap *mii_regmap, *phy_regmap = NULL;
0274     struct device_node *np = pdev->dev.of_node;
0275     struct device *dev = &pdev->dev;
0276     void __iomem *regs, *phy_regs;
0277     struct mscc_miim_dev *miim;
0278     struct resource *res;
0279     struct mii_bus *bus;
0280     int ret;
0281
0282     regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
0283     if (IS_ERR(regs)) {
0284         dev_err(dev, "Unable to map MIIM registers\n");
0285         return PTR_ERR(regs);
0286     }
0287
0288     mii_regmap = devm_regmap_init_mmio(dev, regs, &mscc_miim_regmap_config);
0289
0290     if (IS_ERR(mii_regmap)) {
0291         dev_err(dev, "Unable to create MIIM regmap\n");
0292         return PTR_ERR(mii_regmap);
0293     }
0294
0295     /* This resource is optional */
0296     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0297     if (res) {
0298         phy_regs = devm_ioremap_resource(dev, res);
0299         if (IS_ERR(phy_regs)) {
0300             dev_err(dev, "Unable to map internal phy registers\n");
0301             return PTR_ERR(phy_regs);
0302         }
0303
0304         phy_regmap = devm_regmap_init_mmio(dev, phy_regs,
0305                            &mscc_miim_phy_regmap_config);
0306         if (IS_ERR(phy_regmap)) {
0307             dev_err(dev, "Unable to create phy register regmap\n");
0308             return PTR_ERR(phy_regmap);
0309         }
0310     }
0311
0312     ret = mscc_miim_setup(dev, &bus, "mscc_miim", mii_regmap, 0);
0313     if (ret < 0) {
0314         dev_err(dev, "Unable to setup the MDIO bus\n");
0315         return ret;
0316     }
0317
0318     miim = bus->priv;
0319     miim->phy_regs = phy_regmap;
0320
0321     miim->info = device_get_match_data(dev);
0322     if (!miim->info)
0323         return -EINVAL;
0324
0325     miim->clk = devm_clk_get_optional(dev, NULL);
0326     if (IS_ERR(miim->clk))
0327         return PTR_ERR(miim->clk);
0328
0329     of_property_read_u32(np, "clock-frequency", &miim->bus_freq);
0330
0331     if (miim->bus_freq && !miim->clk) {
0332         dev_err(dev, "cannot use clock-frequency without a clock\n");
0333         return -EINVAL;
0334     }
0335
0336     ret = clk_prepare_enable(miim->clk);
0337     if (ret)
0338         return ret;
0339
0340     ret = mscc_miim_clk_set(bus);
0341     if (ret)
0342         goto out_disable_clk;
0343
0344     ret = of_mdiobus_register(bus, np);
0345     if (ret < 0) {
0346         dev_err(dev, "Cannot register MDIO bus (%d)\n", ret);
0347         goto out_disable_clk;
0348     }
0349
0350     platform_set_drvdata(pdev, bus);
0351
0352     return 0;
0353
0354 out_disable_clk:
0355     clk_disable_unprepare(miim->clk);
0356     return ret;
0357 }
0358
0359 static int mscc_miim_remove(struct platform_device *pdev)
0360 {
0361     struct mii_bus *bus = platform_get_drvdata(pdev);
0362     struct mscc_miim_dev *miim = bus->priv;
0363
0364     clk_disable_unprepare(miim->clk);
0365     mdiobus_unregister(bus);
0366
0367     return 0;
0368 }
0369
0370 static const struct mscc_miim_info mscc_ocelot_miim_info = {
0371     .phy_reset_offset = MSCC_PHY_REG_PHY_CFG,
0372     .phy_reset_bits = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET |
0373               PHY_CFG_PHY_RESET,
0374 };
0375
0376 static const struct mscc_miim_info microchip_lan966x_miim_info = {
0377     .phy_reset_offset = LAN966X_CUPHY_COMMON_CFG,
0378     .phy_reset_bits = CUPHY_COMMON_CFG_RESET_N,
0379 };
0380
0381 static const struct of_device_id mscc_miim_match[] = {
0382     {
0383         .compatible = "mscc,ocelot-miim",
0384         .data = &mscc_ocelot_miim_info
0385     }, {
0386         .compatible = "microchip,lan966x-miim",
0387         .data = &microchip_lan966x_miim_info
0388     },
0389     { }
0390 };
0391 MODULE_DEVICE_TABLE(of, mscc_miim_match);
0392
0393 static struct platform_driver mscc_miim_driver = {
0394     .probe = mscc_miim_probe,
0395     .remove = mscc_miim_remove,
0396     .driver = {
0397         .name = "mscc-miim",
0398         .of_match_table = mscc_miim_match,
0399     },
0400 };
0401
0402 module_platform_driver(mscc_miim_driver);
0403
0404 MODULE_DESCRIPTION("Microsemi MIIM driver");
0405 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
0406 MODULE_LICENSE("Dual MIT/GPL");