net/mdio/mdio-cavium.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2009-2016 Cavium, Inc.
0004  */
0005
0006 enum cavium_mdiobus_mode {
0007     UNINIT = 0,
0008     C22,
0009     C45
0010 };
0011
0012 #define SMI_CMD     0x0
0013 #define SMI_WR_DAT  0x8
0014 #define SMI_RD_DAT  0x10
0015 #define SMI_CLK     0x18
0016 #define SMI_EN      0x20
0017
0018 #ifdef __BIG_ENDIAN_BITFIELD
0019 #define OCT_MDIO_BITFIELD_FIELD(field, more)    \
0020     field;                  \
0021     more
0022
0023 #else
0024 #define OCT_MDIO_BITFIELD_FIELD(field, more)    \
0025     more                    \
0026     field;
0027
0028 #endif
0029
0030 union cvmx_smix_clk {
0031     u64 u64;
0032     struct cvmx_smix_clk_s {
0033       OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
0034       OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
0035       OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
0036       OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
0037       OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
0038       OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
0039       OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
0040       OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
0041       OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
0042       OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
0043       ;))))))))))
0044     } s;
0045 };
0046
0047 union cvmx_smix_cmd {
0048     u64 u64;
0049     struct cvmx_smix_cmd_s {
0050       OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
0051       OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
0052       OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
0053       OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
0054       OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
0055       OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
0056       ;))))))
0057     } s;
0058 };
0059
0060 union cvmx_smix_en {
0061     u64 u64;
0062     struct cvmx_smix_en_s {
0063       OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
0064       OCT_MDIO_BITFIELD_FIELD(u64 en:1,
0065       ;))
0066     } s;
0067 };
0068
0069 union cvmx_smix_rd_dat {
0070     u64 u64;
0071     struct cvmx_smix_rd_dat_s {
0072       OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
0073       OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
0074       OCT_MDIO_BITFIELD_FIELD(u64 val:1,
0075       OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
0076       ;))))
0077     } s;
0078 };
0079
0080 union cvmx_smix_wr_dat {
0081     u64 u64;
0082     struct cvmx_smix_wr_dat_s {
0083       OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
0084       OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
0085       OCT_MDIO_BITFIELD_FIELD(u64 val:1,
0086       OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
0087       ;))))
0088     } s;
0089 };
0090
0091 struct cavium_mdiobus {
0092     struct mii_bus *mii_bus;
0093     void __iomem *register_base;
0094     enum cavium_mdiobus_mode mode;
0095 };
0096
0097 #ifdef CONFIG_CAVIUM_OCTEON_SOC
0098
0099 #include <asm/octeon/octeon.h>
0100
0101 static inline void oct_mdio_writeq(u64 val, void __iomem *addr)
0102 {
0103     cvmx_write_csr((u64 __force)addr, val);
0104 }
0105
0106 static inline u64 oct_mdio_readq(void __iomem *addr)
0107 {
0108     return cvmx_read_csr((u64 __force)addr);
0109 }
0110 #else
0111 #include <linux/io-64-nonatomic-lo-hi.h>
0112
0113 #define oct_mdio_writeq(val, addr)  writeq(val, addr)
0114 #define oct_mdio_readq(addr)        readq(addr)
0115 #endif
0116
0117 int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum);
0118 int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val);