net/ipa/gsi_reg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
0004  * Copyright (C) 2018-2021 Linaro Ltd.
0005  */
0006 #ifndef _GSI_REG_H_
0007 #define _GSI_REG_H_
0008
0009 /* === Only "gsi.c" should include this file === */
0010
0011 #include <linux/bits.h>
0012
0013 /**
0014  * DOC: GSI Registers
0015  *
0016  * GSI registers are located within the "gsi" address space defined by Device
0017  * Tree.  The offset of each register within that space is specified by
0018  * symbols defined below.  The GSI address space is mapped to virtual memory
0019  * space in gsi_init().  All GSI registers are 32 bits wide.
0020  *
0021  * Each register type is duplicated for a number of instances of something.
0022  * For example, each GSI channel has its own set of registers defining its
0023  * configuration.  The offset to a channel's set of registers is computed
0024  * based on a "base" offset plus an additional "stride" amount computed
0025  * from the channel's ID.  For such registers, the offset is computed by a
0026  * function-like macro that takes a parameter used in the computation.
0027  *
0028  * The offset of a register dependent on execution environment is computed
0029  * by a macro that is supplied a parameter "ee".  The "ee" value is a member
0030  * of the gsi_ee_id enumerated type.
0031  *
0032  * The offset of a channel register is computed by a macro that is supplied a
0033  * parameter "ch".  The "ch" value is a channel id whose maximum value is 30
0034  * (though the actual limit is hardware-dependent).
0035  *
0036  * The offset of an event register is computed by a macro that is supplied a
0037  * parameter "ev".  The "ev" value is an event id whose maximum value is 15
0038  * (though the actual limit is hardware-dependent).
0039  */
0040
0041 /* GSI EE registers as a group are shifted downward by a fixed constant amount
0042  * for IPA versions 4.5 and beyond.  This applies to all GSI registers we use
0043  * *except* the ones that disable inter-EE interrupts for channels and event
0044  * channels.
0045  *
0046  * The "raw" (not adjusted) GSI register range is mapped, and a pointer to
0047  * the mapped range is held in gsi->virt_raw.  The inter-EE interrupt
0048  * registers are accessed using that pointer.
0049  *
0050  * Most registers are accessed using gsi->virt, which is a copy of the "raw"
0051  * pointer, adjusted downward by the fixed amount.
0052  */
0053 #define GSI_EE_REG_ADJUST           0x0000d000  /* IPA v4.5+ */
0054
0055 /* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */
0056
0057 #define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \
0058             GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
0059 #define GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(ee) \
0060             (0x0000c020 + 0x1000 * (ee))
0061
0062 #define GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET \
0063             GSI_INTER_EE_N_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
0064 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \
0065             (0x0000c024 + 0x1000 * (ee))
0066
0067 /* All other register offsets are relative to gsi->virt */
0068
0069 /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */
0070 enum gsi_channel_type {
0071     GSI_CHANNEL_TYPE_MHI            = 0x0,
0072     GSI_CHANNEL_TYPE_XHCI           = 0x1,
0073     GSI_CHANNEL_TYPE_GPI            = 0x2,
0074     GSI_CHANNEL_TYPE_XDCI           = 0x3,
0075     GSI_CHANNEL_TYPE_WDI2           = 0x4,
0076     GSI_CHANNEL_TYPE_GCI            = 0x5,
0077     GSI_CHANNEL_TYPE_WDI3           = 0x6,
0078     GSI_CHANNEL_TYPE_MHIP           = 0x7,
0079     GSI_CHANNEL_TYPE_AQC            = 0x8,
0080     GSI_CHANNEL_TYPE_11AD           = 0x9,
0081 };
0082
0083 #define GSI_CH_C_CNTXT_0_OFFSET(ch) \
0084         GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP)
0085 #define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \
0086         (0x0001c000 + 0x4000 * (ee) + 0x80 * (ch))
0087 #define CHTYPE_PROTOCOL_FMASK       GENMASK(2, 0)
0088 #define CHTYPE_DIR_FMASK        GENMASK(3, 3)
0089 #define EE_FMASK            GENMASK(7, 4)
0090 #define CHID_FMASK          GENMASK(12, 8)
0091 /* The next field is present for IPA v4.5 and above */
0092 #define CHTYPE_PROTOCOL_MSB_FMASK   GENMASK(13, 13)
0093 #define ERINDEX_FMASK           GENMASK(18, 14)
0094 #define CHSTATE_FMASK           GENMASK(23, 20)
0095 #define ELEMENT_SIZE_FMASK      GENMASK(31, 24)
0096
0097 /* Encoded value for CH_C_CNTXT_0 register channel protocol fields */
0098 static inline u32
0099 chtype_protocol_encoded(enum ipa_version version, enum gsi_channel_type type)
0100 {
0101     u32 val;
0102
0103     val = u32_encode_bits(type, CHTYPE_PROTOCOL_FMASK);
0104     if (version < IPA_VERSION_4_5)
0105         return val;
0106
0107     /* Encode upper bit(s) as well */
0108     type >>= hweight32(CHTYPE_PROTOCOL_FMASK);
0109     val |= u32_encode_bits(type, CHTYPE_PROTOCOL_MSB_FMASK);
0110
0111     return val;
0112 }
0113
0114 #define GSI_CH_C_CNTXT_1_OFFSET(ch) \
0115         GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP)
0116 #define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \
0117         (0x0001c004 + 0x4000 * (ee) + 0x80 * (ch))
0118
0119 /* Encoded value for CH_C_CNTXT_1 register R_LENGTH field */
0120 static inline u32 r_length_encoded(enum ipa_version version, u32 length)
0121 {
0122     if (version < IPA_VERSION_4_9)
0123         return u32_encode_bits(length, GENMASK(15, 0));
0124     return u32_encode_bits(length, GENMASK(19, 0));
0125 }
0126
0127 #define GSI_CH_C_CNTXT_2_OFFSET(ch) \
0128         GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP)
0129 #define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \
0130         (0x0001c008 + 0x4000 * (ee) + 0x80 * (ch))
0131
0132 #define GSI_CH_C_CNTXT_3_OFFSET(ch) \
0133         GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP)
0134 #define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \
0135         (0x0001c00c + 0x4000 * (ee) + 0x80 * (ch))
0136
0137 #define GSI_CH_C_QOS_OFFSET(ch) \
0138         GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP)
0139 #define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \
0140         (0x0001c05c + 0x4000 * (ee) + 0x80 * (ch))
0141 #define WRR_WEIGHT_FMASK        GENMASK(3, 0)
0142 #define MAX_PREFETCH_FMASK      GENMASK(8, 8)
0143 #define USE_DB_ENG_FMASK        GENMASK(9, 9)
0144 /* The next field is only present for IPA v4.0, v4.1, and v4.2 */
0145 #define USE_ESCAPE_BUF_ONLY_FMASK   GENMASK(10, 10)
0146 /* The next two fields are present for IPA v4.5 and above */
0147 #define PREFETCH_MODE_FMASK     GENMASK(13, 10)
0148 #define EMPTY_LVL_THRSHOLD_FMASK    GENMASK(23, 16)
0149 /* The next field is present for IPA v4.9 and above */
0150 #define DB_IN_BYTES         GENMASK(24, 24)
0151
0152 /** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */
0153 enum gsi_prefetch_mode {
0154     GSI_USE_PREFETCH_BUFS           = 0x0,
0155     GSI_ESCAPE_BUF_ONLY         = 0x1,
0156     GSI_SMART_PREFETCH          = 0x2,
0157     GSI_FREE_PREFETCH           = 0x3,
0158 };
0159
0160 #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \
0161         GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP)
0162 #define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \
0163         (0x0001c060 + 0x4000 * (ee) + 0x80 * (ch))
0164
0165 #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \
0166         GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP)
0167 #define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \
0168         (0x0001c064 + 0x4000 * (ee) + 0x80 * (ch))
0169
0170 #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \
0171         GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP)
0172 #define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \
0173         (0x0001c068 + 0x4000 * (ee) + 0x80 * (ch))
0174
0175 #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \
0176         GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP)
0177 #define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \
0178         (0x0001c06c + 0x4000 * (ee) + 0x80 * (ch))
0179
0180 #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \
0181         GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP)
0182 #define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \
0183         (0x0001d000 + 0x4000 * (ee) + 0x80 * (ev))
0184 /* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */
0185 #define EV_CHTYPE_FMASK         GENMASK(3, 0)
0186 #define EV_EE_FMASK         GENMASK(7, 4)
0187 #define EV_EVCHID_FMASK         GENMASK(15, 8)
0188 #define EV_INTYPE_FMASK         GENMASK(16, 16)
0189 #define EV_CHSTATE_FMASK        GENMASK(23, 20)
0190 #define EV_ELEMENT_SIZE_FMASK       GENMASK(31, 24)
0191
0192 #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \
0193         GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP)
0194 #define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \
0195         (0x0001d004 + 0x4000 * (ee) + 0x80 * (ev))
0196 /* Encoded value for EV_CH_C_CNTXT_1 register EV_R_LENGTH field */
0197 static inline u32 ev_r_length_encoded(enum ipa_version version, u32 length)
0198 {
0199     if (version < IPA_VERSION_4_9)
0200         return u32_encode_bits(length, GENMASK(15, 0));
0201     return u32_encode_bits(length, GENMASK(19, 0));
0202 }
0203
0204 #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \
0205         GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP)
0206 #define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \
0207         (0x0001d008 + 0x4000 * (ee) + 0x80 * (ev))
0208
0209 #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \
0210         GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP)
0211 #define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \
0212         (0x0001d00c + 0x4000 * (ee) + 0x80 * (ev))
0213
0214 #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \
0215         GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP)
0216 #define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \
0217         (0x0001d010 + 0x4000 * (ee) + 0x80 * (ev))
0218
0219 #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \
0220         GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP)
0221 #define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \
0222         (0x0001d020 + 0x4000 * (ee) + 0x80 * (ev))
0223 #define MODT_FMASK          GENMASK(15, 0)
0224 #define MODC_FMASK          GENMASK(23, 16)
0225 #define MOD_CNT_FMASK           GENMASK(31, 24)
0226
0227 #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \
0228         GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP)
0229 #define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \
0230         (0x0001d024 + 0x4000 * (ee) + 0x80 * (ev))
0231
0232 #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \
0233         GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP)
0234 #define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \
0235         (0x0001d028 + 0x4000 * (ee) + 0x80 * (ev))
0236
0237 #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \
0238         GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP)
0239 #define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \
0240         (0x0001d02c + 0x4000 * (ee) + 0x80 * (ev))
0241
0242 #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \
0243         GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP)
0244 #define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \
0245         (0x0001d030 + 0x4000 * (ee) + 0x80 * (ev))
0246
0247 #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \
0248         GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP)
0249 #define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \
0250         (0x0001d034 + 0x4000 * (ee) + 0x80 * (ev))
0251
0252 #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \
0253         GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP)
0254 #define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \
0255         (0x0001d048 + 0x4000 * (ee) + 0x80 * (ev))
0256
0257 #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \
0258         GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP)
0259 #define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \
0260         (0x0001d04c + 0x4000 * (ee) + 0x80 * (ev))
0261
0262 #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \
0263         GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP)
0264 #define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \
0265             (0x0001e000 + 0x4000 * (ee) + 0x08 * (ch))
0266
0267 #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \
0268             GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP)
0269 #define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \
0270             (0x0001e100 + 0x4000 * (ee) + 0x08 * (ev))
0271
0272 #define GSI_GSI_STATUS_OFFSET \
0273             GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP)
0274 #define GSI_EE_N_GSI_STATUS_OFFSET(ee) \
0275             (0x0001f000 + 0x4000 * (ee))
0276 #define ENABLED_FMASK           GENMASK(0, 0)
0277
0278 #define GSI_CH_CMD_OFFSET \
0279             GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP)
0280 #define GSI_EE_N_CH_CMD_OFFSET(ee) \
0281             (0x0001f008 + 0x4000 * (ee))
0282 #define CH_CHID_FMASK           GENMASK(7, 0)
0283 #define CH_OPCODE_FMASK         GENMASK(31, 24)
0284
0285 /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */
0286 enum gsi_ch_cmd_opcode {
0287     GSI_CH_ALLOCATE             = 0x0,
0288     GSI_CH_START                = 0x1,
0289     GSI_CH_STOP             = 0x2,
0290     GSI_CH_RESET                = 0x9,
0291     GSI_CH_DE_ALLOC             = 0xa,
0292     GSI_CH_DB_STOP              = 0xb,
0293 };
0294
0295 #define GSI_EV_CH_CMD_OFFSET \
0296             GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP)
0297 #define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \
0298             (0x0001f010 + 0x4000 * (ee))
0299 #define EV_CHID_FMASK           GENMASK(7, 0)
0300 #define EV_OPCODE_FMASK         GENMASK(31, 24)
0301
0302 /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */
0303 enum gsi_evt_cmd_opcode {
0304     GSI_EVT_ALLOCATE            = 0x0,
0305     GSI_EVT_RESET               = 0x9,
0306     GSI_EVT_DE_ALLOC            = 0xa,
0307 };
0308
0309 #define GSI_GENERIC_CMD_OFFSET \
0310             GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP)
0311 #define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \
0312             (0x0001f018 + 0x4000 * (ee))
0313 #define GENERIC_OPCODE_FMASK        GENMASK(4, 0)
0314 #define GENERIC_CHID_FMASK      GENMASK(9, 5)
0315 #define GENERIC_EE_FMASK        GENMASK(13, 10)
0316 #define GENERIC_PARAMS_FMASK        GENMASK(31, 24) /* IPA v4.11+ */
0317
0318 /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */
0319 enum gsi_generic_cmd_opcode {
0320     GSI_GENERIC_HALT_CHANNEL        = 0x1,
0321     GSI_GENERIC_ALLOCATE_CHANNEL        = 0x2,
0322     GSI_GENERIC_ENABLE_FLOW_CONTROL     = 0x3,  /* IPA v4.2+ */
0323     GSI_GENERIC_DISABLE_FLOW_CONTROL    = 0x4,  /* IPA v4.2+ */
0324     GSI_GENERIC_QUERY_FLOW_CONTROL      = 0x5,  /* IPA v4.11+ */
0325 };
0326
0327 /* The next register is present for IPA v3.5.1 and above */
0328 #define GSI_GSI_HW_PARAM_2_OFFSET \
0329             GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP)
0330 #define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \
0331             (0x0001f040 + 0x4000 * (ee))
0332 #define IRAM_SIZE_FMASK         GENMASK(2, 0)
0333 #define NUM_CH_PER_EE_FMASK     GENMASK(7, 3)
0334 #define NUM_EV_PER_EE_FMASK     GENMASK(12, 8)
0335 #define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13)
0336 #define GSI_CH_FULL_LOGIC_FMASK     GENMASK(14, 14)
0337 /* Fields below are present for IPA v4.0 and above */
0338 #define GSI_USE_SDMA_FMASK      GENMASK(15, 15)
0339 #define GSI_SDMA_N_INT_FMASK        GENMASK(18, 16)
0340 #define GSI_SDMA_MAX_BURST_FMASK    GENMASK(26, 19)
0341 #define GSI_SDMA_N_IOVEC_FMASK      GENMASK(29, 27)
0342 /* Fields below are present for IPA v4.2 and above */
0343 #define GSI_USE_RD_WR_ENG_FMASK     GENMASK(30, 30)
0344 #define GSI_USE_INTER_EE_FMASK      GENMASK(31, 31)
0345
0346 /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */
0347 enum gsi_iram_size {
0348     IRAM_SIZE_ONE_KB            = 0x0,
0349     IRAM_SIZE_TWO_KB            = 0x1,
0350     /* The next two values are available for IPA v4.0 and above */
0351     IRAM_SIZE_TWO_N_HALF_KB         = 0x2,
0352     IRAM_SIZE_THREE_KB          = 0x3,
0353     /* The next two values are available for IPA v4.5 and above */
0354     IRAM_SIZE_THREE_N_HALF_KB       = 0x4,
0355     IRAM_SIZE_FOUR_KB           = 0x5,
0356 };
0357
0358 /* IRQ condition for each type is cleared by writing type-specific register */
0359 #define GSI_CNTXT_TYPE_IRQ_OFFSET \
0360             GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP)
0361 #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \
0362             (0x0001f080 + 0x4000 * (ee))
0363 #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \
0364             GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP)
0365 #define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \
0366             (0x0001f088 + 0x4000 * (ee))
0367
0368 /* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */
0369 enum gsi_irq_type_id {
0370     GSI_CH_CTRL     = 0x0,  /* channel allocation, etc.  */
0371     GSI_EV_CTRL     = 0x1,  /* event ring allocation, etc. */
0372     GSI_GLOB_EE     = 0x2,  /* global/general event */
0373     GSI_IEOB        = 0x3,  /* TRE completion */
0374     GSI_INTER_EE_CH_CTRL    = 0x4,  /* remote-issued stop/reset (unused) */
0375     GSI_INTER_EE_EV_CTRL    = 0x5,  /* remote-issued event reset (unused) */
0376     GSI_GENERAL     = 0x6,  /* general-purpose event */
0377 };
0378
0379 #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \
0380             GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
0381 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \
0382             (0x0001f090 + 0x4000 * (ee))
0383
0384 #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \
0385             GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
0386 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \
0387             (0x0001f094 + 0x4000 * (ee))
0388
0389 #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \
0390             GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
0391 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \
0392             (0x0001f098 + 0x4000 * (ee))
0393
0394 #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \
0395             GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
0396 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \
0397             (0x0001f09c + 0x4000 * (ee))
0398
0399 #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \
0400             GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
0401 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \
0402             (0x0001f0a0 + 0x4000 * (ee))
0403
0404 #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \
0405             GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
0406 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \
0407             (0x0001f0a4 + 0x4000 * (ee))
0408
0409 #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \
0410             GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP)
0411 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \
0412             (0x0001f0b0 + 0x4000 * (ee))
0413
0414 #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \
0415             GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP)
0416 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \
0417             (0x0001f0b8 + 0x4000 * (ee))
0418
0419 #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \
0420             GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP)
0421 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \
0422             (0x0001f0c0 + 0x4000 * (ee))
0423
0424 #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \
0425             GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP)
0426 #define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \
0427             (0x0001f100 + 0x4000 * (ee))
0428 #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \
0429             GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP)
0430 #define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \
0431             (0x0001f108 + 0x4000 * (ee))
0432 #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \
0433             GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP)
0434 #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \
0435             (0x0001f110 + 0x4000 * (ee))
0436 /* Values here are bit positions in the GLOB_IRQ_* registers */
0437 enum gsi_global_irq_id {
0438     ERROR_INT               = 0x0,
0439     GP_INT1                 = 0x1,
0440     GP_INT2                 = 0x2,
0441     GP_INT3                 = 0x3,
0442 };
0443
0444 #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
0445             GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
0446 #define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \
0447             (0x0001f118 + 0x4000 * (ee))
0448 #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \
0449             GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP)
0450 #define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \
0451             (0x0001f120 + 0x4000 * (ee))
0452 #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \
0453             GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP)
0454 #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \
0455             (0x0001f128 + 0x4000 * (ee))
0456 /* Values here are bit positions in the (general) GSI_IRQ_* registers */
0457 enum gsi_general_id {
0458     BREAK_POINT             = 0x0,
0459     BUS_ERROR               = 0x1,
0460     CMD_FIFO_OVRFLOW            = 0x2,
0461     MCS_STACK_OVRFLOW           = 0x3,
0462 };
0463
0464 #define GSI_CNTXT_INTSET_OFFSET \
0465             GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP)
0466 #define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \
0467             (0x0001f180 + 0x4000 * (ee))
0468 #define INTYPE_FMASK            GENMASK(0, 0)
0469
0470 #define GSI_ERROR_LOG_OFFSET \
0471             GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP)
0472 #define GSI_EE_N_ERROR_LOG_OFFSET(ee) \
0473             (0x0001f200 + 0x4000 * (ee))
0474
0475 /* Fields below are present for IPA v3.5.1 and above */
0476 #define ERR_ARG3_FMASK          GENMASK(3, 0)
0477 #define ERR_ARG2_FMASK          GENMASK(7, 4)
0478 #define ERR_ARG1_FMASK          GENMASK(11, 8)
0479 #define ERR_CODE_FMASK          GENMASK(15, 12)
0480 #define ERR_VIRT_IDX_FMASK      GENMASK(23, 19)
0481 #define ERR_TYPE_FMASK          GENMASK(27, 24)
0482 #define ERR_EE_FMASK            GENMASK(31, 28)
0483
0484 /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */
0485 enum gsi_err_code {
0486     GSI_INVALID_TRE             = 0x1,
0487     GSI_OUT_OF_BUFFERS          = 0x2,
0488     GSI_OUT_OF_RESOURCES            = 0x3,
0489     GSI_UNSUPPORTED_INTER_EE_OP     = 0x4,
0490     GSI_EVT_RING_EMPTY          = 0x5,
0491     GSI_NON_ALLOCATED_EVT_ACCESS        = 0x6,
0492     /* 7 is not assigned */
0493     GSI_HWO_1               = 0x8,
0494 };
0495
0496 /** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */
0497 enum gsi_err_type {
0498     GSI_ERR_TYPE_GLOB           = 0x1,
0499     GSI_ERR_TYPE_CHAN           = 0x2,
0500     GSI_ERR_TYPE_EVT            = 0x3,
0501 };
0502
0503 #define GSI_ERROR_LOG_CLR_OFFSET \
0504             GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP)
0505 #define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \
0506             (0x0001f210 + 0x4000 * (ee))
0507
0508 #define GSI_CNTXT_SCRATCH_0_OFFSET \
0509             GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP)
0510 #define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \
0511             (0x0001f400 + 0x4000 * (ee))
0512 #define INTER_EE_RESULT_FMASK       GENMASK(2, 0)
0513 #define GENERIC_EE_RESULT_FMASK     GENMASK(7, 5)
0514
0515 /** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */
0516 enum gsi_generic_ee_result {
0517     GENERIC_EE_SUCCESS          = 0x1,
0518     GENERIC_EE_INCORRECT_CHANNEL_STATE  = 0x2,
0519     GENERIC_EE_INCORRECT_DIRECTION      = 0x3,
0520     GENERIC_EE_INCORRECT_CHANNEL_TYPE   = 0x4,
0521     GENERIC_EE_INCORRECT_CHANNEL        = 0x5,
0522     GENERIC_EE_RETRY            = 0x6,
0523     GENERIC_EE_NO_RESOURCES         = 0x7,
0524 };
0525
0526 #endif  /* _GSI_REG_H_ */