ipa/data/ipa_data-v3.1.c

0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
0004  * Copyright (C) 2019-2021 Linaro Ltd.
0005  */
0006
0007 #include <linux/log2.h>
0008
0009 #include "../gsi.h"
0010 #include "../ipa_data.h"
0011 #include "../ipa_endpoint.h"
0012 #include "../ipa_mem.h"
0013
0014 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.1 */
0015 enum ipa_resource_type {
0016     /* Source resource types; first must have value 0 */
0017     IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS      = 0,
0018     IPA_RESOURCE_TYPE_SRC_HDR_SECTORS,
0019     IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER,
0020     IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
0021     IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
0022     IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS,
0023     IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
0024     IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
0025
0026     /* Destination resource types; first must have value 0 */
0027     IPA_RESOURCE_TYPE_DST_DATA_SECTORS      = 0,
0028     IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS,
0029     IPA_RESOURCE_TYPE_DST_DPS_DMARS,
0030 };
0031
0032 /* Resource groups used for an SoC having IPA v3.1 */
0033 enum ipa_rsrc_group_id {
0034     /* Source resource group identifiers */
0035     IPA_RSRC_GROUP_SRC_UL       = 0,
0036     IPA_RSRC_GROUP_SRC_DL,
0037     IPA_RSRC_GROUP_SRC_DIAG,
0038     IPA_RSRC_GROUP_SRC_DMA,
0039     IPA_RSRC_GROUP_SRC_UNUSED,
0040     IPA_RSRC_GROUP_SRC_UC_RX_Q,
0041     IPA_RSRC_GROUP_SRC_COUNT,   /* Last in set; not a source group */
0042
0043     /* Destination resource group identifiers */
0044     IPA_RSRC_GROUP_DST_UL       = 0,
0045     IPA_RSRC_GROUP_DST_DL,
0046     IPA_RSRC_GROUP_DST_DIAG_DPL,
0047     IPA_RSRC_GROUP_DST_DMA,
0048     IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL,
0049     IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE,
0050     IPA_RSRC_GROUP_DST_COUNT,   /* Last; not a destination group */
0051 };
0052
0053 /* QSB configuration data for an SoC having IPA v3.1 */
0054 static const struct ipa_qsb_data ipa_qsb_data[] = {
0055     [IPA_QSB_MASTER_DDR] = {
0056         .max_writes = 8,
0057         .max_reads  = 8,
0058     },
0059     [IPA_QSB_MASTER_PCIE] = {
0060         .max_writes = 2,
0061         .max_reads  = 8,
0062     },
0063 };
0064
0065 /* Endpoint data for an SoC having IPA v3.1 */
0066 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
0067     [IPA_ENDPOINT_AP_COMMAND_TX] = {
0068         .ee_id      = GSI_EE_AP,
0069         .channel_id = 6,
0070         .endpoint_id    = 22,
0071         .toward_ipa = true,
0072         .channel = {
0073             .tre_count  = 256,
0074             .event_count    = 256,
0075             .tlv_count  = 18,
0076         },
0077         .endpoint = {
0078             .config = {
0079                 .resource_group = IPA_RSRC_GROUP_SRC_UL,
0080                 .dma_mode   = true,
0081                 .dma_endpoint   = IPA_ENDPOINT_AP_LAN_RX,
0082                 .tx = {
0083                     .seq_type = IPA_SEQ_DMA,
0084                 },
0085             },
0086         },
0087     },
0088     [IPA_ENDPOINT_AP_LAN_RX] = {
0089         .ee_id      = GSI_EE_AP,
0090         .channel_id = 7,
0091         .endpoint_id    = 15,
0092         .toward_ipa = false,
0093         .channel = {
0094             .tre_count  = 256,
0095             .event_count    = 256,
0096             .tlv_count  = 8,
0097         },
0098         .endpoint = {
0099             .config = {
0100                 .resource_group = IPA_RSRC_GROUP_SRC_UL,
0101                 .aggregation    = true,
0102                 .status_enable  = true,
0103                 .rx = {
0104                     .buffer_size    = 8192,
0105                     .pad_align  = ilog2(sizeof(u32)),
0106                     .aggr_time_limit = 500,
0107                 },
0108             },
0109         },
0110     },
0111     [IPA_ENDPOINT_AP_MODEM_TX] = {
0112         .ee_id      = GSI_EE_AP,
0113         .channel_id = 5,
0114         .endpoint_id    = 3,
0115         .toward_ipa = true,
0116         .channel = {
0117             .tre_count  = 512,
0118             .event_count    = 512,
0119             .tlv_count  = 16,
0120         },
0121         .endpoint = {
0122             .filter_support = true,
0123             .config = {
0124                 .resource_group = IPA_RSRC_GROUP_SRC_UL,
0125                 .checksum   = true,
0126                 .qmap       = true,
0127                 .status_enable  = true,
0128                 .tx = {
0129                     .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
0130                     .status_endpoint =
0131                         IPA_ENDPOINT_MODEM_AP_RX,
0132                 },
0133             },
0134         },
0135     },
0136     [IPA_ENDPOINT_AP_MODEM_RX] = {
0137         .ee_id      = GSI_EE_AP,
0138         .channel_id = 8,
0139         .endpoint_id    = 16,
0140         .toward_ipa = false,
0141         .channel = {
0142             .tre_count  = 256,
0143             .event_count    = 256,
0144             .tlv_count  = 8,
0145         },
0146         .endpoint = {
0147             .config = {
0148                 .resource_group = IPA_RSRC_GROUP_DST_DL,
0149                 .checksum   = true,
0150                 .qmap       = true,
0151                 .aggregation    = true,
0152                 .rx = {
0153                     .buffer_size    = 8192,
0154                     .aggr_time_limit = 500,
0155                     .aggr_close_eof = true,
0156                 },
0157             },
0158         },
0159     },
0160     [IPA_ENDPOINT_MODEM_LAN_TX] = {
0161         .ee_id      = GSI_EE_MODEM,
0162         .channel_id = 4,
0163         .endpoint_id    = 9,
0164         .toward_ipa = true,
0165         .endpoint = {
0166             .filter_support = true,
0167         },
0168     },
0169     [IPA_ENDPOINT_MODEM_AP_TX] = {
0170         .ee_id      = GSI_EE_MODEM,
0171         .channel_id = 0,
0172         .endpoint_id    = 5,
0173         .toward_ipa = true,
0174         .endpoint = {
0175             .filter_support = true,
0176         },
0177     },
0178     [IPA_ENDPOINT_MODEM_AP_RX] = {
0179         .ee_id      = GSI_EE_MODEM,
0180         .channel_id = 5,
0181         .endpoint_id    = 18,
0182         .toward_ipa = false,
0183     },
0184 };
0185
0186 /* Source resource configuration data for an SoC having IPA v3.1 */
0187 static const struct ipa_resource ipa_resource_src[] = {
0188     [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
0189         .limits[IPA_RSRC_GROUP_SRC_UL] = {
0190             .min = 3,   .max = 255,
0191         },
0192         .limits[IPA_RSRC_GROUP_SRC_DL] = {
0193             .min = 3,   .max = 255,
0194         },
0195         .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
0196             .min = 1,   .max = 255,
0197         },
0198         .limits[IPA_RSRC_GROUP_SRC_DMA] = {
0199             .min = 1,   .max = 255,
0200         },
0201         .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
0202             .min = 2,   .max = 255,
0203         },
0204     },
0205     [IPA_RESOURCE_TYPE_SRC_HDR_SECTORS] = {
0206         .limits[IPA_RSRC_GROUP_SRC_UL] = {
0207             .min = 0,   .max = 255,
0208         },
0209         .limits[IPA_RSRC_GROUP_SRC_DL] = {
0210             .min = 0,   .max = 255,
0211         },
0212         .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
0213             .min = 0,   .max = 255,
0214         },
0215         .limits[IPA_RSRC_GROUP_SRC_DMA] = {
0216             .min = 0,   .max = 255,
0217         },
0218         .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
0219             .min = 0,   .max = 255,
0220         },
0221     },
0222     [IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER] = {
0223         .limits[IPA_RSRC_GROUP_SRC_UL] = {
0224             .min = 0,   .max = 255,
0225         },
0226         .limits[IPA_RSRC_GROUP_SRC_DL] = {
0227             .min = 0,   .max = 255,
0228         },
0229         .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
0230             .min = 0,   .max = 255,
0231         },
0232         .limits[IPA_RSRC_GROUP_SRC_DMA] = {
0233             .min = 0,   .max = 255,
0234         },
0235         .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
0236             .min = 0,   .max = 255,
0237         },
0238     },
0239     [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
0240         .limits[IPA_RSRC_GROUP_SRC_UL] = {
0241             .min = 14,  .max = 14,
0242         },
0243         .limits[IPA_RSRC_GROUP_SRC_DL] = {
0244             .min = 16,  .max = 16,
0245         },
0246         .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
0247             .min = 5,   .max = 5,
0248         },
0249         .limits[IPA_RSRC_GROUP_SRC_DMA] = {
0250             .min = 5,   .max = 5,
0251         },
0252         .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
0253             .min = 8,   .max = 8,
0254         },
0255     },
0256     [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
0257         .limits[IPA_RSRC_GROUP_SRC_UL] = {
0258             .min = 19,  .max = 19,
0259         },
0260         .limits[IPA_RSRC_GROUP_SRC_DL] = {
0261             .min = 26,  .max = 26,
0262         },
0263         .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
0264             .min = 5,   .max = 5,   /* 3 downstream */
0265         },
0266         .limits[IPA_RSRC_GROUP_SRC_DMA] = {
0267             .min = 5,   .max = 5,   /* 7 downstream */
0268         },
0269         .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
0270             .min = 8,   .max = 8,
0271         },
0272     },
0273     [IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS] = {
0274         .limits[IPA_RSRC_GROUP_SRC_UL] = {
0275             .min = 0,   .max = 255,
0276         },
0277         .limits[IPA_RSRC_GROUP_SRC_DL] = {
0278             .min = 0,   .max = 255,
0279         },
0280         .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
0281             .min = 0,   .max = 255,
0282         },
0283         .limits[IPA_RSRC_GROUP_SRC_DMA] = {
0284             .min = 0,   .max = 255,
0285         },
0286         .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
0287             .min = 0,   .max = 255,
0288         },
0289     },
0290     [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
0291         .limits[IPA_RSRC_GROUP_SRC_UL] = {
0292             .min = 0,   .max = 255,
0293         },
0294         .limits[IPA_RSRC_GROUP_SRC_DL] = {
0295             .min = 0,   .max = 255,
0296         },
0297         .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
0298             .min = 0,   .max = 255,
0299         },
0300         .limits[IPA_RSRC_GROUP_SRC_DMA] = {
0301             .min = 0,   .max = 255,
0302         },
0303         .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
0304             .min = 0,   .max = 255,
0305         },
0306     },
0307     [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
0308         .limits[IPA_RSRC_GROUP_SRC_UL] = {
0309             .min = 19,  .max = 19,
0310         },
0311         .limits[IPA_RSRC_GROUP_SRC_DL] = {
0312             .min = 26,  .max = 26,
0313         },
0314         .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
0315             .min = 5,   .max = 5,
0316         },
0317         .limits[IPA_RSRC_GROUP_SRC_DMA] = {
0318             .min = 5,   .max = 5,
0319         },
0320         .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
0321             .min = 8,   .max = 8,
0322         },
0323     },
0324 };
0325
0326 /* Destination resource configuration data for an SoC having IPA v3.1 */
0327 static const struct ipa_resource ipa_resource_dst[] = {
0328     [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
0329         .limits[IPA_RSRC_GROUP_DST_UL] = {
0330             .min = 3,   .max = 3,   /* 2 downstream */
0331         },
0332         .limits[IPA_RSRC_GROUP_DST_DL] = {
0333             .min = 3,   .max = 3,
0334         },
0335         .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
0336             .min = 1,   .max = 1,   /* 0 downstream */
0337         },
0338         /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */
0339         .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
0340             .min = 3,   .max = 3,
0341         },
0342         .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = {
0343             .min = 3,   .max = 3,
0344         },
0345     },
0346     [IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS] = {
0347         .limits[IPA_RSRC_GROUP_DST_UL] = {
0348             .min = 0,   .max = 255,
0349         },
0350         .limits[IPA_RSRC_GROUP_DST_DL] = {
0351             .min = 0,   .max = 255,
0352         },
0353         .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
0354             .min = 0,   .max = 255,
0355         },
0356         .limits[IPA_RSRC_GROUP_DST_DMA] = {
0357             .min = 0,   .max = 255,
0358         },
0359         .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
0360             .min = 0,   .max = 255,
0361         },
0362         .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = {
0363             .min = 0,   .max = 255,
0364         },
0365     },
0366     [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
0367         .limits[IPA_RSRC_GROUP_DST_UL] = {
0368             .min = 1,   .max = 1,
0369         },
0370         .limits[IPA_RSRC_GROUP_DST_DL] = {
0371             .min = 1,   .max = 1,
0372         },
0373         .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
0374             .min = 1,   .max = 1,
0375         },
0376         .limits[IPA_RSRC_GROUP_DST_DMA] = {
0377             .min = 1,   .max = 1,
0378         },
0379         .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
0380             .min = 1,   .max = 1,
0381         },
0382     },
0383 };
0384
0385 /* Resource configuration data for an SoC having IPA v3.1 */
0386 static const struct ipa_resource_data ipa_resource_data = {
0387     .rsrc_group_src_count   = IPA_RSRC_GROUP_SRC_COUNT,
0388     .rsrc_group_dst_count   = IPA_RSRC_GROUP_DST_COUNT,
0389     .resource_src_count = ARRAY_SIZE(ipa_resource_src),
0390     .resource_src       = ipa_resource_src,
0391     .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
0392     .resource_dst       = ipa_resource_dst,
0393 };
0394
0395 /* IPA-resident memory region data for an SoC having IPA v3.1 */
0396 static const struct ipa_mem ipa_mem_local_data[] = {
0397     {
0398         .id     = IPA_MEM_UC_SHARED,
0399         .offset     = 0x0000,
0400         .size       = 0x0080,
0401         .canary_count   = 0,
0402     },
0403     {
0404         .id     = IPA_MEM_UC_INFO,
0405         .offset     = 0x0080,
0406         .size       = 0x0200,
0407         .canary_count   = 0,
0408     },
0409     {
0410         .id     = IPA_MEM_V4_FILTER_HASHED,
0411         .offset     = 0x0288,
0412         .size       = 0x0078,
0413         .canary_count   = 2,
0414     },
0415     {
0416         .id     = IPA_MEM_V4_FILTER,
0417         .offset     = 0x0308,
0418         .size       = 0x0078,
0419         .canary_count   = 2,
0420     },
0421     {
0422         .id     = IPA_MEM_V6_FILTER_HASHED,
0423         .offset     = 0x0388,
0424         .size       = 0x0078,
0425         .canary_count   = 2,
0426     },
0427     {
0428         .id     = IPA_MEM_V6_FILTER,
0429         .offset     = 0x0408,
0430         .size       = 0x0078,
0431         .canary_count   = 2,
0432     },
0433     {
0434         .id     = IPA_MEM_V4_ROUTE_HASHED,
0435         .offset     = 0x0488,
0436         .size       = 0x0078,
0437         .canary_count   = 2,
0438     },
0439     {
0440         .id     = IPA_MEM_V4_ROUTE,
0441         .offset     = 0x0508,
0442         .size       = 0x0078,
0443         .canary_count   = 2,
0444     },
0445     {
0446         .id     = IPA_MEM_V6_ROUTE_HASHED,
0447         .offset     = 0x0588,
0448         .size       = 0x0078,
0449         .canary_count   = 2,
0450     },
0451     {
0452         .id     = IPA_MEM_V6_ROUTE,
0453         .offset     = 0x0608,
0454         .size       = 0x0078,
0455         .canary_count   = 2,
0456     },
0457     {
0458         .id     = IPA_MEM_MODEM_HEADER,
0459         .offset     = 0x0688,
0460         .size       = 0x0140,
0461         .canary_count   = 2,
0462     },
0463     {
0464         .id     = IPA_MEM_MODEM_PROC_CTX,
0465         .offset     = 0x07d0,
0466         .size       = 0x0200,
0467         .canary_count   = 2,
0468     },
0469     {
0470         .id     = IPA_MEM_AP_PROC_CTX,
0471         .offset     = 0x09d0,
0472         .size       = 0x0200,
0473         .canary_count   = 0,
0474     },
0475     {
0476         .id     = IPA_MEM_MODEM,
0477         .offset     = 0x0bd8,
0478         .size       = 0x1424,
0479         .canary_count   = 0,
0480     },
0481     {
0482         .id     = IPA_MEM_END_MARKER,
0483         .offset     = 0x2000,
0484         .size       = 0,
0485         .canary_count   = 1,
0486     },
0487 };
0488
0489 /* Memory configuration data for an SoC having IPA v3.1 */
0490 static const struct ipa_mem_data ipa_mem_data = {
0491     .local_count    = ARRAY_SIZE(ipa_mem_local_data),
0492     .local      = ipa_mem_local_data,
0493     .imem_addr  = 0x146bd000,
0494     .imem_size  = 0x00002000,
0495     .smem_id    = 497,
0496     .smem_size  = 0x00002000,
0497 };
0498
0499 /* Interconnect bandwidths are in 1000 byte/second units */
0500 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
0501     {
0502         .name           = "memory",
0503         .peak_bandwidth     = 640000,   /* 640 MBps */
0504         .average_bandwidth  = 80000,    /* 80 MBps */
0505     },
0506     {
0507         .name           = "imem",
0508         .peak_bandwidth     = 640000,   /* 640 MBps */
0509         .average_bandwidth  = 80000,    /* 80 MBps */
0510     },
0511     /* Average bandwidth is unused for the next interconnect */
0512     {
0513         .name           = "config",
0514         .peak_bandwidth     = 80000,    /* 80 MBps */
0515         .average_bandwidth  = 0,        /* unused */
0516     },
0517 };
0518
0519 /* Clock and interconnect configuration data for an SoC having IPA v3.1 */
0520 static const struct ipa_power_data ipa_power_data = {
0521     .core_clock_rate    = 16 * 1000 * 1000, /* Hz */
0522     .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
0523     .interconnect_data  = ipa_interconnect_data,
0524 };
0525
0526 /* Configuration data for an SoC having IPA v3.1 */
0527 const struct ipa_data ipa_data_v3_1 = {
0528     .version    = IPA_VERSION_3_1,
0529     .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK,
0530     .qsb_count  = ARRAY_SIZE(ipa_qsb_data),
0531     .qsb_data   = ipa_qsb_data,
0532     .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
0533     .endpoint_data  = ipa_gsi_endpoint_data,
0534     .resource_data  = &ipa_resource_data,
0535     .mem_data   = &ipa_mem_data,
0536     .power_data = &ipa_power_data,
0537 };