Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
0004  *
0005  * Copyright (C) 2012 Alan Ott <alan@signal11.us>
0006  *                    Signal 11 Software
0007  */
0008 
0009 #include <linux/spi/spi.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/mod_devicetable.h>
0012 #include <linux/module.h>
0013 #include <linux/regmap.h>
0014 #include <linux/ieee802154.h>
0015 #include <linux/irq.h>
0016 #include <net/cfg802154.h>
0017 #include <net/mac802154.h>
0018 
0019 /* MRF24J40 Short Address Registers */
0020 #define REG_RXMCR   0x00  /* Receive MAC control */
0021 #define BIT_PROMI   BIT(0)
0022 #define BIT_ERRPKT  BIT(1)
0023 #define BIT_NOACKRSP    BIT(5)
0024 #define BIT_PANCOORD    BIT(3)
0025 
0026 #define REG_PANIDL  0x01  /* PAN ID (low) */
0027 #define REG_PANIDH  0x02  /* PAN ID (high) */
0028 #define REG_SADRL   0x03  /* Short address (low) */
0029 #define REG_SADRH   0x04  /* Short address (high) */
0030 #define REG_EADR0   0x05  /* Long address (low) (high is EADR7) */
0031 #define REG_EADR1   0x06
0032 #define REG_EADR2   0x07
0033 #define REG_EADR3   0x08
0034 #define REG_EADR4   0x09
0035 #define REG_EADR5   0x0A
0036 #define REG_EADR6   0x0B
0037 #define REG_EADR7   0x0C
0038 #define REG_RXFLUSH 0x0D
0039 #define REG_ORDER   0x10
0040 #define REG_TXMCR   0x11  /* Transmit MAC control */
0041 #define TXMCR_MIN_BE_SHIFT      3
0042 #define TXMCR_MIN_BE_MASK       0x18
0043 #define TXMCR_CSMA_RETRIES_SHIFT    0
0044 #define TXMCR_CSMA_RETRIES_MASK     0x07
0045 
0046 #define REG_ACKTMOUT    0x12
0047 #define REG_ESLOTG1 0x13
0048 #define REG_SYMTICKL    0x14
0049 #define REG_SYMTICKH    0x15
0050 #define REG_PACON0  0x16  /* Power Amplifier Control */
0051 #define REG_PACON1  0x17  /* Power Amplifier Control */
0052 #define REG_PACON2  0x18  /* Power Amplifier Control */
0053 #define REG_TXBCON0 0x1A
0054 #define REG_TXNCON  0x1B  /* Transmit Normal FIFO Control */
0055 #define BIT_TXNTRIG BIT(0)
0056 #define BIT_TXNSECEN    BIT(1)
0057 #define BIT_TXNACKREQ   BIT(2)
0058 
0059 #define REG_TXG1CON 0x1C
0060 #define REG_TXG2CON 0x1D
0061 #define REG_ESLOTG23    0x1E
0062 #define REG_ESLOTG45    0x1F
0063 #define REG_ESLOTG67    0x20
0064 #define REG_TXPEND  0x21
0065 #define REG_WAKECON 0x22
0066 #define REG_FROMOFFSET  0x23
0067 #define REG_TXSTAT  0x24  /* TX MAC Status Register */
0068 #define REG_TXBCON1 0x25
0069 #define REG_GATECLK 0x26
0070 #define REG_TXTIME  0x27
0071 #define REG_HSYMTMRL    0x28
0072 #define REG_HSYMTMRH    0x29
0073 #define REG_SOFTRST 0x2A  /* Soft Reset */
0074 #define REG_SECCON0 0x2C
0075 #define REG_SECCON1 0x2D
0076 #define REG_TXSTBL  0x2E  /* TX Stabilization */
0077 #define REG_RXSR    0x30
0078 #define REG_INTSTAT 0x31  /* Interrupt Status */
0079 #define BIT_TXNIF   BIT(0)
0080 #define BIT_RXIF    BIT(3)
0081 #define BIT_SECIF   BIT(4)
0082 #define BIT_SECIGNORE   BIT(7)
0083 
0084 #define REG_INTCON  0x32  /* Interrupt Control */
0085 #define BIT_TXNIE   BIT(0)
0086 #define BIT_RXIE    BIT(3)
0087 #define BIT_SECIE   BIT(4)
0088 
0089 #define REG_GPIO    0x33  /* GPIO */
0090 #define REG_TRISGPIO    0x34  /* GPIO direction */
0091 #define REG_SLPACK  0x35
0092 #define REG_RFCTL   0x36  /* RF Control Mode Register */
0093 #define BIT_RFRST   BIT(2)
0094 
0095 #define REG_SECCR2  0x37
0096 #define REG_BBREG0  0x38
0097 #define REG_BBREG1  0x39  /* Baseband Registers */
0098 #define BIT_RXDECINV    BIT(2)
0099 
0100 #define REG_BBREG2  0x3A  /* */
0101 #define BBREG2_CCA_MODE_SHIFT   6
0102 #define BBREG2_CCA_MODE_MASK    0xc0
0103 
0104 #define REG_BBREG3  0x3B
0105 #define REG_BBREG4  0x3C
0106 #define REG_BBREG6  0x3E  /* */
0107 #define REG_CCAEDTH 0x3F  /* Energy Detection Threshold */
0108 
0109 /* MRF24J40 Long Address Registers */
0110 #define REG_RFCON0  0x200  /* RF Control Registers */
0111 #define RFCON0_CH_SHIFT 4
0112 #define RFCON0_CH_MASK  0xf0
0113 #define RFOPT_RECOMMEND 3
0114 
0115 #define REG_RFCON1  0x201
0116 #define REG_RFCON2  0x202
0117 #define REG_RFCON3  0x203
0118 
0119 #define TXPWRL_MASK 0xc0
0120 #define TXPWRL_SHIFT    6
0121 #define TXPWRL_30   0x3
0122 #define TXPWRL_20   0x2
0123 #define TXPWRL_10   0x1
0124 #define TXPWRL_0    0x0
0125 
0126 #define TXPWRS_MASK 0x38
0127 #define TXPWRS_SHIFT    3
0128 #define TXPWRS_6_3  0x7
0129 #define TXPWRS_4_9  0x6
0130 #define TXPWRS_3_7  0x5
0131 #define TXPWRS_2_8  0x4
0132 #define TXPWRS_1_9  0x3
0133 #define TXPWRS_1_2  0x2
0134 #define TXPWRS_0_5  0x1
0135 #define TXPWRS_0    0x0
0136 
0137 #define REG_RFCON5  0x205
0138 #define REG_RFCON6  0x206
0139 #define REG_RFCON7  0x207
0140 #define REG_RFCON8  0x208
0141 #define REG_SLPCAL0 0x209
0142 #define REG_SLPCAL1 0x20A
0143 #define REG_SLPCAL2 0x20B
0144 #define REG_RFSTATE 0x20F
0145 #define REG_RSSI    0x210
0146 #define REG_SLPCON0 0x211  /* Sleep Clock Control Registers */
0147 #define BIT_INTEDGE BIT(1)
0148 
0149 #define REG_SLPCON1 0x220
0150 #define REG_WAKETIMEL   0x222  /* Wake-up Time Match Value Low */
0151 #define REG_WAKETIMEH   0x223  /* Wake-up Time Match Value High */
0152 #define REG_REMCNTL 0x224
0153 #define REG_REMCNTH 0x225
0154 #define REG_MAINCNT0    0x226
0155 #define REG_MAINCNT1    0x227
0156 #define REG_MAINCNT2    0x228
0157 #define REG_MAINCNT3    0x229
0158 #define REG_TESTMODE    0x22F  /* Test mode */
0159 #define REG_ASSOEAR0    0x230
0160 #define REG_ASSOEAR1    0x231
0161 #define REG_ASSOEAR2    0x232
0162 #define REG_ASSOEAR3    0x233
0163 #define REG_ASSOEAR4    0x234
0164 #define REG_ASSOEAR5    0x235
0165 #define REG_ASSOEAR6    0x236
0166 #define REG_ASSOEAR7    0x237
0167 #define REG_ASSOSAR0    0x238
0168 #define REG_ASSOSAR1    0x239
0169 #define REG_UNONCE0 0x240
0170 #define REG_UNONCE1 0x241
0171 #define REG_UNONCE2 0x242
0172 #define REG_UNONCE3 0x243
0173 #define REG_UNONCE4 0x244
0174 #define REG_UNONCE5 0x245
0175 #define REG_UNONCE6 0x246
0176 #define REG_UNONCE7 0x247
0177 #define REG_UNONCE8 0x248
0178 #define REG_UNONCE9 0x249
0179 #define REG_UNONCE10    0x24A
0180 #define REG_UNONCE11    0x24B
0181 #define REG_UNONCE12    0x24C
0182 #define REG_RX_FIFO 0x300  /* Receive FIFO */
0183 
0184 /* Device configuration: Only channels 11-26 on page 0 are supported. */
0185 #define MRF24J40_CHAN_MIN 11
0186 #define MRF24J40_CHAN_MAX 26
0187 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
0188               - ((u32)1 << MRF24J40_CHAN_MIN))
0189 
0190 #define TX_FIFO_SIZE 128 /* From datasheet */
0191 #define RX_FIFO_SIZE 144 /* From datasheet */
0192 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
0193 
0194 enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
0195 
0196 /* Device Private Data */
0197 struct mrf24j40 {
0198     struct spi_device *spi;
0199     struct ieee802154_hw *hw;
0200 
0201     struct regmap *regmap_short;
0202     struct regmap *regmap_long;
0203 
0204     /* for writing txfifo */
0205     struct spi_message tx_msg;
0206     u8 tx_hdr_buf[2];
0207     struct spi_transfer tx_hdr_trx;
0208     u8 tx_len_buf[2];
0209     struct spi_transfer tx_len_trx;
0210     struct spi_transfer tx_buf_trx;
0211     struct sk_buff *tx_skb;
0212 
0213     /* post transmit message to send frame out  */
0214     struct spi_message tx_post_msg;
0215     u8 tx_post_buf[2];
0216     struct spi_transfer tx_post_trx;
0217 
0218     /* for protect/unprotect/read length rxfifo */
0219     struct spi_message rx_msg;
0220     u8 rx_buf[3];
0221     struct spi_transfer rx_trx;
0222 
0223     /* receive handling */
0224     struct spi_message rx_buf_msg;
0225     u8 rx_addr_buf[2];
0226     struct spi_transfer rx_addr_trx;
0227     u8 rx_lqi_buf[2];
0228     struct spi_transfer rx_lqi_trx;
0229     u8 rx_fifo_buf[RX_FIFO_SIZE];
0230     struct spi_transfer rx_fifo_buf_trx;
0231 
0232     /* isr handling for reading intstat */
0233     struct spi_message irq_msg;
0234     u8 irq_buf[2];
0235     struct spi_transfer irq_trx;
0236 };
0237 
0238 /* regmap information for short address register access */
0239 #define MRF24J40_SHORT_WRITE    0x01
0240 #define MRF24J40_SHORT_READ 0x00
0241 #define MRF24J40_SHORT_NUMREGS  0x3F
0242 
0243 /* regmap information for long address register access */
0244 #define MRF24J40_LONG_ACCESS    0x80
0245 #define MRF24J40_LONG_NUMREGS   0x38F
0246 
0247 /* Read/Write SPI Commands for Short and Long Address registers. */
0248 #define MRF24J40_READSHORT(reg) ((reg) << 1)
0249 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
0250 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
0251 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
0252 
0253 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
0254 #define MAX_SPI_SPEED_HZ 10000000
0255 
0256 #define printdev(X) (&X->spi->dev)
0257 
0258 static bool
0259 mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
0260 {
0261     switch (reg) {
0262     case REG_RXMCR:
0263     case REG_PANIDL:
0264     case REG_PANIDH:
0265     case REG_SADRL:
0266     case REG_SADRH:
0267     case REG_EADR0:
0268     case REG_EADR1:
0269     case REG_EADR2:
0270     case REG_EADR3:
0271     case REG_EADR4:
0272     case REG_EADR5:
0273     case REG_EADR6:
0274     case REG_EADR7:
0275     case REG_RXFLUSH:
0276     case REG_ORDER:
0277     case REG_TXMCR:
0278     case REG_ACKTMOUT:
0279     case REG_ESLOTG1:
0280     case REG_SYMTICKL:
0281     case REG_SYMTICKH:
0282     case REG_PACON0:
0283     case REG_PACON1:
0284     case REG_PACON2:
0285     case REG_TXBCON0:
0286     case REG_TXNCON:
0287     case REG_TXG1CON:
0288     case REG_TXG2CON:
0289     case REG_ESLOTG23:
0290     case REG_ESLOTG45:
0291     case REG_ESLOTG67:
0292     case REG_TXPEND:
0293     case REG_WAKECON:
0294     case REG_FROMOFFSET:
0295     case REG_TXBCON1:
0296     case REG_GATECLK:
0297     case REG_TXTIME:
0298     case REG_HSYMTMRL:
0299     case REG_HSYMTMRH:
0300     case REG_SOFTRST:
0301     case REG_SECCON0:
0302     case REG_SECCON1:
0303     case REG_TXSTBL:
0304     case REG_RXSR:
0305     case REG_INTCON:
0306     case REG_TRISGPIO:
0307     case REG_GPIO:
0308     case REG_RFCTL:
0309     case REG_SECCR2:
0310     case REG_SLPACK:
0311     case REG_BBREG0:
0312     case REG_BBREG1:
0313     case REG_BBREG2:
0314     case REG_BBREG3:
0315     case REG_BBREG4:
0316     case REG_BBREG6:
0317     case REG_CCAEDTH:
0318         return true;
0319     default:
0320         return false;
0321     }
0322 }
0323 
0324 static bool
0325 mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)
0326 {
0327     bool rc;
0328 
0329     /* all writeable are also readable */
0330     rc = mrf24j40_short_reg_writeable(dev, reg);
0331     if (rc)
0332         return rc;
0333 
0334     /* readonly regs */
0335     switch (reg) {
0336     case REG_TXSTAT:
0337     case REG_INTSTAT:
0338         return true;
0339     default:
0340         return false;
0341     }
0342 }
0343 
0344 static bool
0345 mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)
0346 {
0347     /* can be changed during runtime */
0348     switch (reg) {
0349     case REG_TXSTAT:
0350     case REG_INTSTAT:
0351     case REG_RXFLUSH:
0352     case REG_TXNCON:
0353     case REG_SOFTRST:
0354     case REG_RFCTL:
0355     case REG_TXBCON0:
0356     case REG_TXG1CON:
0357     case REG_TXG2CON:
0358     case REG_TXBCON1:
0359     case REG_SECCON0:
0360     case REG_RXSR:
0361     case REG_SLPACK:
0362     case REG_SECCR2:
0363     case REG_BBREG6:
0364     /* use them in spi_async and regmap so it's volatile */
0365     case REG_BBREG1:
0366         return true;
0367     default:
0368         return false;
0369     }
0370 }
0371 
0372 static bool
0373 mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)
0374 {
0375     /* don't clear irq line on read */
0376     switch (reg) {
0377     case REG_INTSTAT:
0378         return true;
0379     default:
0380         return false;
0381     }
0382 }
0383 
0384 static const struct regmap_config mrf24j40_short_regmap = {
0385     .name = "mrf24j40_short",
0386     .reg_bits = 7,
0387     .val_bits = 8,
0388     .pad_bits = 1,
0389     .write_flag_mask = MRF24J40_SHORT_WRITE,
0390     .read_flag_mask = MRF24J40_SHORT_READ,
0391     .cache_type = REGCACHE_RBTREE,
0392     .max_register = MRF24J40_SHORT_NUMREGS,
0393     .writeable_reg = mrf24j40_short_reg_writeable,
0394     .readable_reg = mrf24j40_short_reg_readable,
0395     .volatile_reg = mrf24j40_short_reg_volatile,
0396     .precious_reg = mrf24j40_short_reg_precious,
0397 };
0398 
0399 static bool
0400 mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)
0401 {
0402     switch (reg) {
0403     case REG_RFCON0:
0404     case REG_RFCON1:
0405     case REG_RFCON2:
0406     case REG_RFCON3:
0407     case REG_RFCON5:
0408     case REG_RFCON6:
0409     case REG_RFCON7:
0410     case REG_RFCON8:
0411     case REG_SLPCAL2:
0412     case REG_SLPCON0:
0413     case REG_SLPCON1:
0414     case REG_WAKETIMEL:
0415     case REG_WAKETIMEH:
0416     case REG_REMCNTL:
0417     case REG_REMCNTH:
0418     case REG_MAINCNT0:
0419     case REG_MAINCNT1:
0420     case REG_MAINCNT2:
0421     case REG_MAINCNT3:
0422     case REG_TESTMODE:
0423     case REG_ASSOEAR0:
0424     case REG_ASSOEAR1:
0425     case REG_ASSOEAR2:
0426     case REG_ASSOEAR3:
0427     case REG_ASSOEAR4:
0428     case REG_ASSOEAR5:
0429     case REG_ASSOEAR6:
0430     case REG_ASSOEAR7:
0431     case REG_ASSOSAR0:
0432     case REG_ASSOSAR1:
0433     case REG_UNONCE0:
0434     case REG_UNONCE1:
0435     case REG_UNONCE2:
0436     case REG_UNONCE3:
0437     case REG_UNONCE4:
0438     case REG_UNONCE5:
0439     case REG_UNONCE6:
0440     case REG_UNONCE7:
0441     case REG_UNONCE8:
0442     case REG_UNONCE9:
0443     case REG_UNONCE10:
0444     case REG_UNONCE11:
0445     case REG_UNONCE12:
0446         return true;
0447     default:
0448         return false;
0449     }
0450 }
0451 
0452 static bool
0453 mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)
0454 {
0455     bool rc;
0456 
0457     /* all writeable are also readable */
0458     rc = mrf24j40_long_reg_writeable(dev, reg);
0459     if (rc)
0460         return rc;
0461 
0462     /* readonly regs */
0463     switch (reg) {
0464     case REG_SLPCAL0:
0465     case REG_SLPCAL1:
0466     case REG_RFSTATE:
0467     case REG_RSSI:
0468         return true;
0469     default:
0470         return false;
0471     }
0472 }
0473 
0474 static bool
0475 mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)
0476 {
0477     /* can be changed during runtime */
0478     switch (reg) {
0479     case REG_SLPCAL0:
0480     case REG_SLPCAL1:
0481     case REG_SLPCAL2:
0482     case REG_RFSTATE:
0483     case REG_RSSI:
0484     case REG_MAINCNT3:
0485         return true;
0486     default:
0487         return false;
0488     }
0489 }
0490 
0491 static const struct regmap_config mrf24j40_long_regmap = {
0492     .name = "mrf24j40_long",
0493     .reg_bits = 11,
0494     .val_bits = 8,
0495     .pad_bits = 5,
0496     .write_flag_mask = MRF24J40_LONG_ACCESS,
0497     .read_flag_mask = MRF24J40_LONG_ACCESS,
0498     .cache_type = REGCACHE_RBTREE,
0499     .max_register = MRF24J40_LONG_NUMREGS,
0500     .writeable_reg = mrf24j40_long_reg_writeable,
0501     .readable_reg = mrf24j40_long_reg_readable,
0502     .volatile_reg = mrf24j40_long_reg_volatile,
0503 };
0504 
0505 static int mrf24j40_long_regmap_write(void *context, const void *data,
0506                       size_t count)
0507 {
0508     struct spi_device *spi = context;
0509     u8 buf[3];
0510 
0511     if (count > 3)
0512         return -EINVAL;
0513 
0514     /* regmap supports read/write mask only in frist byte
0515      * long write access need to set the 12th bit, so we
0516      * make special handling for write.
0517      */
0518     memcpy(buf, data, count);
0519     buf[1] |= (1 << 4);
0520 
0521     return spi_write(spi, buf, count);
0522 }
0523 
0524 static int
0525 mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,
0526               void *val, size_t val_size)
0527 {
0528     struct spi_device *spi = context;
0529 
0530     return spi_write_then_read(spi, reg, reg_size, val, val_size);
0531 }
0532 
0533 static const struct regmap_bus mrf24j40_long_regmap_bus = {
0534     .write = mrf24j40_long_regmap_write,
0535     .read = mrf24j40_long_regmap_read,
0536     .reg_format_endian_default = REGMAP_ENDIAN_BIG,
0537     .val_format_endian_default = REGMAP_ENDIAN_BIG,
0538 };
0539 
0540 static void write_tx_buf_complete(void *context)
0541 {
0542     struct mrf24j40 *devrec = context;
0543     __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
0544     u8 val = BIT_TXNTRIG;
0545     int ret;
0546 
0547     if (ieee802154_is_secen(fc))
0548         val |= BIT_TXNSECEN;
0549 
0550     if (ieee802154_is_ackreq(fc))
0551         val |= BIT_TXNACKREQ;
0552 
0553     devrec->tx_post_msg.complete = NULL;
0554     devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
0555     devrec->tx_post_buf[1] = val;
0556 
0557     ret = spi_async(devrec->spi, &devrec->tx_post_msg);
0558     if (ret)
0559         dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");
0560 }
0561 
0562 /* This function relies on an undocumented write method. Once a write command
0563    and address is set, as many bytes of data as desired can be clocked into
0564    the device. The datasheet only shows setting one byte at a time. */
0565 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
0566             const u8 *data, size_t length)
0567 {
0568     u16 cmd;
0569     int ret;
0570 
0571     /* Range check the length. 2 bytes are used for the length fields.*/
0572     if (length > TX_FIFO_SIZE-2) {
0573         dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
0574         length = TX_FIFO_SIZE-2;
0575     }
0576 
0577     cmd = MRF24J40_WRITELONG(reg);
0578     devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;
0579     devrec->tx_hdr_buf[1] = cmd & 0xff;
0580     devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
0581     devrec->tx_len_buf[1] = length; /* Total length */
0582     devrec->tx_buf_trx.tx_buf = data;
0583     devrec->tx_buf_trx.len = length;
0584 
0585     ret = spi_async(devrec->spi, &devrec->tx_msg);
0586     if (ret)
0587         dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
0588 
0589     return ret;
0590 }
0591 
0592 static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
0593 {
0594     struct mrf24j40 *devrec = hw->priv;
0595 
0596     dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
0597     devrec->tx_skb = skb;
0598 
0599     return write_tx_buf(devrec, 0x000, skb->data, skb->len);
0600 }
0601 
0602 static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
0603 {
0604     /* TODO: */
0605     pr_warn("mrf24j40: ed not implemented\n");
0606     *level = 0;
0607     return 0;
0608 }
0609 
0610 static int mrf24j40_start(struct ieee802154_hw *hw)
0611 {
0612     struct mrf24j40 *devrec = hw->priv;
0613 
0614     dev_dbg(printdev(devrec), "start\n");
0615 
0616     /* Clear TXNIE and RXIE. Enable interrupts */
0617     return regmap_update_bits(devrec->regmap_short, REG_INTCON,
0618                   BIT_TXNIE | BIT_RXIE | BIT_SECIE, 0);
0619 }
0620 
0621 static void mrf24j40_stop(struct ieee802154_hw *hw)
0622 {
0623     struct mrf24j40 *devrec = hw->priv;
0624 
0625     dev_dbg(printdev(devrec), "stop\n");
0626 
0627     /* Set TXNIE and RXIE. Disable Interrupts */
0628     regmap_update_bits(devrec->regmap_short, REG_INTCON,
0629                BIT_TXNIE | BIT_RXIE, BIT_TXNIE | BIT_RXIE);
0630 }
0631 
0632 static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
0633 {
0634     struct mrf24j40 *devrec = hw->priv;
0635     u8 val;
0636     int ret;
0637 
0638     dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
0639 
0640     WARN_ON(page != 0);
0641     WARN_ON(channel < MRF24J40_CHAN_MIN);
0642     WARN_ON(channel > MRF24J40_CHAN_MAX);
0643 
0644     /* Set Channel TODO */
0645     val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND;
0646     ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0,
0647                  RFCON0_CH_MASK, val);
0648     if (ret)
0649         return ret;
0650 
0651     /* RF Reset */
0652     ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST,
0653                  BIT_RFRST);
0654     if (ret)
0655         return ret;
0656 
0657     ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0);
0658     if (!ret)
0659         udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
0660 
0661     return ret;
0662 }
0663 
0664 static int mrf24j40_filter(struct ieee802154_hw *hw,
0665                struct ieee802154_hw_addr_filt *filt,
0666                unsigned long changed)
0667 {
0668     struct mrf24j40 *devrec = hw->priv;
0669 
0670     dev_dbg(printdev(devrec), "filter\n");
0671 
0672     if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
0673         /* Short Addr */
0674         u8 addrh, addrl;
0675 
0676         addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
0677         addrl = le16_to_cpu(filt->short_addr) & 0xff;
0678 
0679         regmap_write(devrec->regmap_short, REG_SADRH, addrh);
0680         regmap_write(devrec->regmap_short, REG_SADRL, addrl);
0681         dev_dbg(printdev(devrec),
0682             "Set short addr to %04hx\n", filt->short_addr);
0683     }
0684 
0685     if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
0686         /* Device Address */
0687         u8 i, addr[8];
0688 
0689         memcpy(addr, &filt->ieee_addr, 8);
0690         for (i = 0; i < 8; i++)
0691             regmap_write(devrec->regmap_short, REG_EADR0 + i,
0692                      addr[i]);
0693 
0694 #ifdef DEBUG
0695         pr_debug("Set long addr to: ");
0696         for (i = 0; i < 8; i++)
0697             pr_debug("%02hhx ", addr[7 - i]);
0698         pr_debug("\n");
0699 #endif
0700     }
0701 
0702     if (changed & IEEE802154_AFILT_PANID_CHANGED) {
0703         /* PAN ID */
0704         u8 panidl, panidh;
0705 
0706         panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
0707         panidl = le16_to_cpu(filt->pan_id) & 0xff;
0708         regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
0709         regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
0710 
0711         dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
0712     }
0713 
0714     if (changed & IEEE802154_AFILT_PANC_CHANGED) {
0715         /* Pan Coordinator */
0716         u8 val;
0717         int ret;
0718 
0719         if (filt->pan_coord)
0720             val = BIT_PANCOORD;
0721         else
0722             val = 0;
0723         ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
0724                      BIT_PANCOORD, val);
0725         if (ret)
0726             return ret;
0727 
0728         /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
0729          * REG_ORDER is maintained as default (no beacon/superframe).
0730          */
0731 
0732         dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
0733             filt->pan_coord ? "on" : "off");
0734     }
0735 
0736     return 0;
0737 }
0738 
0739 static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
0740 {
0741     int ret;
0742 
0743     /* Turn back on reception of packets off the air. */
0744     devrec->rx_msg.complete = NULL;
0745     devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
0746     devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */
0747     ret = spi_async(devrec->spi, &devrec->rx_msg);
0748     if (ret)
0749         dev_err(printdev(devrec), "failed to unlock rx buffer\n");
0750 }
0751 
0752 static void mrf24j40_handle_rx_read_buf_complete(void *context)
0753 {
0754     struct mrf24j40 *devrec = context;
0755     u8 len = devrec->rx_buf[2];
0756     u8 rx_local_buf[RX_FIFO_SIZE];
0757     struct sk_buff *skb;
0758 
0759     memcpy(rx_local_buf, devrec->rx_fifo_buf, len);
0760     mrf24j40_handle_rx_read_buf_unlock(devrec);
0761 
0762     skb = dev_alloc_skb(IEEE802154_MTU);
0763     if (!skb) {
0764         dev_err(printdev(devrec), "failed to allocate skb\n");
0765         return;
0766     }
0767 
0768     skb_put_data(skb, rx_local_buf, len);
0769     ieee802154_rx_irqsafe(devrec->hw, skb, 0);
0770 
0771 #ifdef DEBUG
0772      print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1,
0773             rx_local_buf, len, 0);
0774      pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
0775           devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);
0776 #endif
0777 }
0778 
0779 static void mrf24j40_handle_rx_read_buf(void *context)
0780 {
0781     struct mrf24j40 *devrec = context;
0782     u16 cmd;
0783     int ret;
0784 
0785     /* if length is invalid read the full MTU */
0786     if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))
0787         devrec->rx_buf[2] = IEEE802154_MTU;
0788 
0789     cmd = MRF24J40_READLONG(REG_RX_FIFO + 1);
0790     devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;
0791     devrec->rx_addr_buf[1] = cmd & 0xff;
0792     devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];
0793     ret = spi_async(devrec->spi, &devrec->rx_buf_msg);
0794     if (ret) {
0795         dev_err(printdev(devrec), "failed to read rx buffer\n");
0796         mrf24j40_handle_rx_read_buf_unlock(devrec);
0797     }
0798 }
0799 
0800 static void mrf24j40_handle_rx_read_len(void *context)
0801 {
0802     struct mrf24j40 *devrec = context;
0803     u16 cmd;
0804     int ret;
0805 
0806     /* read the length of received frame */
0807     devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;
0808     devrec->rx_trx.len = 3;
0809     cmd = MRF24J40_READLONG(REG_RX_FIFO);
0810     devrec->rx_buf[0] = cmd >> 8 & 0xff;
0811     devrec->rx_buf[1] = cmd & 0xff;
0812 
0813     ret = spi_async(devrec->spi, &devrec->rx_msg);
0814     if (ret) {
0815         dev_err(printdev(devrec), "failed to read rx buffer length\n");
0816         mrf24j40_handle_rx_read_buf_unlock(devrec);
0817     }
0818 }
0819 
0820 static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
0821 {
0822     /* Turn off reception of packets off the air. This prevents the
0823      * device from overwriting the buffer while we're reading it.
0824      */
0825     devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
0826     devrec->rx_trx.len = 2;
0827     devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
0828     devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */
0829 
0830     return spi_async(devrec->spi, &devrec->rx_msg);
0831 }
0832 
0833 static int
0834 mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
0835              u8 retries)
0836 {
0837     struct mrf24j40 *devrec = hw->priv;
0838     u8 val;
0839 
0840     /* min_be */
0841     val = min_be << TXMCR_MIN_BE_SHIFT;
0842     /* csma backoffs */
0843     val |= retries << TXMCR_CSMA_RETRIES_SHIFT;
0844 
0845     return regmap_update_bits(devrec->regmap_short, REG_TXMCR,
0846                   TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK,
0847                   val);
0848 }
0849 
0850 static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
0851                  const struct wpan_phy_cca *cca)
0852 {
0853     struct mrf24j40 *devrec = hw->priv;
0854     u8 val;
0855 
0856     /* mapping 802.15.4 to driver spec */
0857     switch (cca->mode) {
0858     case NL802154_CCA_ENERGY:
0859         val = 2;
0860         break;
0861     case NL802154_CCA_CARRIER:
0862         val = 1;
0863         break;
0864     case NL802154_CCA_ENERGY_CARRIER:
0865         switch (cca->opt) {
0866         case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
0867             val = 3;
0868             break;
0869         default:
0870             return -EINVAL;
0871         }
0872         break;
0873     default:
0874         return -EINVAL;
0875     }
0876 
0877     return regmap_update_bits(devrec->regmap_short, REG_BBREG2,
0878                   BBREG2_CCA_MODE_MASK,
0879                   val << BBREG2_CCA_MODE_SHIFT);
0880 }
0881 
0882 /* array for representing ed levels */
0883 static const s32 mrf24j40_ed_levels[] = {
0884     -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100,
0885     -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100,
0886     -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100,
0887     -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100,
0888     -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100,
0889     -4000, -3900, -3800, -3700, -3600, -3500
0890 };
0891 
0892 /* map ed levels to register value */
0893 static const s32 mrf24j40_ed_levels_map[][2] = {
0894     { -9000, 0 }, { -8900, 1 }, { -8800, 2 }, { -8700, 5 }, { -8600, 9 },
0895     { -8500, 13 }, { -8400, 18 }, { -8300, 23 }, { -8200, 27 },
0896     { -8100, 32 }, { -8000, 37 }, { -7900, 43 }, { -7800, 48 },
0897     { -7700, 53 }, { -7600, 58 }, { -7500, 63 }, { -7400, 68 },
0898     { -7300, 73 }, { -7200, 78 }, { -7100, 83 }, { -7000, 89 },
0899     { -6900, 95 }, { -6800, 100 }, { -6700, 107 }, { -6600, 111 },
0900     { -6500, 117 }, { -6400, 121 }, { -6300, 125 }, { -6200, 129 },
0901     { -6100, 133 }, { -6000, 138 }, { -5900, 143 }, { -5800, 148 },
0902     { -5700, 153 }, { -5600, 159 }, { -5500, 165 }, { -5400, 170 },
0903     { -5300, 176 }, { -5200, 183 }, { -5100, 188 }, { -5000, 193 },
0904     { -4900, 198 }, { -4800, 203 }, { -4700, 207 }, { -4600, 212 },
0905     { -4500, 216 }, { -4400, 221 }, { -4300, 225 }, { -4200, 228 },
0906     { -4100, 233 }, { -4000, 239 }, { -3900, 245 }, { -3800, 250 },
0907     { -3700, 253 }, { -3600, 254 }, { -3500, 255 },
0908 };
0909 
0910 static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
0911 {
0912     struct mrf24j40 *devrec = hw->priv;
0913     int i;
0914 
0915     for (i = 0; i < ARRAY_SIZE(mrf24j40_ed_levels_map); i++) {
0916         if (mrf24j40_ed_levels_map[i][0] == mbm)
0917             return regmap_write(devrec->regmap_short, REG_CCAEDTH,
0918                         mrf24j40_ed_levels_map[i][1]);
0919     }
0920 
0921     return -EINVAL;
0922 }
0923 
0924 static const s32 mrf24j40ma_powers[] = {
0925     0, -50, -120, -190, -280, -370, -490, -630, -1000, -1050, -1120, -1190,
0926     -1280, -1370, -1490, -1630, -2000, -2050, -2120, -2190, -2280, -2370,
0927     -2490, -2630, -3000, -3050, -3120, -3190, -3280, -3370, -3490, -3630,
0928 };
0929 
0930 static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm)
0931 {
0932     struct mrf24j40 *devrec = hw->priv;
0933     s32 small_scale;
0934     u8 val;
0935 
0936     if (0 >= mbm && mbm > -1000) {
0937         val = TXPWRL_0 << TXPWRL_SHIFT;
0938         small_scale = mbm;
0939     } else if (-1000 >= mbm && mbm > -2000) {
0940         val = TXPWRL_10 << TXPWRL_SHIFT;
0941         small_scale = mbm + 1000;
0942     } else if (-2000 >= mbm && mbm > -3000) {
0943         val = TXPWRL_20 << TXPWRL_SHIFT;
0944         small_scale = mbm + 2000;
0945     } else if (-3000 >= mbm && mbm > -4000) {
0946         val = TXPWRL_30 << TXPWRL_SHIFT;
0947         small_scale = mbm + 3000;
0948     } else {
0949         return -EINVAL;
0950     }
0951 
0952     switch (small_scale) {
0953     case 0:
0954         val |= (TXPWRS_0 << TXPWRS_SHIFT);
0955         break;
0956     case -50:
0957         val |= (TXPWRS_0_5 << TXPWRS_SHIFT);
0958         break;
0959     case -120:
0960         val |= (TXPWRS_1_2 << TXPWRS_SHIFT);
0961         break;
0962     case -190:
0963         val |= (TXPWRS_1_9 << TXPWRS_SHIFT);
0964         break;
0965     case -280:
0966         val |= (TXPWRS_2_8 << TXPWRS_SHIFT);
0967         break;
0968     case -370:
0969         val |= (TXPWRS_3_7 << TXPWRS_SHIFT);
0970         break;
0971     case -490:
0972         val |= (TXPWRS_4_9 << TXPWRS_SHIFT);
0973         break;
0974     case -630:
0975         val |= (TXPWRS_6_3 << TXPWRS_SHIFT);
0976         break;
0977     default:
0978         return -EINVAL;
0979     }
0980 
0981     return regmap_update_bits(devrec->regmap_long, REG_RFCON3,
0982                   TXPWRL_MASK | TXPWRS_MASK, val);
0983 }
0984 
0985 static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
0986 {
0987     struct mrf24j40 *devrec = hw->priv;
0988     int ret;
0989 
0990     if (on) {
0991         /* set PROMI, ERRPKT and NOACKRSP */
0992         ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
0993                      BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
0994                      BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP);
0995     } else {
0996         /* clear PROMI, ERRPKT and NOACKRSP */
0997         ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
0998                      BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
0999                      0);
1000     }
1001 
1002     return ret;
1003 }
1004 
1005 static const struct ieee802154_ops mrf24j40_ops = {
1006     .owner = THIS_MODULE,
1007     .xmit_async = mrf24j40_tx,
1008     .ed = mrf24j40_ed,
1009     .start = mrf24j40_start,
1010     .stop = mrf24j40_stop,
1011     .set_channel = mrf24j40_set_channel,
1012     .set_hw_addr_filt = mrf24j40_filter,
1013     .set_csma_params = mrf24j40_csma_params,
1014     .set_cca_mode = mrf24j40_set_cca_mode,
1015     .set_cca_ed_level = mrf24j40_set_cca_ed_level,
1016     .set_txpower = mrf24j40_set_txpower,
1017     .set_promiscuous_mode = mrf24j40_set_promiscuous_mode,
1018 };
1019 
1020 static void mrf24j40_intstat_complete(void *context)
1021 {
1022     struct mrf24j40 *devrec = context;
1023     u8 intstat = devrec->irq_buf[1];
1024 
1025     enable_irq(devrec->spi->irq);
1026 
1027     /* Ignore Rx security decryption */
1028     if (intstat & BIT_SECIF)
1029         regmap_write_async(devrec->regmap_short, REG_SECCON0,
1030                    BIT_SECIGNORE);
1031 
1032     /* Check for TX complete */
1033     if (intstat & BIT_TXNIF)
1034         ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
1035 
1036     /* Check for Rx */
1037     if (intstat & BIT_RXIF)
1038         mrf24j40_handle_rx(devrec);
1039 }
1040 
1041 static irqreturn_t mrf24j40_isr(int irq, void *data)
1042 {
1043     struct mrf24j40 *devrec = data;
1044     int ret;
1045 
1046     disable_irq_nosync(irq);
1047 
1048     devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT);
1049     devrec->irq_buf[1] = 0;
1050 
1051     /* Read the interrupt status */
1052     ret = spi_async(devrec->spi, &devrec->irq_msg);
1053     if (ret) {
1054         enable_irq(irq);
1055         return IRQ_NONE;
1056     }
1057 
1058     return IRQ_HANDLED;
1059 }
1060 
1061 static int mrf24j40_hw_init(struct mrf24j40 *devrec)
1062 {
1063     u32 irq_type;
1064     int ret;
1065 
1066     /* Initialize the device.
1067         From datasheet section 3.2: Initialization. */
1068     ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
1069     if (ret)
1070         goto err_ret;
1071 
1072     ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
1073     if (ret)
1074         goto err_ret;
1075 
1076     ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
1077     if (ret)
1078         goto err_ret;
1079 
1080     ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
1081     if (ret)
1082         goto err_ret;
1083 
1084     ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
1085     if (ret)
1086         goto err_ret;
1087 
1088     ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
1089     if (ret)
1090         goto err_ret;
1091 
1092     ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
1093     if (ret)
1094         goto err_ret;
1095 
1096     ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
1097     if (ret)
1098         goto err_ret;
1099 
1100     ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
1101     if (ret)
1102         goto err_ret;
1103 
1104     ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
1105     if (ret)
1106         goto err_ret;
1107 
1108     ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
1109     if (ret)
1110         goto err_ret;
1111 
1112     ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
1113     if (ret)
1114         goto err_ret;
1115 
1116     ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
1117     if (ret)
1118         goto err_ret;
1119 
1120     ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
1121     if (ret)
1122         goto err_ret;
1123 
1124     ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
1125     if (ret)
1126         goto err_ret;
1127 
1128     udelay(192);
1129 
1130     /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
1131     ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
1132     if (ret)
1133         goto err_ret;
1134 
1135     if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
1136         /* Enable external amplifier.
1137          * From MRF24J40MC datasheet section 1.3: Operation.
1138          */
1139         regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
1140                    0x07);
1141 
1142         /* Set GPIO3 as output. */
1143         regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
1144                    0x08);
1145 
1146         /* Set GPIO3 HIGH to enable U5 voltage regulator */
1147         regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
1148 
1149         /* Reduce TX pwr to meet FCC requirements.
1150          * From MRF24J40MC datasheet section 3.1.1
1151          */
1152         regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
1153     }
1154 
1155     irq_type = irq_get_trigger_type(devrec->spi->irq);
1156     if (irq_type == IRQ_TYPE_EDGE_RISING ||
1157         irq_type == IRQ_TYPE_EDGE_FALLING)
1158         dev_warn(&devrec->spi->dev,
1159              "Using edge triggered irq's are not recommended, because it can cause races and result in a non-functional driver!\n");
1160     switch (irq_type) {
1161     case IRQ_TYPE_EDGE_RISING:
1162     case IRQ_TYPE_LEVEL_HIGH:
1163         /* set interrupt polarity to rising */
1164         ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0,
1165                      BIT_INTEDGE, BIT_INTEDGE);
1166         if (ret)
1167             goto err_ret;
1168         break;
1169     default:
1170         /* default is falling edge */
1171         break;
1172     }
1173 
1174     return 0;
1175 
1176 err_ret:
1177     return ret;
1178 }
1179 
1180 static void
1181 mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
1182 {
1183     spi_message_init(&devrec->tx_msg);
1184     devrec->tx_msg.context = devrec;
1185     devrec->tx_msg.complete = write_tx_buf_complete;
1186     devrec->tx_hdr_trx.len = 2;
1187     devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;
1188     spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);
1189     devrec->tx_len_trx.len = 2;
1190     devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;
1191     spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);
1192     spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);
1193 
1194     spi_message_init(&devrec->tx_post_msg);
1195     devrec->tx_post_msg.context = devrec;
1196     devrec->tx_post_trx.len = 2;
1197     devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;
1198     spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
1199 }
1200 
1201 static void
1202 mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
1203 {
1204     spi_message_init(&devrec->rx_msg);
1205     devrec->rx_msg.context = devrec;
1206     devrec->rx_trx.len = 2;
1207     devrec->rx_trx.tx_buf = devrec->rx_buf;
1208     devrec->rx_trx.rx_buf = devrec->rx_buf;
1209     spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);
1210 
1211     spi_message_init(&devrec->rx_buf_msg);
1212     devrec->rx_buf_msg.context = devrec;
1213     devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;
1214     devrec->rx_addr_trx.len = 2;
1215     devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;
1216     spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);
1217     devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;
1218     spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);
1219     devrec->rx_lqi_trx.len = 2;
1220     devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;
1221     spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);
1222 }
1223 
1224 static void
1225 mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)
1226 {
1227     spi_message_init(&devrec->irq_msg);
1228     devrec->irq_msg.context = devrec;
1229     devrec->irq_msg.complete = mrf24j40_intstat_complete;
1230     devrec->irq_trx.len = 2;
1231     devrec->irq_trx.tx_buf = devrec->irq_buf;
1232     devrec->irq_trx.rx_buf = devrec->irq_buf;
1233     spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg);
1234 }
1235 
1236 static void  mrf24j40_phy_setup(struct mrf24j40 *devrec)
1237 {
1238     ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
1239     devrec->hw->phy->current_channel = 11;
1240 
1241     /* mrf24j40 supports max_minbe 0 - 3 */
1242     devrec->hw->phy->supported.max_minbe = 3;
1243     /* datasheet doesn't say anything about max_be, but we have min_be
1244      * So we assume the max_be default.
1245      */
1246     devrec->hw->phy->supported.min_maxbe = 5;
1247     devrec->hw->phy->supported.max_maxbe = 5;
1248 
1249     devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER;
1250     devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
1251                            BIT(NL802154_CCA_CARRIER) |
1252                            BIT(NL802154_CCA_ENERGY_CARRIER);
1253     devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND);
1254 
1255     devrec->hw->phy->cca_ed_level = -6900;
1256     devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels;
1257     devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels);
1258 
1259     switch (spi_get_device_id(devrec->spi)->driver_data) {
1260     case MRF24J40:
1261     case MRF24J40MA:
1262         devrec->hw->phy->supported.tx_powers = mrf24j40ma_powers;
1263         devrec->hw->phy->supported.tx_powers_size = ARRAY_SIZE(mrf24j40ma_powers);
1264         devrec->hw->phy->flags |= WPAN_PHY_FLAG_TXPOWER;
1265         break;
1266     default:
1267         break;
1268     }
1269 }
1270 
1271 static int mrf24j40_probe(struct spi_device *spi)
1272 {
1273     int ret = -ENOMEM, irq_type;
1274     struct ieee802154_hw *hw;
1275     struct mrf24j40 *devrec;
1276 
1277     dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
1278 
1279     /* Register with the 802154 subsystem */
1280 
1281     hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);
1282     if (!hw)
1283         goto err_ret;
1284 
1285     devrec = hw->priv;
1286     devrec->spi = spi;
1287     spi_set_drvdata(spi, devrec);
1288     devrec->hw = hw;
1289     devrec->hw->parent = &spi->dev;
1290     devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
1291     devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT |
1292                 IEEE802154_HW_CSMA_PARAMS |
1293                 IEEE802154_HW_PROMISCUOUS;
1294 
1295     devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE |
1296                  WPAN_PHY_FLAG_CCA_ED_LEVEL;
1297 
1298     mrf24j40_setup_tx_spi_messages(devrec);
1299     mrf24j40_setup_rx_spi_messages(devrec);
1300     mrf24j40_setup_irq_spi_messages(devrec);
1301 
1302     devrec->regmap_short = devm_regmap_init_spi(spi,
1303                             &mrf24j40_short_regmap);
1304     if (IS_ERR(devrec->regmap_short)) {
1305         ret = PTR_ERR(devrec->regmap_short);
1306         dev_err(&spi->dev, "Failed to allocate short register map: %d\n",
1307             ret);
1308         goto err_register_device;
1309     }
1310 
1311     devrec->regmap_long = devm_regmap_init(&spi->dev,
1312                            &mrf24j40_long_regmap_bus,
1313                            spi, &mrf24j40_long_regmap);
1314     if (IS_ERR(devrec->regmap_long)) {
1315         ret = PTR_ERR(devrec->regmap_long);
1316         dev_err(&spi->dev, "Failed to allocate long register map: %d\n",
1317             ret);
1318         goto err_register_device;
1319     }
1320 
1321     if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) {
1322         dev_warn(&spi->dev, "spi clock above possible maximum: %d",
1323              MAX_SPI_SPEED_HZ);
1324         ret = -EINVAL;
1325         goto err_register_device;
1326     }
1327 
1328     ret = mrf24j40_hw_init(devrec);
1329     if (ret)
1330         goto err_register_device;
1331 
1332     mrf24j40_phy_setup(devrec);
1333 
1334     /* request IRQF_TRIGGER_LOW as fallback default */
1335     irq_type = irq_get_trigger_type(spi->irq);
1336     if (!irq_type)
1337         irq_type = IRQF_TRIGGER_LOW;
1338 
1339     ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr,
1340                    irq_type, dev_name(&spi->dev), devrec);
1341     if (ret) {
1342         dev_err(printdev(devrec), "Unable to get IRQ");
1343         goto err_register_device;
1344     }
1345 
1346     dev_dbg(printdev(devrec), "registered mrf24j40\n");
1347     ret = ieee802154_register_hw(devrec->hw);
1348     if (ret)
1349         goto err_register_device;
1350 
1351     return 0;
1352 
1353 err_register_device:
1354     ieee802154_free_hw(devrec->hw);
1355 err_ret:
1356     return ret;
1357 }
1358 
1359 static void mrf24j40_remove(struct spi_device *spi)
1360 {
1361     struct mrf24j40 *devrec = spi_get_drvdata(spi);
1362 
1363     dev_dbg(printdev(devrec), "remove\n");
1364 
1365     ieee802154_unregister_hw(devrec->hw);
1366     ieee802154_free_hw(devrec->hw);
1367     /* TODO: Will ieee802154_free_device() wait until ->xmit() is
1368      * complete? */
1369 }
1370 
1371 static const struct of_device_id mrf24j40_of_match[] = {
1372     { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 },
1373     { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA },
1374     { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC },
1375     { },
1376 };
1377 MODULE_DEVICE_TABLE(of, mrf24j40_of_match);
1378 
1379 static const struct spi_device_id mrf24j40_ids[] = {
1380     { "mrf24j40", MRF24J40 },
1381     { "mrf24j40ma", MRF24J40MA },
1382     { "mrf24j40mc", MRF24J40MC },
1383     { },
1384 };
1385 MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
1386 
1387 static struct spi_driver mrf24j40_driver = {
1388     .driver = {
1389         .of_match_table = mrf24j40_of_match,
1390         .name = "mrf24j40",
1391     },
1392     .id_table = mrf24j40_ids,
1393     .probe = mrf24j40_probe,
1394     .remove = mrf24j40_remove,
1395 };
1396 
1397 module_spi_driver(mrf24j40_driver);
1398 
1399 MODULE_LICENSE("GPL");
1400 MODULE_AUTHOR("Alan Ott");
1401 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!