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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
0004  *
0005  * Copyright (C) 2018 Xue Liu <liuxuenetmail@gmail.com>
0006  */
0007 #include <linux/kernel.h>
0008 #include <linux/module.h>
0009 #include <linux/gpio/consumer.h>
0010 #include <linux/spi/spi.h>
0011 #include <linux/workqueue.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/irq.h>
0014 #include <linux/skbuff.h>
0015 #include <linux/of_gpio.h>
0016 #include <linux/regmap.h>
0017 #include <linux/ieee802154.h>
0018 #include <linux/debugfs.h>
0019 
0020 #include <net/mac802154.h>
0021 #include <net/cfg802154.h>
0022 
0023 #include <linux/device.h>
0024 
0025 #include "mcr20a.h"
0026 
0027 #define SPI_COMMAND_BUFFER      3
0028 
0029 #define REGISTER_READ           BIT(7)
0030 #define REGISTER_WRITE          (0 << 7)
0031 #define REGISTER_ACCESS         (0 << 6)
0032 #define PACKET_BUFF_BURST_ACCESS    BIT(6)
0033 #define PACKET_BUFF_BYTE_ACCESS     BIT(5)
0034 
0035 #define MCR20A_WRITE_REG(x)     (x)
0036 #define MCR20A_READ_REG(x)      (REGISTER_READ | (x))
0037 #define MCR20A_BURST_READ_PACKET_BUF    (0xC0)
0038 #define MCR20A_BURST_WRITE_PACKET_BUF   (0x40)
0039 
0040 #define MCR20A_CMD_REG      0x80
0041 #define MCR20A_CMD_REG_MASK 0x3f
0042 #define MCR20A_CMD_WRITE    0x40
0043 #define MCR20A_CMD_FB       0x20
0044 
0045 /* Number of Interrupt Request Status Register */
0046 #define MCR20A_IRQSTS_NUM 2 /* only IRQ_STS1 and IRQ_STS2 */
0047 
0048 /* MCR20A CCA Type */
0049 enum {
0050     MCR20A_CCA_ED,    // energy detect - CCA bit not active,
0051               // not to be used for T and CCCA sequences
0052     MCR20A_CCA_MODE1, // energy detect - CCA bit ACTIVE
0053     MCR20A_CCA_MODE2, // 802.15.4 compliant signal detect - CCA bit ACTIVE
0054     MCR20A_CCA_MODE3
0055 };
0056 
0057 enum {
0058     MCR20A_XCVSEQ_IDLE  = 0x00,
0059     MCR20A_XCVSEQ_RX    = 0x01,
0060     MCR20A_XCVSEQ_TX    = 0x02,
0061     MCR20A_XCVSEQ_CCA   = 0x03,
0062     MCR20A_XCVSEQ_TR    = 0x04,
0063     MCR20A_XCVSEQ_CCCA  = 0x05,
0064 };
0065 
0066 /* IEEE-802.15.4 defined constants (2.4 GHz logical channels) */
0067 #define MCR20A_MIN_CHANNEL  (11)
0068 #define MCR20A_MAX_CHANNEL  (26)
0069 #define MCR20A_CHANNEL_SPACING  (5)
0070 
0071 /* MCR20A CCA Threshold constans */
0072 #define MCR20A_MIN_CCA_THRESHOLD (0x6EU)
0073 #define MCR20A_MAX_CCA_THRESHOLD (0x00U)
0074 
0075 /* version 0C */
0076 #define MCR20A_OVERWRITE_VERSION (0x0C)
0077 
0078 /* MCR20A PLL configurations */
0079 static const u8  PLL_INT[16] = {
0080     /* 2405 */ 0x0B,    /* 2410 */ 0x0B,    /* 2415 */ 0x0B,
0081     /* 2420 */ 0x0B,    /* 2425 */ 0x0B,    /* 2430 */ 0x0B,
0082     /* 2435 */ 0x0C,    /* 2440 */ 0x0C,    /* 2445 */ 0x0C,
0083     /* 2450 */ 0x0C,    /* 2455 */ 0x0C,    /* 2460 */ 0x0C,
0084     /* 2465 */ 0x0D,    /* 2470 */ 0x0D,    /* 2475 */ 0x0D,
0085     /* 2480 */ 0x0D
0086 };
0087 
0088 static const u8 PLL_FRAC[16] = {
0089     /* 2405 */ 0x28,    /* 2410 */ 0x50,    /* 2415 */ 0x78,
0090     /* 2420 */ 0xA0,    /* 2425 */ 0xC8,    /* 2430 */ 0xF0,
0091     /* 2435 */ 0x18,    /* 2440 */ 0x40,    /* 2445 */ 0x68,
0092     /* 2450 */ 0x90,    /* 2455 */ 0xB8,    /* 2460 */ 0xE0,
0093     /* 2465 */ 0x08,    /* 2470 */ 0x30,    /* 2475 */ 0x58,
0094     /* 2480 */ 0x80
0095 };
0096 
0097 static const struct reg_sequence mar20a_iar_overwrites[] = {
0098     { IAR_MISC_PAD_CTRL,    0x02 },
0099     { IAR_VCO_CTRL1,    0xB3 },
0100     { IAR_VCO_CTRL2,    0x07 },
0101     { IAR_PA_TUNING,    0x71 },
0102     { IAR_CHF_IBUF,     0x2F },
0103     { IAR_CHF_QBUF,     0x2F },
0104     { IAR_CHF_IRIN,     0x24 },
0105     { IAR_CHF_QRIN,     0x24 },
0106     { IAR_CHF_IL,       0x24 },
0107     { IAR_CHF_QL,       0x24 },
0108     { IAR_CHF_CC1,      0x32 },
0109     { IAR_CHF_CCL,      0x1D },
0110     { IAR_CHF_CC2,      0x2D },
0111     { IAR_CHF_IROUT,    0x24 },
0112     { IAR_CHF_QROUT,    0x24 },
0113     { IAR_PA_CAL,       0x28 },
0114     { IAR_AGC_THR1,     0x55 },
0115     { IAR_AGC_THR2,     0x2D },
0116     { IAR_ATT_RSSI1,    0x5F },
0117     { IAR_ATT_RSSI2,    0x8F },
0118     { IAR_RSSI_OFFSET,  0x61 },
0119     { IAR_CHF_PMA_GAIN, 0x03 },
0120     { IAR_CCA1_THRESH,  0x50 },
0121     { IAR_CORR_NVAL,    0x13 },
0122     { IAR_ACKDELAY,     0x3D },
0123 };
0124 
0125 #define MCR20A_VALID_CHANNELS (0x07FFF800)
0126 #define MCR20A_MAX_BUF      (127)
0127 
0128 #define printdev(X) (&X->spi->dev)
0129 
0130 /* regmap information for Direct Access Register (DAR) access */
0131 #define MCR20A_DAR_WRITE    0x01
0132 #define MCR20A_DAR_READ     0x00
0133 #define MCR20A_DAR_NUMREGS  0x3F
0134 
0135 /* regmap information for Indirect Access Register (IAR) access */
0136 #define MCR20A_IAR_ACCESS   0x80
0137 #define MCR20A_IAR_NUMREGS  0xBEFF
0138 
0139 /* Read/Write SPI Commands for DAR and IAR registers. */
0140 #define MCR20A_READSHORT(reg)   ((reg) << 1)
0141 #define MCR20A_WRITESHORT(reg)  ((reg) << 1 | 1)
0142 #define MCR20A_READLONG(reg)    (1 << 15 | (reg) << 5)
0143 #define MCR20A_WRITELONG(reg)   (1 << 15 | (reg) << 5 | 1 << 4)
0144 
0145 /* Type definitions for link configuration of instantiable layers  */
0146 #define MCR20A_PHY_INDIRECT_QUEUE_SIZE (12)
0147 
0148 static bool
0149 mcr20a_dar_writeable(struct device *dev, unsigned int reg)
0150 {
0151     switch (reg) {
0152     case DAR_IRQ_STS1:
0153     case DAR_IRQ_STS2:
0154     case DAR_IRQ_STS3:
0155     case DAR_PHY_CTRL1:
0156     case DAR_PHY_CTRL2:
0157     case DAR_PHY_CTRL3:
0158     case DAR_PHY_CTRL4:
0159     case DAR_SRC_CTRL:
0160     case DAR_SRC_ADDRS_SUM_LSB:
0161     case DAR_SRC_ADDRS_SUM_MSB:
0162     case DAR_T3CMP_LSB:
0163     case DAR_T3CMP_MSB:
0164     case DAR_T3CMP_USB:
0165     case DAR_T2PRIMECMP_LSB:
0166     case DAR_T2PRIMECMP_MSB:
0167     case DAR_T1CMP_LSB:
0168     case DAR_T1CMP_MSB:
0169     case DAR_T1CMP_USB:
0170     case DAR_T2CMP_LSB:
0171     case DAR_T2CMP_MSB:
0172     case DAR_T2CMP_USB:
0173     case DAR_T4CMP_LSB:
0174     case DAR_T4CMP_MSB:
0175     case DAR_T4CMP_USB:
0176     case DAR_PLL_INT0:
0177     case DAR_PLL_FRAC0_LSB:
0178     case DAR_PLL_FRAC0_MSB:
0179     case DAR_PA_PWR:
0180     /* no DAR_ACM */
0181     case DAR_OVERWRITE_VER:
0182     case DAR_CLK_OUT_CTRL:
0183     case DAR_PWR_MODES:
0184         return true;
0185     default:
0186         return false;
0187     }
0188 }
0189 
0190 static bool
0191 mcr20a_dar_readable(struct device *dev, unsigned int reg)
0192 {
0193     bool rc;
0194 
0195     /* all writeable are also readable */
0196     rc = mcr20a_dar_writeable(dev, reg);
0197     if (rc)
0198         return rc;
0199 
0200     /* readonly regs */
0201     switch (reg) {
0202     case DAR_RX_FRM_LEN:
0203     case DAR_CCA1_ED_FNL:
0204     case DAR_EVENT_TMR_LSB:
0205     case DAR_EVENT_TMR_MSB:
0206     case DAR_EVENT_TMR_USB:
0207     case DAR_TIMESTAMP_LSB:
0208     case DAR_TIMESTAMP_MSB:
0209     case DAR_TIMESTAMP_USB:
0210     case DAR_SEQ_STATE:
0211     case DAR_LQI_VALUE:
0212     case DAR_RSSI_CCA_CONT:
0213         return true;
0214     default:
0215         return false;
0216     }
0217 }
0218 
0219 static bool
0220 mcr20a_dar_volatile(struct device *dev, unsigned int reg)
0221 {
0222     /* can be changed during runtime */
0223     switch (reg) {
0224     case DAR_IRQ_STS1:
0225     case DAR_IRQ_STS2:
0226     case DAR_IRQ_STS3:
0227     /* use them in spi_async and regmap so it's volatile */
0228         return true;
0229     default:
0230         return false;
0231     }
0232 }
0233 
0234 static bool
0235 mcr20a_dar_precious(struct device *dev, unsigned int reg)
0236 {
0237     /* don't clear irq line on read */
0238     switch (reg) {
0239     case DAR_IRQ_STS1:
0240     case DAR_IRQ_STS2:
0241     case DAR_IRQ_STS3:
0242         return true;
0243     default:
0244         return false;
0245     }
0246 }
0247 
0248 static const struct regmap_config mcr20a_dar_regmap = {
0249     .name           = "mcr20a_dar",
0250     .reg_bits       = 8,
0251     .val_bits       = 8,
0252     .write_flag_mask    = REGISTER_ACCESS | REGISTER_WRITE,
0253     .read_flag_mask     = REGISTER_ACCESS | REGISTER_READ,
0254     .cache_type     = REGCACHE_RBTREE,
0255     .writeable_reg      = mcr20a_dar_writeable,
0256     .readable_reg       = mcr20a_dar_readable,
0257     .volatile_reg       = mcr20a_dar_volatile,
0258     .precious_reg       = mcr20a_dar_precious,
0259     .fast_io        = true,
0260     .can_multi_write    = true,
0261 };
0262 
0263 static bool
0264 mcr20a_iar_writeable(struct device *dev, unsigned int reg)
0265 {
0266     switch (reg) {
0267     case IAR_XTAL_TRIM:
0268     case IAR_PMC_LP_TRIM:
0269     case IAR_MACPANID0_LSB:
0270     case IAR_MACPANID0_MSB:
0271     case IAR_MACSHORTADDRS0_LSB:
0272     case IAR_MACSHORTADDRS0_MSB:
0273     case IAR_MACLONGADDRS0_0:
0274     case IAR_MACLONGADDRS0_8:
0275     case IAR_MACLONGADDRS0_16:
0276     case IAR_MACLONGADDRS0_24:
0277     case IAR_MACLONGADDRS0_32:
0278     case IAR_MACLONGADDRS0_40:
0279     case IAR_MACLONGADDRS0_48:
0280     case IAR_MACLONGADDRS0_56:
0281     case IAR_RX_FRAME_FILTER:
0282     case IAR_PLL_INT1:
0283     case IAR_PLL_FRAC1_LSB:
0284     case IAR_PLL_FRAC1_MSB:
0285     case IAR_MACPANID1_LSB:
0286     case IAR_MACPANID1_MSB:
0287     case IAR_MACSHORTADDRS1_LSB:
0288     case IAR_MACSHORTADDRS1_MSB:
0289     case IAR_MACLONGADDRS1_0:
0290     case IAR_MACLONGADDRS1_8:
0291     case IAR_MACLONGADDRS1_16:
0292     case IAR_MACLONGADDRS1_24:
0293     case IAR_MACLONGADDRS1_32:
0294     case IAR_MACLONGADDRS1_40:
0295     case IAR_MACLONGADDRS1_48:
0296     case IAR_MACLONGADDRS1_56:
0297     case IAR_DUAL_PAN_CTRL:
0298     case IAR_DUAL_PAN_DWELL:
0299     case IAR_CCA1_THRESH:
0300     case IAR_CCA1_ED_OFFSET_COMP:
0301     case IAR_LQI_OFFSET_COMP:
0302     case IAR_CCA_CTRL:
0303     case IAR_CCA2_CORR_PEAKS:
0304     case IAR_CCA2_CORR_THRESH:
0305     case IAR_TMR_PRESCALE:
0306     case IAR_ANT_PAD_CTRL:
0307     case IAR_MISC_PAD_CTRL:
0308     case IAR_BSM_CTRL:
0309     case IAR_RNG:
0310     case IAR_RX_WTR_MARK:
0311     case IAR_SOFT_RESET:
0312     case IAR_TXDELAY:
0313     case IAR_ACKDELAY:
0314     case IAR_CORR_NVAL:
0315     case IAR_ANT_AGC_CTRL:
0316     case IAR_AGC_THR1:
0317     case IAR_AGC_THR2:
0318     case IAR_PA_CAL:
0319     case IAR_ATT_RSSI1:
0320     case IAR_ATT_RSSI2:
0321     case IAR_RSSI_OFFSET:
0322     case IAR_XTAL_CTRL:
0323     case IAR_CHF_PMA_GAIN:
0324     case IAR_CHF_IBUF:
0325     case IAR_CHF_QBUF:
0326     case IAR_CHF_IRIN:
0327     case IAR_CHF_QRIN:
0328     case IAR_CHF_IL:
0329     case IAR_CHF_QL:
0330     case IAR_CHF_CC1:
0331     case IAR_CHF_CCL:
0332     case IAR_CHF_CC2:
0333     case IAR_CHF_IROUT:
0334     case IAR_CHF_QROUT:
0335     case IAR_PA_TUNING:
0336     case IAR_VCO_CTRL1:
0337     case IAR_VCO_CTRL2:
0338         return true;
0339     default:
0340         return false;
0341     }
0342 }
0343 
0344 static bool
0345 mcr20a_iar_readable(struct device *dev, unsigned int reg)
0346 {
0347     bool rc;
0348 
0349     /* all writeable are also readable */
0350     rc = mcr20a_iar_writeable(dev, reg);
0351     if (rc)
0352         return rc;
0353 
0354     /* readonly regs */
0355     switch (reg) {
0356     case IAR_PART_ID:
0357     case IAR_DUAL_PAN_STS:
0358     case IAR_RX_BYTE_COUNT:
0359     case IAR_FILTERFAIL_CODE1:
0360     case IAR_FILTERFAIL_CODE2:
0361     case IAR_RSSI:
0362         return true;
0363     default:
0364         return false;
0365     }
0366 }
0367 
0368 static bool
0369 mcr20a_iar_volatile(struct device *dev, unsigned int reg)
0370 {
0371 /* can be changed during runtime */
0372     switch (reg) {
0373     case IAR_DUAL_PAN_STS:
0374     case IAR_RX_BYTE_COUNT:
0375     case IAR_FILTERFAIL_CODE1:
0376     case IAR_FILTERFAIL_CODE2:
0377     case IAR_RSSI:
0378         return true;
0379     default:
0380         return false;
0381     }
0382 }
0383 
0384 static const struct regmap_config mcr20a_iar_regmap = {
0385     .name           = "mcr20a_iar",
0386     .reg_bits       = 16,
0387     .val_bits       = 8,
0388     .write_flag_mask    = REGISTER_ACCESS | REGISTER_WRITE | IAR_INDEX,
0389     .read_flag_mask     = REGISTER_ACCESS | REGISTER_READ  | IAR_INDEX,
0390     .cache_type     = REGCACHE_RBTREE,
0391     .writeable_reg      = mcr20a_iar_writeable,
0392     .readable_reg       = mcr20a_iar_readable,
0393     .volatile_reg       = mcr20a_iar_volatile,
0394     .fast_io        = true,
0395 };
0396 
0397 struct mcr20a_local {
0398     struct spi_device *spi;
0399 
0400     struct ieee802154_hw *hw;
0401     struct regmap *regmap_dar;
0402     struct regmap *regmap_iar;
0403 
0404     u8 *buf;
0405 
0406     bool is_tx;
0407 
0408     /* for writing tx buffer */
0409     struct spi_message tx_buf_msg;
0410     u8 tx_header[1];
0411     /* burst buffer write command */
0412     struct spi_transfer tx_xfer_header;
0413     u8 tx_len[1];
0414     /* len of tx packet */
0415     struct spi_transfer tx_xfer_len;
0416     /* data of tx packet */
0417     struct spi_transfer tx_xfer_buf;
0418     struct sk_buff *tx_skb;
0419 
0420     /* for read length rxfifo */
0421     struct spi_message reg_msg;
0422     u8 reg_cmd[1];
0423     u8 reg_data[MCR20A_IRQSTS_NUM];
0424     struct spi_transfer reg_xfer_cmd;
0425     struct spi_transfer reg_xfer_data;
0426 
0427     /* receive handling */
0428     struct spi_message rx_buf_msg;
0429     u8 rx_header[1];
0430     struct spi_transfer rx_xfer_header;
0431     u8 rx_lqi[1];
0432     struct spi_transfer rx_xfer_lqi;
0433     u8 rx_buf[MCR20A_MAX_BUF];
0434     struct spi_transfer rx_xfer_buf;
0435 
0436     /* isr handling for reading intstat */
0437     struct spi_message irq_msg;
0438     u8 irq_header[1];
0439     u8 irq_data[MCR20A_IRQSTS_NUM];
0440     struct spi_transfer irq_xfer_data;
0441     struct spi_transfer irq_xfer_header;
0442 };
0443 
0444 static void
0445 mcr20a_write_tx_buf_complete(void *context)
0446 {
0447     struct mcr20a_local *lp = context;
0448     int ret;
0449 
0450     dev_dbg(printdev(lp), "%s\n", __func__);
0451 
0452     lp->reg_msg.complete = NULL;
0453     lp->reg_cmd[0]  = MCR20A_WRITE_REG(DAR_PHY_CTRL1);
0454     lp->reg_data[0] = MCR20A_XCVSEQ_TX;
0455     lp->reg_xfer_data.len = 1;
0456 
0457     ret = spi_async(lp->spi, &lp->reg_msg);
0458     if (ret)
0459         dev_err(printdev(lp), "failed to set SEQ TX\n");
0460 }
0461 
0462 static int
0463 mcr20a_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
0464 {
0465     struct mcr20a_local *lp = hw->priv;
0466 
0467     dev_dbg(printdev(lp), "%s\n", __func__);
0468 
0469     lp->tx_skb = skb;
0470 
0471     print_hex_dump_debug("mcr20a tx: ", DUMP_PREFIX_OFFSET, 16, 1,
0472                  skb->data, skb->len, 0);
0473 
0474     lp->is_tx = 1;
0475 
0476     lp->reg_msg.complete    = NULL;
0477     lp->reg_cmd[0]      = MCR20A_WRITE_REG(DAR_PHY_CTRL1);
0478     lp->reg_data[0]     = MCR20A_XCVSEQ_IDLE;
0479     lp->reg_xfer_data.len   = 1;
0480 
0481     return spi_async(lp->spi, &lp->reg_msg);
0482 }
0483 
0484 static int
0485 mcr20a_ed(struct ieee802154_hw *hw, u8 *level)
0486 {
0487     WARN_ON(!level);
0488     *level = 0xbe;
0489     return 0;
0490 }
0491 
0492 static int
0493 mcr20a_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
0494 {
0495     struct mcr20a_local *lp = hw->priv;
0496     int ret;
0497 
0498     dev_dbg(printdev(lp), "%s\n", __func__);
0499 
0500     /* freqency = ((PLL_INT+64) + (PLL_FRAC/65536)) * 32 MHz */
0501     ret = regmap_write(lp->regmap_dar, DAR_PLL_INT0, PLL_INT[channel - 11]);
0502     if (ret)
0503         return ret;
0504     ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_LSB, 0x00);
0505     if (ret)
0506         return ret;
0507     ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_MSB,
0508                PLL_FRAC[channel - 11]);
0509     if (ret)
0510         return ret;
0511 
0512     return 0;
0513 }
0514 
0515 static int
0516 mcr20a_start(struct ieee802154_hw *hw)
0517 {
0518     struct mcr20a_local *lp = hw->priv;
0519     int ret;
0520 
0521     dev_dbg(printdev(lp), "%s\n", __func__);
0522 
0523     /* No slotted operation */
0524     dev_dbg(printdev(lp), "no slotted operation\n");
0525     ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
0526                  DAR_PHY_CTRL1_SLOTTED, 0x0);
0527     if (ret < 0)
0528         return ret;
0529 
0530     /* enable irq */
0531     enable_irq(lp->spi->irq);
0532 
0533     /* Unmask SEQ interrupt */
0534     ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL2,
0535                  DAR_PHY_CTRL2_SEQMSK, 0x0);
0536     if (ret < 0)
0537         return ret;
0538 
0539     /* Start the RX sequence */
0540     dev_dbg(printdev(lp), "start the RX sequence\n");
0541     ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
0542                  DAR_PHY_CTRL1_XCVSEQ_MASK, MCR20A_XCVSEQ_RX);
0543     if (ret < 0)
0544         return ret;
0545 
0546     return 0;
0547 }
0548 
0549 static void
0550 mcr20a_stop(struct ieee802154_hw *hw)
0551 {
0552     struct mcr20a_local *lp = hw->priv;
0553 
0554     dev_dbg(printdev(lp), "%s\n", __func__);
0555 
0556     /* stop all running sequence */
0557     regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
0558                DAR_PHY_CTRL1_XCVSEQ_MASK, MCR20A_XCVSEQ_IDLE);
0559 
0560     /* disable irq */
0561     disable_irq(lp->spi->irq);
0562 }
0563 
0564 static int
0565 mcr20a_set_hw_addr_filt(struct ieee802154_hw *hw,
0566             struct ieee802154_hw_addr_filt *filt,
0567             unsigned long changed)
0568 {
0569     struct mcr20a_local *lp = hw->priv;
0570 
0571     dev_dbg(printdev(lp), "%s\n", __func__);
0572 
0573     if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
0574         u16 addr = le16_to_cpu(filt->short_addr);
0575 
0576         regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_LSB, addr);
0577         regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_MSB, addr >> 8);
0578     }
0579 
0580     if (changed & IEEE802154_AFILT_PANID_CHANGED) {
0581         u16 pan = le16_to_cpu(filt->pan_id);
0582 
0583         regmap_write(lp->regmap_iar, IAR_MACPANID0_LSB, pan);
0584         regmap_write(lp->regmap_iar, IAR_MACPANID0_MSB, pan >> 8);
0585     }
0586 
0587     if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
0588         u8 addr[8], i;
0589 
0590         memcpy(addr, &filt->ieee_addr, 8);
0591         for (i = 0; i < 8; i++)
0592             regmap_write(lp->regmap_iar,
0593                      IAR_MACLONGADDRS0_0 + i, addr[i]);
0594     }
0595 
0596     if (changed & IEEE802154_AFILT_PANC_CHANGED) {
0597         if (filt->pan_coord) {
0598             regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
0599                        DAR_PHY_CTRL4_PANCORDNTR0, 0x10);
0600         } else {
0601             regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
0602                        DAR_PHY_CTRL4_PANCORDNTR0, 0x00);
0603         }
0604     }
0605 
0606     return 0;
0607 }
0608 
0609 /* -30 dBm to 10 dBm */
0610 #define MCR20A_MAX_TX_POWERS 0x14
0611 static const s32 mcr20a_powers[MCR20A_MAX_TX_POWERS + 1] = {
0612     -3000, -2800, -2600, -2400, -2200, -2000, -1800, -1600, -1400,
0613     -1200, -1000, -800, -600, -400, -200, 0, 200, 400, 600, 800, 1000
0614 };
0615 
0616 static int
0617 mcr20a_set_txpower(struct ieee802154_hw *hw, s32 mbm)
0618 {
0619     struct mcr20a_local *lp = hw->priv;
0620     u32 i;
0621 
0622     dev_dbg(printdev(lp), "%s(%d)\n", __func__, mbm);
0623 
0624     for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
0625         if (lp->hw->phy->supported.tx_powers[i] == mbm)
0626             return regmap_write(lp->regmap_dar, DAR_PA_PWR,
0627                         ((i + 8) & 0x1F));
0628     }
0629 
0630     return -EINVAL;
0631 }
0632 
0633 #define MCR20A_MAX_ED_LEVELS MCR20A_MIN_CCA_THRESHOLD
0634 static s32 mcr20a_ed_levels[MCR20A_MAX_ED_LEVELS + 1];
0635 
0636 static int
0637 mcr20a_set_cca_mode(struct ieee802154_hw *hw,
0638             const struct wpan_phy_cca *cca)
0639 {
0640     struct mcr20a_local *lp = hw->priv;
0641     unsigned int cca_mode = 0xff;
0642     bool cca_mode_and = false;
0643     int ret;
0644 
0645     dev_dbg(printdev(lp), "%s\n", __func__);
0646 
0647     /* mapping 802.15.4 to driver spec */
0648     switch (cca->mode) {
0649     case NL802154_CCA_ENERGY:
0650         cca_mode = MCR20A_CCA_MODE1;
0651         break;
0652     case NL802154_CCA_CARRIER:
0653         cca_mode = MCR20A_CCA_MODE2;
0654         break;
0655     case NL802154_CCA_ENERGY_CARRIER:
0656         switch (cca->opt) {
0657         case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
0658             cca_mode = MCR20A_CCA_MODE3;
0659             cca_mode_and = true;
0660             break;
0661         case NL802154_CCA_OPT_ENERGY_CARRIER_OR:
0662             cca_mode = MCR20A_CCA_MODE3;
0663             cca_mode_and = false;
0664             break;
0665         default:
0666             return -EINVAL;
0667         }
0668         break;
0669     default:
0670         return -EINVAL;
0671     }
0672     ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
0673                  DAR_PHY_CTRL4_CCATYPE_MASK,
0674                  cca_mode << DAR_PHY_CTRL4_CCATYPE_SHIFT);
0675     if (ret < 0)
0676         return ret;
0677 
0678     if (cca_mode == MCR20A_CCA_MODE3) {
0679         if (cca_mode_and) {
0680             ret = regmap_update_bits(lp->regmap_iar, IAR_CCA_CTRL,
0681                          IAR_CCA_CTRL_CCA3_AND_NOT_OR,
0682                          0x08);
0683         } else {
0684             ret = regmap_update_bits(lp->regmap_iar,
0685                          IAR_CCA_CTRL,
0686                          IAR_CCA_CTRL_CCA3_AND_NOT_OR,
0687                          0x00);
0688         }
0689         if (ret < 0)
0690             return ret;
0691     }
0692 
0693     return ret;
0694 }
0695 
0696 static int
0697 mcr20a_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
0698 {
0699     struct mcr20a_local *lp = hw->priv;
0700     u32 i;
0701 
0702     dev_dbg(printdev(lp), "%s\n", __func__);
0703 
0704     for (i = 0; i < hw->phy->supported.cca_ed_levels_size; i++) {
0705         if (hw->phy->supported.cca_ed_levels[i] == mbm)
0706             return regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, i);
0707     }
0708 
0709     return 0;
0710 }
0711 
0712 static int
0713 mcr20a_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
0714 {
0715     struct mcr20a_local *lp = hw->priv;
0716     int ret;
0717     u8 rx_frame_filter_reg = 0x0;
0718 
0719     dev_dbg(printdev(lp), "%s(%d)\n", __func__, on);
0720 
0721     if (on) {
0722         /* All frame types accepted*/
0723         rx_frame_filter_reg &= ~(IAR_RX_FRAME_FLT_FRM_VER);
0724         rx_frame_filter_reg |= (IAR_RX_FRAME_FLT_ACK_FT |
0725                   IAR_RX_FRAME_FLT_NS_FT);
0726 
0727         ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
0728                      DAR_PHY_CTRL4_PROMISCUOUS,
0729                      DAR_PHY_CTRL4_PROMISCUOUS);
0730         if (ret < 0)
0731             return ret;
0732 
0733         ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,
0734                    rx_frame_filter_reg);
0735         if (ret < 0)
0736             return ret;
0737     } else {
0738         ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
0739                      DAR_PHY_CTRL4_PROMISCUOUS, 0x0);
0740         if (ret < 0)
0741             return ret;
0742 
0743         ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,
0744                    IAR_RX_FRAME_FLT_FRM_VER |
0745                    IAR_RX_FRAME_FLT_BEACON_FT |
0746                    IAR_RX_FRAME_FLT_DATA_FT |
0747                    IAR_RX_FRAME_FLT_CMD_FT);
0748         if (ret < 0)
0749             return ret;
0750     }
0751 
0752     return 0;
0753 }
0754 
0755 static const struct ieee802154_ops mcr20a_hw_ops = {
0756     .owner          = THIS_MODULE,
0757     .xmit_async     = mcr20a_xmit,
0758     .ed         = mcr20a_ed,
0759     .set_channel        = mcr20a_set_channel,
0760     .start          = mcr20a_start,
0761     .stop           = mcr20a_stop,
0762     .set_hw_addr_filt   = mcr20a_set_hw_addr_filt,
0763     .set_txpower        = mcr20a_set_txpower,
0764     .set_cca_mode       = mcr20a_set_cca_mode,
0765     .set_cca_ed_level   = mcr20a_set_cca_ed_level,
0766     .set_promiscuous_mode   = mcr20a_set_promiscuous_mode,
0767 };
0768 
0769 static int
0770 mcr20a_request_rx(struct mcr20a_local *lp)
0771 {
0772     dev_dbg(printdev(lp), "%s\n", __func__);
0773 
0774     /* Start the RX sequence */
0775     regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1,
0776                  DAR_PHY_CTRL1_XCVSEQ_MASK, MCR20A_XCVSEQ_RX);
0777 
0778     return 0;
0779 }
0780 
0781 static void
0782 mcr20a_handle_rx_read_buf_complete(void *context)
0783 {
0784     struct mcr20a_local *lp = context;
0785     u8 len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK;
0786     struct sk_buff *skb;
0787 
0788     dev_dbg(printdev(lp), "%s\n", __func__);
0789 
0790     dev_dbg(printdev(lp), "RX is done\n");
0791 
0792     if (!ieee802154_is_valid_psdu_len(len)) {
0793         dev_vdbg(&lp->spi->dev, "corrupted frame received\n");
0794         len = IEEE802154_MTU;
0795     }
0796 
0797     len = len - 2;  /* get rid of frame check field */
0798 
0799     skb = dev_alloc_skb(len);
0800     if (!skb)
0801         return;
0802 
0803     __skb_put_data(skb, lp->rx_buf, len);
0804     ieee802154_rx_irqsafe(lp->hw, skb, lp->rx_lqi[0]);
0805 
0806     print_hex_dump_debug("mcr20a rx: ", DUMP_PREFIX_OFFSET, 16, 1,
0807                  lp->rx_buf, len, 0);
0808     pr_debug("mcr20a rx: lqi: %02hhx\n", lp->rx_lqi[0]);
0809 
0810     /* start RX sequence */
0811     mcr20a_request_rx(lp);
0812 }
0813 
0814 static void
0815 mcr20a_handle_rx_read_len_complete(void *context)
0816 {
0817     struct mcr20a_local *lp = context;
0818     u8 len;
0819     int ret;
0820 
0821     dev_dbg(printdev(lp), "%s\n", __func__);
0822 
0823     /* get the length of received frame */
0824     len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK;
0825     dev_dbg(printdev(lp), "frame len : %d\n", len);
0826 
0827     /* prepare to read the rx buf */
0828     lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete;
0829     lp->rx_header[0] = MCR20A_BURST_READ_PACKET_BUF;
0830     lp->rx_xfer_buf.len = len;
0831 
0832     ret = spi_async(lp->spi, &lp->rx_buf_msg);
0833     if (ret)
0834         dev_err(printdev(lp), "failed to read rx buffer length\n");
0835 }
0836 
0837 static int
0838 mcr20a_handle_rx(struct mcr20a_local *lp)
0839 {
0840     dev_dbg(printdev(lp), "%s\n", __func__);
0841     lp->reg_msg.complete = mcr20a_handle_rx_read_len_complete;
0842     lp->reg_cmd[0] = MCR20A_READ_REG(DAR_RX_FRM_LEN);
0843     lp->reg_xfer_data.len   = 1;
0844 
0845     return spi_async(lp->spi, &lp->reg_msg);
0846 }
0847 
0848 static int
0849 mcr20a_handle_tx_complete(struct mcr20a_local *lp)
0850 {
0851     dev_dbg(printdev(lp), "%s\n", __func__);
0852 
0853     ieee802154_xmit_complete(lp->hw, lp->tx_skb, false);
0854 
0855     return mcr20a_request_rx(lp);
0856 }
0857 
0858 static int
0859 mcr20a_handle_tx(struct mcr20a_local *lp)
0860 {
0861     int ret;
0862 
0863     dev_dbg(printdev(lp), "%s\n", __func__);
0864 
0865     /* write tx buffer */
0866     lp->tx_header[0]    = MCR20A_BURST_WRITE_PACKET_BUF;
0867     /* add 2 bytes of FCS */
0868     lp->tx_len[0]       = lp->tx_skb->len + 2;
0869     lp->tx_xfer_buf.tx_buf  = lp->tx_skb->data;
0870     /* add 1 byte psduLength */
0871     lp->tx_xfer_buf.len = lp->tx_skb->len + 1;
0872 
0873     ret = spi_async(lp->spi, &lp->tx_buf_msg);
0874     if (ret) {
0875         dev_err(printdev(lp), "SPI write Failed for TX buf\n");
0876         return ret;
0877     }
0878 
0879     return 0;
0880 }
0881 
0882 static void
0883 mcr20a_irq_clean_complete(void *context)
0884 {
0885     struct mcr20a_local *lp = context;
0886     u8 seq_state = lp->irq_data[DAR_IRQ_STS1] & DAR_PHY_CTRL1_XCVSEQ_MASK;
0887 
0888     dev_dbg(printdev(lp), "%s\n", __func__);
0889 
0890     enable_irq(lp->spi->irq);
0891 
0892     dev_dbg(printdev(lp), "IRQ STA1 (%02x) STA2 (%02x)\n",
0893         lp->irq_data[DAR_IRQ_STS1], lp->irq_data[DAR_IRQ_STS2]);
0894 
0895     switch (seq_state) {
0896     /* TX IRQ, RX IRQ and SEQ IRQ */
0897     case (DAR_IRQSTS1_TXIRQ | DAR_IRQSTS1_SEQIRQ):
0898         if (lp->is_tx) {
0899             lp->is_tx = 0;
0900             dev_dbg(printdev(lp), "TX is done. No ACK\n");
0901             mcr20a_handle_tx_complete(lp);
0902         }
0903         break;
0904     case (DAR_IRQSTS1_RXIRQ | DAR_IRQSTS1_SEQIRQ):
0905         /* rx is starting */
0906         dev_dbg(printdev(lp), "RX is starting\n");
0907         mcr20a_handle_rx(lp);
0908         break;
0909     case (DAR_IRQSTS1_RXIRQ | DAR_IRQSTS1_TXIRQ | DAR_IRQSTS1_SEQIRQ):
0910         if (lp->is_tx) {
0911             /* tx is done */
0912             lp->is_tx = 0;
0913             dev_dbg(printdev(lp), "TX is done. Get ACK\n");
0914             mcr20a_handle_tx_complete(lp);
0915         } else {
0916             /* rx is starting */
0917             dev_dbg(printdev(lp), "RX is starting\n");
0918             mcr20a_handle_rx(lp);
0919         }
0920         break;
0921     case (DAR_IRQSTS1_SEQIRQ):
0922         if (lp->is_tx) {
0923             dev_dbg(printdev(lp), "TX is starting\n");
0924             mcr20a_handle_tx(lp);
0925         } else {
0926             dev_dbg(printdev(lp), "MCR20A is stop\n");
0927         }
0928         break;
0929     }
0930 }
0931 
0932 static void mcr20a_irq_status_complete(void *context)
0933 {
0934     int ret;
0935     struct mcr20a_local *lp = context;
0936 
0937     dev_dbg(printdev(lp), "%s\n", __func__);
0938     regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1,
0939                  DAR_PHY_CTRL1_XCVSEQ_MASK, MCR20A_XCVSEQ_IDLE);
0940 
0941     lp->reg_msg.complete = mcr20a_irq_clean_complete;
0942     lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_IRQ_STS1);
0943     memcpy(lp->reg_data, lp->irq_data, MCR20A_IRQSTS_NUM);
0944     lp->reg_xfer_data.len = MCR20A_IRQSTS_NUM;
0945 
0946     ret = spi_async(lp->spi, &lp->reg_msg);
0947 
0948     if (ret)
0949         dev_err(printdev(lp), "failed to clean irq status\n");
0950 }
0951 
0952 static irqreturn_t mcr20a_irq_isr(int irq, void *data)
0953 {
0954     struct mcr20a_local *lp = data;
0955     int ret;
0956 
0957     disable_irq_nosync(irq);
0958 
0959     lp->irq_header[0] = MCR20A_READ_REG(DAR_IRQ_STS1);
0960     /* read IRQSTSx */
0961     ret = spi_async(lp->spi, &lp->irq_msg);
0962     if (ret) {
0963         enable_irq(irq);
0964         return IRQ_NONE;
0965     }
0966 
0967     return IRQ_HANDLED;
0968 }
0969 
0970 static void mcr20a_hw_setup(struct mcr20a_local *lp)
0971 {
0972     u8 i;
0973     struct ieee802154_hw *hw = lp->hw;
0974     struct wpan_phy *phy = lp->hw->phy;
0975 
0976     dev_dbg(printdev(lp), "%s\n", __func__);
0977 
0978     hw->flags = IEEE802154_HW_TX_OMIT_CKSUM |
0979             IEEE802154_HW_AFILT |
0980             IEEE802154_HW_PROMISCUOUS;
0981 
0982     phy->flags = WPAN_PHY_FLAG_TXPOWER | WPAN_PHY_FLAG_CCA_ED_LEVEL |
0983             WPAN_PHY_FLAG_CCA_MODE;
0984 
0985     phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
0986         BIT(NL802154_CCA_CARRIER) | BIT(NL802154_CCA_ENERGY_CARRIER);
0987     phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) |
0988         BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR);
0989 
0990     /* initiating cca_ed_levels */
0991     for (i = MCR20A_MAX_CCA_THRESHOLD; i < MCR20A_MIN_CCA_THRESHOLD + 1;
0992           ++i) {
0993         mcr20a_ed_levels[i] =  -i * 100;
0994     }
0995 
0996     phy->supported.cca_ed_levels = mcr20a_ed_levels;
0997     phy->supported.cca_ed_levels_size = ARRAY_SIZE(mcr20a_ed_levels);
0998 
0999     phy->cca.mode = NL802154_CCA_ENERGY;
1000 
1001     phy->supported.channels[0] = MCR20A_VALID_CHANNELS;
1002     phy->current_page = 0;
1003     /* MCR20A default reset value */
1004     phy->current_channel = 20;
1005     phy->supported.tx_powers = mcr20a_powers;
1006     phy->supported.tx_powers_size = ARRAY_SIZE(mcr20a_powers);
1007     phy->cca_ed_level = phy->supported.cca_ed_levels[75];
1008     phy->transmit_power = phy->supported.tx_powers[0x0F];
1009 }
1010 
1011 static void
1012 mcr20a_setup_tx_spi_messages(struct mcr20a_local *lp)
1013 {
1014     spi_message_init(&lp->tx_buf_msg);
1015     lp->tx_buf_msg.context = lp;
1016     lp->tx_buf_msg.complete = mcr20a_write_tx_buf_complete;
1017 
1018     lp->tx_xfer_header.len = 1;
1019     lp->tx_xfer_header.tx_buf = lp->tx_header;
1020 
1021     lp->tx_xfer_len.len = 1;
1022     lp->tx_xfer_len.tx_buf = lp->tx_len;
1023 
1024     spi_message_add_tail(&lp->tx_xfer_header, &lp->tx_buf_msg);
1025     spi_message_add_tail(&lp->tx_xfer_len, &lp->tx_buf_msg);
1026     spi_message_add_tail(&lp->tx_xfer_buf, &lp->tx_buf_msg);
1027 }
1028 
1029 static void
1030 mcr20a_setup_rx_spi_messages(struct mcr20a_local *lp)
1031 {
1032     spi_message_init(&lp->reg_msg);
1033     lp->reg_msg.context = lp;
1034 
1035     lp->reg_xfer_cmd.len = 1;
1036     lp->reg_xfer_cmd.tx_buf = lp->reg_cmd;
1037     lp->reg_xfer_cmd.rx_buf = lp->reg_cmd;
1038 
1039     lp->reg_xfer_data.rx_buf = lp->reg_data;
1040     lp->reg_xfer_data.tx_buf = lp->reg_data;
1041 
1042     spi_message_add_tail(&lp->reg_xfer_cmd, &lp->reg_msg);
1043     spi_message_add_tail(&lp->reg_xfer_data, &lp->reg_msg);
1044 
1045     spi_message_init(&lp->rx_buf_msg);
1046     lp->rx_buf_msg.context = lp;
1047     lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete;
1048     lp->rx_xfer_header.len = 1;
1049     lp->rx_xfer_header.tx_buf = lp->rx_header;
1050     lp->rx_xfer_header.rx_buf = lp->rx_header;
1051 
1052     lp->rx_xfer_buf.rx_buf = lp->rx_buf;
1053 
1054     lp->rx_xfer_lqi.len = 1;
1055     lp->rx_xfer_lqi.rx_buf = lp->rx_lqi;
1056 
1057     spi_message_add_tail(&lp->rx_xfer_header, &lp->rx_buf_msg);
1058     spi_message_add_tail(&lp->rx_xfer_buf, &lp->rx_buf_msg);
1059     spi_message_add_tail(&lp->rx_xfer_lqi, &lp->rx_buf_msg);
1060 }
1061 
1062 static void
1063 mcr20a_setup_irq_spi_messages(struct mcr20a_local *lp)
1064 {
1065     spi_message_init(&lp->irq_msg);
1066     lp->irq_msg.context     = lp;
1067     lp->irq_msg.complete    = mcr20a_irq_status_complete;
1068     lp->irq_xfer_header.len = 1;
1069     lp->irq_xfer_header.tx_buf = lp->irq_header;
1070     lp->irq_xfer_header.rx_buf = lp->irq_header;
1071 
1072     lp->irq_xfer_data.len   = MCR20A_IRQSTS_NUM;
1073     lp->irq_xfer_data.rx_buf = lp->irq_data;
1074 
1075     spi_message_add_tail(&lp->irq_xfer_header, &lp->irq_msg);
1076     spi_message_add_tail(&lp->irq_xfer_data, &lp->irq_msg);
1077 }
1078 
1079 static int
1080 mcr20a_phy_init(struct mcr20a_local *lp)
1081 {
1082     u8 index;
1083     unsigned int phy_reg = 0;
1084     int ret;
1085 
1086     dev_dbg(printdev(lp), "%s\n", __func__);
1087 
1088     /* Disable Tristate on COCO MISO for SPI reads */
1089     ret = regmap_write(lp->regmap_iar, IAR_MISC_PAD_CTRL, 0x02);
1090     if (ret)
1091         goto err_ret;
1092 
1093     /* Clear all PP IRQ bits in IRQSTS1 to avoid unexpected interrupts
1094      * immediately after init
1095      */
1096     ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS1, 0xEF);
1097     if (ret)
1098         goto err_ret;
1099 
1100     /* Clear all PP IRQ bits in IRQSTS2 */
1101     ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS2,
1102                DAR_IRQSTS2_ASM_IRQ | DAR_IRQSTS2_PB_ERR_IRQ |
1103                DAR_IRQSTS2_WAKE_IRQ);
1104     if (ret)
1105         goto err_ret;
1106 
1107     /* Disable all timer interrupts */
1108     ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS3, 0xFF);
1109     if (ret)
1110         goto err_ret;
1111 
1112     /*  PHY_CTRL1 : default HW settings + AUTOACK enabled */
1113     ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
1114                  DAR_PHY_CTRL1_AUTOACK, DAR_PHY_CTRL1_AUTOACK);
1115 
1116     /*  PHY_CTRL2 : disable all interrupts */
1117     ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL2, 0xFF);
1118     if (ret)
1119         goto err_ret;
1120 
1121     /* PHY_CTRL3 : disable all timers and remaining interrupts */
1122     ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL3,
1123                DAR_PHY_CTRL3_ASM_MSK | DAR_PHY_CTRL3_PB_ERR_MSK |
1124                DAR_PHY_CTRL3_WAKE_MSK);
1125     if (ret)
1126         goto err_ret;
1127 
1128     /* SRC_CTRL : enable Acknowledge Frame Pending and
1129      * Source Address Matching Enable
1130      */
1131     ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL,
1132                DAR_SRC_CTRL_ACK_FRM_PND |
1133                (DAR_SRC_CTRL_INDEX << DAR_SRC_CTRL_INDEX_SHIFT));
1134     if (ret)
1135         goto err_ret;
1136 
1137     /*  RX_FRAME_FILTER */
1138     /*  FRM_VER[1:0] = b11. Accept FrameVersion 0 and 1 packets */
1139     ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,
1140                IAR_RX_FRAME_FLT_FRM_VER |
1141                IAR_RX_FRAME_FLT_BEACON_FT |
1142                IAR_RX_FRAME_FLT_DATA_FT |
1143                IAR_RX_FRAME_FLT_CMD_FT);
1144     if (ret)
1145         goto err_ret;
1146 
1147     dev_info(printdev(lp), "MCR20A DAR overwrites version: 0x%02x\n",
1148          MCR20A_OVERWRITE_VERSION);
1149 
1150     /* Overwrites direct registers  */
1151     ret = regmap_write(lp->regmap_dar, DAR_OVERWRITE_VER,
1152                MCR20A_OVERWRITE_VERSION);
1153     if (ret)
1154         goto err_ret;
1155 
1156     /* Overwrites indirect registers  */
1157     ret = regmap_multi_reg_write(lp->regmap_iar, mar20a_iar_overwrites,
1158                      ARRAY_SIZE(mar20a_iar_overwrites));
1159     if (ret)
1160         goto err_ret;
1161 
1162     /* Clear HW indirect queue */
1163     dev_dbg(printdev(lp), "clear HW indirect queue\n");
1164     for (index = 0; index < MCR20A_PHY_INDIRECT_QUEUE_SIZE; index++) {
1165         phy_reg = (u8)(((index & DAR_SRC_CTRL_INDEX) <<
1166                    DAR_SRC_CTRL_INDEX_SHIFT)
1167                   | (DAR_SRC_CTRL_SRCADDR_EN)
1168                   | (DAR_SRC_CTRL_INDEX_DISABLE));
1169         ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL, phy_reg);
1170         if (ret)
1171             goto err_ret;
1172         phy_reg = 0;
1173     }
1174 
1175     /* Assign HW Indirect hash table to PAN0 */
1176     ret = regmap_read(lp->regmap_iar, IAR_DUAL_PAN_CTRL, &phy_reg);
1177     if (ret)
1178         goto err_ret;
1179 
1180     /* Clear current lvl */
1181     phy_reg &= ~IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK;
1182 
1183     /* Set new lvl */
1184     phy_reg |= MCR20A_PHY_INDIRECT_QUEUE_SIZE <<
1185         IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT;
1186     ret = regmap_write(lp->regmap_iar, IAR_DUAL_PAN_CTRL, phy_reg);
1187     if (ret)
1188         goto err_ret;
1189 
1190     /* Set CCA threshold to -75 dBm */
1191     ret = regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, 0x4B);
1192     if (ret)
1193         goto err_ret;
1194 
1195     /* Set prescaller to obtain 1 symbol (16us) timebase */
1196     ret = regmap_write(lp->regmap_iar, IAR_TMR_PRESCALE, 0x05);
1197     if (ret)
1198         goto err_ret;
1199 
1200     /* Enable autodoze mode. */
1201     ret = regmap_update_bits(lp->regmap_dar, DAR_PWR_MODES,
1202                  DAR_PWR_MODES_AUTODOZE,
1203                  DAR_PWR_MODES_AUTODOZE);
1204     if (ret)
1205         goto err_ret;
1206 
1207     /* Disable clk_out */
1208     ret = regmap_update_bits(lp->regmap_dar, DAR_CLK_OUT_CTRL,
1209                  DAR_CLK_OUT_CTRL_EN, 0x0);
1210     if (ret)
1211         goto err_ret;
1212 
1213     return 0;
1214 
1215 err_ret:
1216     return ret;
1217 }
1218 
1219 static int
1220 mcr20a_probe(struct spi_device *spi)
1221 {
1222     struct ieee802154_hw *hw;
1223     struct mcr20a_local *lp;
1224     struct gpio_desc *rst_b;
1225     int irq_type;
1226     int ret = -ENOMEM;
1227 
1228     dev_dbg(&spi->dev, "%s\n", __func__);
1229 
1230     if (!spi->irq) {
1231         dev_err(&spi->dev, "no IRQ specified\n");
1232         return -EINVAL;
1233     }
1234 
1235     rst_b = devm_gpiod_get(&spi->dev, "rst_b", GPIOD_OUT_HIGH);
1236     if (IS_ERR(rst_b)) {
1237         ret = PTR_ERR(rst_b);
1238         if (ret != -EPROBE_DEFER)
1239             dev_err(&spi->dev, "Failed to get 'rst_b' gpio: %d", ret);
1240         return ret;
1241     }
1242 
1243     /* reset mcr20a */
1244     usleep_range(10, 20);
1245     gpiod_set_value_cansleep(rst_b, 1);
1246     usleep_range(10, 20);
1247     gpiod_set_value_cansleep(rst_b, 0);
1248     usleep_range(120, 240);
1249 
1250     /* allocate ieee802154_hw and private data */
1251     hw = ieee802154_alloc_hw(sizeof(*lp), &mcr20a_hw_ops);
1252     if (!hw) {
1253         dev_crit(&spi->dev, "ieee802154_alloc_hw failed\n");
1254         return ret;
1255     }
1256 
1257     /* init mcr20a local data */
1258     lp = hw->priv;
1259     lp->hw = hw;
1260     lp->spi = spi;
1261 
1262     /* init ieee802154_hw */
1263     hw->parent = &spi->dev;
1264     ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
1265 
1266     /* init buf */
1267     lp->buf = devm_kzalloc(&spi->dev, SPI_COMMAND_BUFFER, GFP_KERNEL);
1268 
1269     if (!lp->buf) {
1270         ret = -ENOMEM;
1271         goto free_dev;
1272     }
1273 
1274     mcr20a_setup_tx_spi_messages(lp);
1275     mcr20a_setup_rx_spi_messages(lp);
1276     mcr20a_setup_irq_spi_messages(lp);
1277 
1278     /* setup regmap */
1279     lp->regmap_dar = devm_regmap_init_spi(spi, &mcr20a_dar_regmap);
1280     if (IS_ERR(lp->regmap_dar)) {
1281         ret = PTR_ERR(lp->regmap_dar);
1282         dev_err(&spi->dev, "Failed to allocate dar map: %d\n",
1283             ret);
1284         goto free_dev;
1285     }
1286 
1287     lp->regmap_iar = devm_regmap_init_spi(spi, &mcr20a_iar_regmap);
1288     if (IS_ERR(lp->regmap_iar)) {
1289         ret = PTR_ERR(lp->regmap_iar);
1290         dev_err(&spi->dev, "Failed to allocate iar map: %d\n", ret);
1291         goto free_dev;
1292     }
1293 
1294     mcr20a_hw_setup(lp);
1295 
1296     spi_set_drvdata(spi, lp);
1297 
1298     ret = mcr20a_phy_init(lp);
1299     if (ret < 0) {
1300         dev_crit(&spi->dev, "mcr20a_phy_init failed\n");
1301         goto free_dev;
1302     }
1303 
1304     irq_type = irq_get_trigger_type(spi->irq);
1305     if (!irq_type)
1306         irq_type = IRQF_TRIGGER_FALLING;
1307 
1308     ret = devm_request_irq(&spi->dev, spi->irq, mcr20a_irq_isr,
1309                    irq_type, dev_name(&spi->dev), lp);
1310     if (ret) {
1311         dev_err(&spi->dev, "could not request_irq for mcr20a\n");
1312         ret = -ENODEV;
1313         goto free_dev;
1314     }
1315 
1316     /* disable_irq by default and wait for starting hardware */
1317     disable_irq(spi->irq);
1318 
1319     ret = ieee802154_register_hw(hw);
1320     if (ret) {
1321         dev_crit(&spi->dev, "ieee802154_register_hw failed\n");
1322         goto free_dev;
1323     }
1324 
1325     return ret;
1326 
1327 free_dev:
1328     ieee802154_free_hw(lp->hw);
1329 
1330     return ret;
1331 }
1332 
1333 static void mcr20a_remove(struct spi_device *spi)
1334 {
1335     struct mcr20a_local *lp = spi_get_drvdata(spi);
1336 
1337     dev_dbg(&spi->dev, "%s\n", __func__);
1338 
1339     ieee802154_unregister_hw(lp->hw);
1340     ieee802154_free_hw(lp->hw);
1341 }
1342 
1343 static const struct of_device_id mcr20a_of_match[] = {
1344     { .compatible = "nxp,mcr20a", },
1345     { },
1346 };
1347 MODULE_DEVICE_TABLE(of, mcr20a_of_match);
1348 
1349 static const struct spi_device_id mcr20a_device_id[] = {
1350     { .name = "mcr20a", },
1351     { },
1352 };
1353 MODULE_DEVICE_TABLE(spi, mcr20a_device_id);
1354 
1355 static struct spi_driver mcr20a_driver = {
1356     .id_table = mcr20a_device_id,
1357     .driver = {
1358         .of_match_table = of_match_ptr(mcr20a_of_match),
1359         .name   = "mcr20a",
1360     },
1361     .probe      = mcr20a_probe,
1362     .remove     = mcr20a_remove,
1363 };
1364 
1365 module_spi_driver(mcr20a_driver);
1366 
1367 MODULE_DESCRIPTION("MCR20A Transceiver Driver");
1368 MODULE_LICENSE("GPL v2");
1369 MODULE_AUTHOR("Xue Liu <liuxuenetmail@gmail>");
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