net/ieee802154/at86rf230.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * AT86RF230/RF231 driver
0004  *
0005  * Copyright (C) 2009-2012 Siemens AG
0006  *
0007  * Written by:
0008  * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
0009  * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
0010  */
0011
0012 #ifndef _AT86RF230_H
0013 #define _AT86RF230_H
0014
0015 #define RG_TRX_STATUS   (0x01)
0016 #define SR_TRX_STATUS       0x01, 0x1f, 0
0017 #define SR_RESERVED_01_3    0x01, 0x20, 5
0018 #define SR_CCA_STATUS       0x01, 0x40, 6
0019 #define SR_CCA_DONE     0x01, 0x80, 7
0020 #define RG_TRX_STATE    (0x02)
0021 #define SR_TRX_CMD      0x02, 0x1f, 0
0022 #define SR_TRAC_STATUS      0x02, 0xe0, 5
0023 #define RG_TRX_CTRL_0   (0x03)
0024 #define SR_CLKM_CTRL        0x03, 0x07, 0
0025 #define SR_CLKM_SHA_SEL     0x03, 0x08, 3
0026 #define SR_PAD_IO_CLKM      0x03, 0x30, 4
0027 #define SR_PAD_IO       0x03, 0xc0, 6
0028 #define RG_TRX_CTRL_1   (0x04)
0029 #define SR_IRQ_POLARITY     0x04, 0x01, 0
0030 #define SR_IRQ_MASK_MODE    0x04, 0x02, 1
0031 #define SR_SPI_CMD_MODE     0x04, 0x0c, 2
0032 #define SR_RX_BL_CTRL       0x04, 0x10, 4
0033 #define SR_TX_AUTO_CRC_ON   0x04, 0x20, 5
0034 #define SR_IRQ_2_EXT_EN     0x04, 0x40, 6
0035 #define SR_PA_EXT_EN        0x04, 0x80, 7
0036 #define RG_PHY_TX_PWR   (0x05)
0037 #define SR_TX_PWR_23X       0x05, 0x0f, 0
0038 #define SR_PA_LT_230        0x05, 0x30, 4
0039 #define SR_PA_BUF_LT_230    0x05, 0xc0, 6
0040 #define SR_TX_PWR_212       0x05, 0x1f, 0
0041 #define SR_GC_PA_212        0x05, 0x60, 5
0042 #define SR_PA_BOOST_LT_212  0x05, 0x80, 7
0043 #define RG_PHY_RSSI (0x06)
0044 #define SR_RSSI         0x06, 0x1f, 0
0045 #define SR_RND_VALUE        0x06, 0x60, 5
0046 #define SR_RX_CRC_VALID     0x06, 0x80, 7
0047 #define RG_PHY_ED_LEVEL (0x07)
0048 #define SR_ED_LEVEL     0x07, 0xff, 0
0049 #define RG_PHY_CC_CCA   (0x08)
0050 #define SR_CHANNEL      0x08, 0x1f, 0
0051 #define SR_CCA_MODE     0x08, 0x60, 5
0052 #define SR_CCA_REQUEST      0x08, 0x80, 7
0053 #define RG_CCA_THRES    (0x09)
0054 #define SR_CCA_ED_THRES     0x09, 0x0f, 0
0055 #define SR_RESERVED_09_1    0x09, 0xf0, 4
0056 #define RG_RX_CTRL  (0x0a)
0057 #define SR_PDT_THRES        0x0a, 0x0f, 0
0058 #define SR_RESERVED_0a_1    0x0a, 0xf0, 4
0059 #define RG_SFD_VALUE    (0x0b)
0060 #define SR_SFD_VALUE        0x0b, 0xff, 0
0061 #define RG_TRX_CTRL_2   (0x0c)
0062 #define SR_OQPSK_DATA_RATE  0x0c, 0x03, 0
0063 #define SR_SUB_MODE     0x0c, 0x04, 2
0064 #define SR_BPSK_QPSK        0x0c, 0x08, 3
0065 #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4
0066 #define SR_RESERVED_0c_5    0x0c, 0x60, 5
0067 #define SR_RX_SAFE_MODE     0x0c, 0x80, 7
0068 #define RG_ANT_DIV  (0x0d)
0069 #define SR_ANT_CTRL     0x0d, 0x03, 0
0070 #define SR_ANT_EXT_SW_EN    0x0d, 0x04, 2
0071 #define SR_ANT_DIV_EN       0x0d, 0x08, 3
0072 #define SR_RESERVED_0d_2    0x0d, 0x70, 4
0073 #define SR_ANT_SEL      0x0d, 0x80, 7
0074 #define RG_IRQ_MASK (0x0e)
0075 #define SR_IRQ_MASK     0x0e, 0xff, 0
0076 #define RG_IRQ_STATUS   (0x0f)
0077 #define SR_IRQ_0_PLL_LOCK   0x0f, 0x01, 0
0078 #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
0079 #define SR_IRQ_2_RX_START   0x0f, 0x04, 2
0080 #define SR_IRQ_3_TRX_END    0x0f, 0x08, 3
0081 #define SR_IRQ_4_CCA_ED_DONE    0x0f, 0x10, 4
0082 #define SR_IRQ_5_AMI        0x0f, 0x20, 5
0083 #define SR_IRQ_6_TRX_UR     0x0f, 0x40, 6
0084 #define SR_IRQ_7_BAT_LOW    0x0f, 0x80, 7
0085 #define RG_VREG_CTRL    (0x10)
0086 #define SR_RESERVED_10_6    0x10, 0x03, 0
0087 #define SR_DVDD_OK      0x10, 0x04, 2
0088 #define SR_DVREG_EXT        0x10, 0x08, 3
0089 #define SR_RESERVED_10_3    0x10, 0x30, 4
0090 #define SR_AVDD_OK      0x10, 0x40, 6
0091 #define SR_AVREG_EXT        0x10, 0x80, 7
0092 #define RG_BATMON   (0x11)
0093 #define SR_BATMON_VTH       0x11, 0x0f, 0
0094 #define SR_BATMON_HR        0x11, 0x10, 4
0095 #define SR_BATMON_OK        0x11, 0x20, 5
0096 #define SR_RESERVED_11_1    0x11, 0xc0, 6
0097 #define RG_XOSC_CTRL    (0x12)
0098 #define SR_XTAL_TRIM        0x12, 0x0f, 0
0099 #define SR_XTAL_MODE        0x12, 0xf0, 4
0100 #define RG_RX_SYN   (0x15)
0101 #define SR_RX_PDT_LEVEL     0x15, 0x0f, 0
0102 #define SR_RESERVED_15_2    0x15, 0x70, 4
0103 #define SR_RX_PDT_DIS       0x15, 0x80, 7
0104 #define RG_XAH_CTRL_1   (0x17)
0105 #define SR_RESERVED_17_8    0x17, 0x01, 0
0106 #define SR_AACK_PROM_MODE   0x17, 0x02, 1
0107 #define SR_AACK_ACK_TIME    0x17, 0x04, 2
0108 #define SR_RESERVED_17_5    0x17, 0x08, 3
0109 #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
0110 #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
0111 #define SR_CSMA_LBT_MODE    0x17, 0x40, 6
0112 #define SR_RESERVED_17_1    0x17, 0x80, 7
0113 #define RG_FTN_CTRL (0x18)
0114 #define SR_RESERVED_18_2    0x18, 0x7f, 0
0115 #define SR_FTN_START        0x18, 0x80, 7
0116 #define RG_PLL_CF   (0x1a)
0117 #define SR_RESERVED_1a_2    0x1a, 0x7f, 0
0118 #define SR_PLL_CF_START     0x1a, 0x80, 7
0119 #define RG_PLL_DCU  (0x1b)
0120 #define SR_RESERVED_1b_3    0x1b, 0x3f, 0
0121 #define SR_RESERVED_1b_2    0x1b, 0x40, 6
0122 #define SR_PLL_DCU_START    0x1b, 0x80, 7
0123 #define RG_PART_NUM (0x1c)
0124 #define SR_PART_NUM     0x1c, 0xff, 0
0125 #define RG_VERSION_NUM  (0x1d)
0126 #define SR_VERSION_NUM      0x1d, 0xff, 0
0127 #define RG_MAN_ID_0 (0x1e)
0128 #define SR_MAN_ID_0     0x1e, 0xff, 0
0129 #define RG_MAN_ID_1 (0x1f)
0130 #define SR_MAN_ID_1     0x1f, 0xff, 0
0131 #define RG_SHORT_ADDR_0 (0x20)
0132 #define SR_SHORT_ADDR_0     0x20, 0xff, 0
0133 #define RG_SHORT_ADDR_1 (0x21)
0134 #define SR_SHORT_ADDR_1     0x21, 0xff, 0
0135 #define RG_PAN_ID_0 (0x22)
0136 #define SR_PAN_ID_0     0x22, 0xff, 0
0137 #define RG_PAN_ID_1 (0x23)
0138 #define SR_PAN_ID_1     0x23, 0xff, 0
0139 #define RG_IEEE_ADDR_0  (0x24)
0140 #define SR_IEEE_ADDR_0      0x24, 0xff, 0
0141 #define RG_IEEE_ADDR_1  (0x25)
0142 #define SR_IEEE_ADDR_1      0x25, 0xff, 0
0143 #define RG_IEEE_ADDR_2  (0x26)
0144 #define SR_IEEE_ADDR_2      0x26, 0xff, 0
0145 #define RG_IEEE_ADDR_3  (0x27)
0146 #define SR_IEEE_ADDR_3      0x27, 0xff, 0
0147 #define RG_IEEE_ADDR_4  (0x28)
0148 #define SR_IEEE_ADDR_4      0x28, 0xff, 0
0149 #define RG_IEEE_ADDR_5  (0x29)
0150 #define SR_IEEE_ADDR_5      0x29, 0xff, 0
0151 #define RG_IEEE_ADDR_6  (0x2a)
0152 #define SR_IEEE_ADDR_6      0x2a, 0xff, 0
0153 #define RG_IEEE_ADDR_7  (0x2b)
0154 #define SR_IEEE_ADDR_7      0x2b, 0xff, 0
0155 #define RG_XAH_CTRL_0   (0x2c)
0156 #define SR_SLOTTED_OPERATION    0x2c, 0x01, 0
0157 #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
0158 #define SR_MAX_FRAME_RETRIES    0x2c, 0xf0, 4
0159 #define RG_CSMA_SEED_0  (0x2d)
0160 #define SR_CSMA_SEED_0      0x2d, 0xff, 0
0161 #define RG_CSMA_SEED_1  (0x2e)
0162 #define SR_CSMA_SEED_1      0x2e, 0x07, 0
0163 #define SR_AACK_I_AM_COORD  0x2e, 0x08, 3
0164 #define SR_AACK_DIS_ACK     0x2e, 0x10, 4
0165 #define SR_AACK_SET_PD      0x2e, 0x20, 5
0166 #define SR_AACK_FVN_MODE    0x2e, 0xc0, 6
0167 #define RG_CSMA_BE  (0x2f)
0168 #define SR_MIN_BE       0x2f, 0x0f, 0
0169 #define SR_MAX_BE       0x2f, 0xf0, 4
0170
0171 #define CMD_REG     0x80
0172 #define CMD_REG_MASK    0x3f
0173 #define CMD_WRITE   0x40
0174 #define CMD_FB      0x20
0175
0176 #define IRQ_BAT_LOW BIT(7)
0177 #define IRQ_TRX_UR  BIT(6)
0178 #define IRQ_AMI     BIT(5)
0179 #define IRQ_CCA_ED  BIT(4)
0180 #define IRQ_TRX_END BIT(3)
0181 #define IRQ_RX_START    BIT(2)
0182 #define IRQ_PLL_UNL BIT(1)
0183 #define IRQ_PLL_LOCK    BIT(0)
0184
0185 #define IRQ_ACTIVE_HIGH 0
0186 #define IRQ_ACTIVE_LOW  1
0187
0188 #define STATE_P_ON      0x00    /* BUSY */
0189 #define STATE_BUSY_RX       0x01
0190 #define STATE_BUSY_TX       0x02
0191 #define STATE_FORCE_TRX_OFF 0x03
0192 #define STATE_FORCE_TX_ON   0x04    /* IDLE */
0193 /* 0x05 */              /* INVALID_PARAMETER */
0194 #define STATE_RX_ON     0x06
0195 /* 0x07 */              /* SUCCESS */
0196 #define STATE_TRX_OFF       0x08
0197 #define STATE_TX_ON     0x09
0198 /* 0x0a - 0x0e */           /* 0x0a - UNSUPPORTED_ATTRIBUTE */
0199 #define STATE_SLEEP     0x0F
0200 #define STATE_PREP_DEEP_SLEEP   0x10
0201 #define STATE_BUSY_RX_AACK  0x11
0202 #define STATE_BUSY_TX_ARET  0x12
0203 #define STATE_RX_AACK_ON    0x16
0204 #define STATE_TX_ARET_ON    0x19
0205 #define STATE_RX_ON_NOCLK   0x1C
0206 #define STATE_RX_AACK_ON_NOCLK  0x1D
0207 #define STATE_BUSY_RX_AACK_NOCLK 0x1E
0208 #define STATE_TRANSITION_IN_PROGRESS 0x1F
0209
0210 #define TRX_STATE_MASK      (0x1F)
0211 #define TRAC_MASK(x)        ((x & 0xe0) >> 5)
0212
0213 #define TRAC_SUCCESS            0
0214 #define TRAC_SUCCESS_DATA_PENDING   1
0215 #define TRAC_SUCCESS_WAIT_FOR_ACK   2
0216 #define TRAC_CHANNEL_ACCESS_FAILURE 3
0217 #define TRAC_NO_ACK         5
0218 #define TRAC_INVALID            7
0219
0220 #endif /* !_AT86RF230_H */