net/hamradio/z8530.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 /* 8530 Serial Communications Controller Register definitions */
0004 #define FLAG    0x7e
0005
0006 /* Write Register 0 */
0007 #define R0  0       /* Register selects */
0008 #define R1  1
0009 #define R2  2
0010 #define R3  3
0011 #define R4  4
0012 #define R5  5
0013 #define R6  6
0014 #define R7  7
0015 #define R8  8
0016 #define R9  9
0017 #define R10 10
0018 #define R11 11
0019 #define R12 12
0020 #define R13 13
0021 #define R14 14
0022 #define R15 15
0023
0024 #define NULLCODE    0   /* Null Code */
0025 #define POINT_HIGH  0x8 /* Select upper half of registers */
0026 #define RES_EXT_INT 0x10    /* Reset Ext. Status Interrupts */
0027 #define SEND_ABORT  0x18    /* HDLC Abort */
0028 #define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
0029 #define RES_Tx_P    0x28    /* Reset TxINT Pending */
0030 #define ERR_RES     0x30    /* Error Reset */
0031 #define RES_H_IUS   0x38    /* Reset highest IUS */
0032
0033 #define RES_Rx_CRC  0x40    /* Reset Rx CRC Checker */
0034 #define RES_Tx_CRC  0x80    /* Reset Tx CRC Checker */
0035 #define RES_EOM_L   0xC0    /* Reset EOM latch */
0036
0037 /* Write Register 1 */
0038
0039 #define EXT_INT_ENAB    0x1 /* Ext Int Enable */
0040 #define TxINT_ENAB  0x2 /* Tx Int Enable */
0041 #define PAR_SPEC    0x4 /* Parity is special condition */
0042
0043 #define RxINT_DISAB 0   /* Rx Int Disable */
0044 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
0045 #define INT_ALL_Rx  0x10    /* Int on all Rx Characters or error */
0046 #define INT_ERR_Rx  0x18    /* Int on error only */
0047
0048 #define WT_RDY_RT   0x20    /* Wait/Ready on R/T */
0049 #define WT_FN_RDYFN 0x40    /* Wait/FN/Ready FN */
0050 #define WT_RDY_ENAB 0x80    /* Wait/Ready Enable */
0051
0052 /* Write Register #2 (Interrupt Vector) */
0053
0054 /* Write Register 3 */
0055
0056 #define RxENABLE    0x1 /* Rx Enable */
0057 #define SYNC_L_INH  0x2 /* Sync Character Load Inhibit */
0058 #define ADD_SM      0x4 /* Address Search Mode (SDLC) */
0059 #define RxCRC_ENAB  0x8 /* Rx CRC Enable */
0060 #define ENT_HM      0x10    /* Enter Hunt Mode */
0061 #define AUTO_ENAB   0x20    /* Auto Enables */
0062 #define Rx5     0x0 /* Rx 5 Bits/Character */
0063 #define Rx7     0x40    /* Rx 7 Bits/Character */
0064 #define Rx6     0x80    /* Rx 6 Bits/Character */
0065 #define Rx8     0xc0    /* Rx 8 Bits/Character */
0066
0067 /* Write Register 4 */
0068
0069 #define PAR_ENA     0x1 /* Parity Enable */
0070 #define PAR_EVEN    0x2 /* Parity Even/Odd* */
0071
0072 #define SYNC_ENAB   0   /* Sync Modes Enable */
0073 #define SB1     0x4 /* 1 stop bit/char */
0074 #define SB15        0x8 /* 1.5 stop bits/char */
0075 #define SB2     0xc /* 2 stop bits/char */
0076
0077 #define MONSYNC     0   /* 8 Bit Sync character */
0078 #define BISYNC      0x10    /* 16 bit sync character */
0079 #define SDLC        0x20    /* SDLC Mode (01111110 Sync Flag) */
0080 #define EXTSYNC     0x30    /* External Sync Mode */
0081
0082 #define X1CLK       0x0 /* x1 clock mode */
0083 #define X16CLK      0x40    /* x16 clock mode */
0084 #define X32CLK      0x80    /* x32 clock mode */
0085 #define X64CLK      0xC0    /* x64 clock mode */
0086
0087 /* Write Register 5 */
0088
0089 #define TxCRC_ENAB  0x1 /* Tx CRC Enable */
0090 #define RTS     0x2 /* RTS */
0091 #define SDLC_CRC    0x4 /* SDLC/CRC-16 */
0092 #define TxENAB      0x8 /* Tx Enable */
0093 #define SND_BRK     0x10    /* Send Break */
0094 #define Tx5     0x0 /* Tx 5 bits (or less)/character */
0095 #define Tx7     0x20    /* Tx 7 bits/character */
0096 #define Tx6     0x40    /* Tx 6 bits/character */
0097 #define Tx8     0x60    /* Tx 8 bits/character */
0098 #define DTR     0x80    /* DTR */
0099
0100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
0101
0102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
0103
0104 /* Write Register 8 (transmit buffer) */
0105
0106 /* Write Register 9 (Master interrupt control) */
0107 #define VIS 1   /* Vector Includes Status */
0108 #define NV  2   /* No Vector */
0109 #define DLC 4   /* Disable Lower Chain */
0110 #define MIE 8   /* Master Interrupt Enable */
0111 #define STATHI  0x10    /* Status high */
0112 #define NORESET 0   /* No reset on write to R9 */
0113 #define CHRB    0x40    /* Reset channel B */
0114 #define CHRA    0x80    /* Reset channel A */
0115 #define FHWRES  0xc0    /* Force hardware reset */
0116
0117 /* Write Register 10 (misc control bits) */
0118 #define BIT6    1   /* 6 bit/8bit sync */
0119 #define LOOPMODE 2  /* SDLC Loop mode */
0120 #define ABUNDER 4   /* Abort/flag on SDLC xmit underrun */
0121 #define MARKIDLE 8  /* Mark/flag on idle */
0122 #define GAOP    0x10    /* Go active on poll */
0123 #define NRZ 0   /* NRZ mode */
0124 #define NRZI    0x20    /* NRZI mode */
0125 #define FM1 0x40    /* FM1 (transition = 1) */
0126 #define FM0 0x60    /* FM0 (transition = 0) */
0127 #define CRCPS   0x80    /* CRC Preset I/O */
0128
0129 /* Write Register 11 (Clock Mode control) */
0130 #define TRxCXT  0   /* TRxC = Xtal output */
0131 #define TRxCTC  1   /* TRxC = Transmit clock */
0132 #define TRxCBR  2   /* TRxC = BR Generator Output */
0133 #define TRxCDP  3   /* TRxC = DPLL output */
0134 #define TRxCOI  4   /* TRxC O/I */
0135 #define TCRTxCP 0   /* Transmit clock = RTxC pin */
0136 #define TCTRxCP 8   /* Transmit clock = TRxC pin */
0137 #define TCBR    0x10    /* Transmit clock = BR Generator output */
0138 #define TCDPLL  0x18    /* Transmit clock = DPLL output */
0139 #define RCRTxCP 0   /* Receive clock = RTxC pin */
0140 #define RCTRxCP 0x20    /* Receive clock = TRxC pin */
0141 #define RCBR    0x40    /* Receive clock = BR Generator output */
0142 #define RCDPLL  0x60    /* Receive clock = DPLL output */
0143 #define RTxCX   0x80    /* RTxC Xtal/No Xtal */
0144
0145 /* Write Register 12 (lower byte of baud rate generator time constant) */
0146
0147 /* Write Register 13 (upper byte of baud rate generator time constant) */
0148
0149 /* Write Register 14 (Misc control bits) */
0150 #define BRENABL 1   /* Baud rate generator enable */
0151 #define BRSRC   2   /* Baud rate generator source */
0152 #define DTRREQ  4   /* DTR/Request function */
0153 #define AUTOECHO 8  /* Auto Echo */
0154 #define LOOPBAK 0x10    /* Local loopback */
0155 #define SEARCH  0x20    /* Enter search mode */
0156 #define RMC 0x40    /* Reset missing clock */
0157 #define DISDPLL 0x60    /* Disable DPLL */
0158 #define SSBR    0x80    /* Set DPLL source = BR generator */
0159 #define SSRTxC  0xa0    /* Set DPLL source = RTxC */
0160 #define SFMM    0xc0    /* Set FM mode */
0161 #define SNRZI   0xe0    /* Set NRZI mode */
0162
0163 /* Write Register 15 (external/status interrupt control) */
0164 #define ZCIE    2   /* Zero count IE */
0165 #define DCDIE   8   /* DCD IE */
0166 #define SYNCIE  0x10    /* Sync/hunt IE */
0167 #define CTSIE   0x20    /* CTS IE */
0168 #define TxUIE   0x40    /* Tx Underrun/EOM IE */
0169 #define BRKIE   0x80    /* Break/Abort IE */
0170
0171
0172 /* Read Register 0 */
0173 #define Rx_CH_AV    0x1 /* Rx Character Available */
0174 #define ZCOUNT      0x2 /* Zero count */
0175 #define Tx_BUF_EMP  0x4 /* Tx Buffer empty */
0176 #define DCD     0x8 /* DCD */
0177 #define SYNC_HUNT   0x10    /* Sync/hunt */
0178 #define CTS     0x20    /* CTS */
0179 #define TxEOM       0x40    /* Tx underrun */
0180 #define BRK_ABRT    0x80    /* Break/Abort */
0181
0182 /* Read Register 1 */
0183 #define ALL_SNT     0x1 /* All sent */
0184 /* Residue Data for 8 Rx bits/char programmed */
0185 #define RES3        0x8 /* 0/3 */
0186 #define RES4        0x4 /* 0/4 */
0187 #define RES5        0xc /* 0/5 */
0188 #define RES6        0x2 /* 0/6 */
0189 #define RES7        0xa /* 0/7 */
0190 #define RES8        0x6 /* 0/8 */
0191 #define RES18       0xe /* 1/8 */
0192 #define RES28       0x0 /* 2/8 */
0193 /* Special Rx Condition Interrupts */
0194 #define PAR_ERR     0x10    /* Parity error */
0195 #define Rx_OVR      0x20    /* Rx Overrun Error */
0196 #define CRC_ERR     0x40    /* CRC/Framing Error */
0197 #define END_FR      0x80    /* End of Frame (SDLC) */
0198
0199 /* Read Register 2 (channel b only) - Interrupt vector */
0200
0201 /* Read Register 3 (interrupt pending register) ch a only */
0202 #define CHBEXT  0x1     /* Channel B Ext/Stat IP */
0203 #define CHBTxIP 0x2     /* Channel B Tx IP */
0204 #define CHBRxIP 0x4     /* Channel B Rx IP */
0205 #define CHAEXT  0x8     /* Channel A Ext/Stat IP */
0206 #define CHATxIP 0x10        /* Channel A Tx IP */
0207 #define CHARxIP 0x20        /* Channel A Rx IP */
0208
0209 /* Read Register 8 (receive data register) */
0210
0211 /* Read Register 10  (misc status bits) */
0212 #define ONLOOP  2       /* On loop */
0213 #define LOOPSEND 0x10       /* Loop sending */
0214 #define CLK2MIS 0x40        /* Two clocks missing */
0215 #define CLK1MIS 0x80        /* One clock missing */
0216
0217 /* Read Register 12 (lower byte of baud rate generator constant) */
0218
0219 /* Read Register 13 (upper byte of baud rate generator constant) */
0220
0221 /* Read Register 15 (value of WR 15) */
0222
0223 /* Z85C30/Z85230 Enhanced SCC register definitions */
0224
0225 /* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
0226 #define AUTOTXF 0x01        /* Auto Tx Flag */
0227 #define AUTOEOM 0x02        /* Auto EOM Latch Reset */
0228 #define AUTORTS 0x04        /* Auto RTS */
0229 #define TXDNRZI 0x08        /* TxD Pulled High in SDLC NRZI mode */
0230 #define RXFIFOH 0x08        /* Z85230: Int on RX FIFO half full */
0231 #define FASTDTR 0x10        /* Fast DTR/REQ Mode */
0232 #define CRCCBCR 0x20        /* CRC Check Bytes Completely Received */
0233 #define TXFIFOE 0x20        /* Z85230: Int on TX FIFO completely empty */
0234 #define EXTRDEN 0x40        /* Extended Read Enabled */
0235
0236 /* Write Register 15 (external/status interrupt control) */
0237 #define SHDLCE  1       /* SDLC/HDLC Enhancements Enable */
0238 #define FIFOE   4       /* FIFO Enable */
0239
0240 /* Read Register 6 (frame status FIFO) */
0241 #define BCLSB   0xff        /* LSB of 14 bits count */
0242
0243 /* Read Register 7 (frame status FIFO) */
0244 #define BCMSB   0x3f        /* MSB of 14 bits count */
0245 #define FDA 0x40        /* FIFO Data Available Status */
0246 #define FOS 0x80        /* FIFO Overflow Status */