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0028 #include <linux/crc-ccitt.h>
0029 #include <linux/module.h>
0030 #include <linux/kernel.h>
0031 #include <linux/init.h>
0032 #include <linux/sched.h>
0033 #include <linux/string.h>
0034 #include <linux/workqueue.h>
0035 #include <linux/fs.h>
0036 #include <linux/parport.h>
0037 #include <linux/if_arp.h>
0038 #include <linux/hdlcdrv.h>
0039 #include <linux/baycom.h>
0040 #include <linux/jiffies.h>
0041 #include <linux/random.h>
0042 #include <net/ax25.h>
0043 #include <linux/uaccess.h>
0044
0045
0046
0047 #define BAYCOM_DEBUG
0048 #define BAYCOM_MAGIC 19730510
0049
0050
0051
0052 static const char paranoia_str[] = KERN_ERR
0053 "baycom_epp: bad magic number for hdlcdrv_state struct in routine %s\n";
0054
0055 static const char bc_drvname[] = "baycom_epp";
0056 static const char bc_drvinfo[] = KERN_INFO "baycom_epp: (C) 1998-2000 Thomas Sailer, HB9JNX/AE4WA\n"
0057 "baycom_epp: version 0.7\n";
0058
0059
0060
0061 #define NR_PORTS 4
0062
0063 static struct net_device *baycom_device[NR_PORTS];
0064
0065
0066
0067
0068 #define EPP_DCDBIT 0x80
0069 #define EPP_PTTBIT 0x08
0070 #define EPP_NREF 0x01
0071 #define EPP_NRAEF 0x02
0072 #define EPP_NRHF 0x04
0073 #define EPP_NTHF 0x20
0074 #define EPP_NTAEF 0x10
0075 #define EPP_NTEF EPP_PTTBIT
0076
0077
0078 #define EPP_TX_FIFO_ENABLE 0x10
0079 #define EPP_RX_FIFO_ENABLE 0x08
0080 #define EPP_MODEM_ENABLE 0x20
0081 #define EPP_LEDS 0xC0
0082 #define EPP_IRQ_ENABLE 0x10
0083
0084
0085 #define LPTREG_ECONTROL 0x402
0086 #define LPTREG_CONFIGB 0x401
0087 #define LPTREG_CONFIGA 0x400
0088 #define LPTREG_EPPDATA 0x004
0089 #define LPTREG_EPPADDR 0x003
0090 #define LPTREG_CONTROL 0x002
0091 #define LPTREG_STATUS 0x001
0092 #define LPTREG_DATA 0x000
0093
0094
0095 #define LPTCTRL_PROGRAM 0x04
0096 #define LPTCTRL_WRITE 0x01
0097 #define LPTCTRL_ADDRSTB 0x08
0098 #define LPTCTRL_DATASTB 0x02
0099 #define LPTCTRL_INTEN 0x10
0100
0101
0102 #define LPTSTAT_SHIFT_NINTR 6
0103 #define LPTSTAT_WAIT 0x80
0104 #define LPTSTAT_NINTR (1<<LPTSTAT_SHIFT_NINTR)
0105 #define LPTSTAT_PE 0x20
0106 #define LPTSTAT_DONE 0x10
0107 #define LPTSTAT_NERROR 0x08
0108 #define LPTSTAT_EPPTIMEOUT 0x01
0109
0110
0111 #define LPTDATA_SHIFT_TDI 0
0112 #define LPTDATA_SHIFT_TMS 2
0113 #define LPTDATA_TDI (1<<LPTDATA_SHIFT_TDI)
0114 #define LPTDATA_TCK 0x02
0115 #define LPTDATA_TMS (1<<LPTDATA_SHIFT_TMS)
0116 #define LPTDATA_INITBIAS 0x80
0117
0118
0119
0120 #define EPP_DCDBIT 0x80
0121 #define EPP_PTTBIT 0x08
0122 #define EPP_RXEBIT 0x01
0123 #define EPP_RXAEBIT 0x02
0124 #define EPP_RXHFULL 0x04
0125
0126 #define EPP_NTHF 0x20
0127 #define EPP_NTAEF 0x10
0128 #define EPP_NTEF EPP_PTTBIT
0129
0130 #define EPP_TX_FIFO_ENABLE 0x10
0131 #define EPP_RX_FIFO_ENABLE 0x08
0132 #define EPP_MODEM_ENABLE 0x20
0133 #define EPP_LEDS 0xC0
0134 #define EPP_IRQ_ENABLE 0x10
0135
0136
0137 #define XC4K_IRLENGTH 3
0138 #define XC4K_EXTEST 0
0139 #define XC4K_PRELOAD 1
0140 #define XC4K_CONFIGURE 5
0141 #define XC4K_BYPASS 7
0142
0143 #define EPP_CONVENTIONAL 0
0144 #define EPP_FPGA 1
0145 #define EPP_FPGAEXTSTATUS 2
0146
0147 #define TXBUFFER_SIZE ((HDLCDRV_MAXFLEN*6/5)+8)
0148
0149
0150
0151
0152
0153
0154 struct baycom_state {
0155 int magic;
0156
0157 struct pardevice *pdev;
0158 struct net_device *dev;
0159 unsigned int work_running;
0160 struct delayed_work run_work;
0161 unsigned int modem;
0162 unsigned int bitrate;
0163 unsigned char stat;
0164
0165 struct {
0166 unsigned int intclk;
0167 unsigned int fclk;
0168 unsigned int bps;
0169 unsigned int extmodem;
0170 unsigned int loopback;
0171 } cfg;
0172
0173 struct hdlcdrv_channel_params ch_params;
0174
0175 struct {
0176 unsigned int bitbuf, bitstream, numbits, state;
0177 unsigned char *bufptr;
0178 int bufcnt;
0179 unsigned char buf[TXBUFFER_SIZE];
0180 } hdlcrx;
0181
0182 struct {
0183 int calibrate;
0184 int slotcnt;
0185 int flags;
0186 enum { tx_idle = 0, tx_keyup, tx_data, tx_tail } state;
0187 unsigned char *bufptr;
0188 int bufcnt;
0189 unsigned char buf[TXBUFFER_SIZE];
0190 } hdlctx;
0191
0192 unsigned int ptt_keyed;
0193 struct sk_buff *skb;
0194
0195 #ifdef BAYCOM_DEBUG
0196 struct debug_vals {
0197 unsigned long last_jiffies;
0198 unsigned cur_intcnt;
0199 unsigned last_intcnt;
0200 int cur_pllcorr;
0201 int last_pllcorr;
0202 unsigned int mod_cycles;
0203 unsigned int demod_cycles;
0204 } debug_vals;
0205 #endif
0206 };
0207
0208
0209
0210 #define KISS_VERBOSE
0211
0212
0213
0214 #define PARAM_TXDELAY 1
0215 #define PARAM_PERSIST 2
0216 #define PARAM_SLOTTIME 3
0217 #define PARAM_TXTAIL 4
0218 #define PARAM_FULLDUP 5
0219 #define PARAM_HARDWARE 6
0220 #define PARAM_RETURN 255
0221
0222
0223
0224
0225
0226
0227
0228
0229
0230
0231 #if 0
0232 static inline void append_crc_ccitt(unsigned char *buffer, int len)
0233 {
0234 unsigned int crc = 0xffff;
0235
0236 for (;len>0;len--)
0237 crc = (crc >> 8) ^ crc_ccitt_table[(crc ^ *buffer++) & 0xff];
0238 crc ^= 0xffff;
0239 *buffer++ = crc;
0240 *buffer++ = crc >> 8;
0241 }
0242 #endif
0243
0244
0245
0246 static inline int check_crc_ccitt(const unsigned char *buf, int cnt)
0247 {
0248 return (crc_ccitt(0xffff, buf, cnt) & 0xffff) == 0xf0b8;
0249 }
0250
0251
0252
0253 static inline int calc_crc_ccitt(const unsigned char *buf, int cnt)
0254 {
0255 return (crc_ccitt(0xffff, buf, cnt) ^ 0xffff) & 0xffff;
0256 }
0257
0258
0259
0260 #define tenms_to_flags(bc,tenms) ((tenms * bc->bitrate) / 800)
0261
0262
0263
0264 static inline void baycom_int_freq(struct baycom_state *bc)
0265 {
0266 #ifdef BAYCOM_DEBUG
0267 unsigned long cur_jiffies = jiffies;
0268
0269
0270
0271 bc->debug_vals.cur_intcnt++;
0272 if (time_after_eq(cur_jiffies, bc->debug_vals.last_jiffies + HZ)) {
0273 bc->debug_vals.last_jiffies = cur_jiffies;
0274 bc->debug_vals.last_intcnt = bc->debug_vals.cur_intcnt;
0275 bc->debug_vals.cur_intcnt = 0;
0276 bc->debug_vals.last_pllcorr = bc->debug_vals.cur_pllcorr;
0277 bc->debug_vals.cur_pllcorr = 0;
0278 }
0279 #endif
0280 }
0281
0282
0283
0284
0285
0286
0287 static char const eppconfig_path[] = "/usr/sbin/eppfpga";
0288
0289 static char *envp[] = { "HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL };
0290
0291
0292 static int eppconfig(struct baycom_state *bc)
0293 {
0294 char modearg[256];
0295 char portarg[16];
0296 char *argv[] = {
0297 (char *)eppconfig_path,
0298 "-s",
0299 "-p", portarg,
0300 "-m", modearg,
0301 NULL };
0302
0303
0304 sprintf(modearg, "%sclk,%smodem,fclk=%d,bps=%d,divider=%d%s,extstat",
0305 bc->cfg.intclk ? "int" : "ext",
0306 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
0307 (bc->cfg.fclk + 8 * bc->cfg.bps) / (16 * bc->cfg.bps),
0308 bc->cfg.loopback ? ",loopback" : "");
0309 sprintf(portarg, "%ld", bc->pdev->port->base);
0310 printk(KERN_DEBUG "%s: %s -s -p %s -m %s\n", bc_drvname, eppconfig_path, portarg, modearg);
0311
0312 return call_usermodehelper(eppconfig_path, argv, envp, UMH_WAIT_PROC);
0313 }
0314
0315
0316
0317 static inline void do_kiss_params(struct baycom_state *bc,
0318 unsigned char *data, unsigned long len)
0319 {
0320
0321 #ifdef KISS_VERBOSE
0322 #define PKP(a,b) printk(KERN_INFO "baycomm_epp: channel params: " a "\n", b)
0323 #else
0324 #define PKP(a,b)
0325 #endif
0326
0327 if (len < 2)
0328 return;
0329 switch(data[0]) {
0330 case PARAM_TXDELAY:
0331 bc->ch_params.tx_delay = data[1];
0332 PKP("TX delay = %ums", 10 * bc->ch_params.tx_delay);
0333 break;
0334 case PARAM_PERSIST:
0335 bc->ch_params.ppersist = data[1];
0336 PKP("p persistence = %u", bc->ch_params.ppersist);
0337 break;
0338 case PARAM_SLOTTIME:
0339 bc->ch_params.slottime = data[1];
0340 PKP("slot time = %ums", bc->ch_params.slottime);
0341 break;
0342 case PARAM_TXTAIL:
0343 bc->ch_params.tx_tail = data[1];
0344 PKP("TX tail = %ums", bc->ch_params.tx_tail);
0345 break;
0346 case PARAM_FULLDUP:
0347 bc->ch_params.fulldup = !!data[1];
0348 PKP("%s duplex", bc->ch_params.fulldup ? "full" : "half");
0349 break;
0350 default:
0351 break;
0352 }
0353 #undef PKP
0354 }
0355
0356
0357
0358 static void encode_hdlc(struct baycom_state *bc)
0359 {
0360 struct sk_buff *skb;
0361 unsigned char *wp, *bp;
0362 int pkt_len;
0363 unsigned bitstream, notbitstream, bitbuf, numbit, crc;
0364 unsigned char crcarr[2];
0365 int j;
0366
0367 if (bc->hdlctx.bufcnt > 0)
0368 return;
0369 skb = bc->skb;
0370 if (!skb)
0371 return;
0372 bc->skb = NULL;
0373 pkt_len = skb->len-1;
0374 wp = bc->hdlctx.buf;
0375 bp = skb->data+1;
0376 crc = calc_crc_ccitt(bp, pkt_len);
0377 crcarr[0] = crc;
0378 crcarr[1] = crc >> 8;
0379 *wp++ = 0x7e;
0380 bitstream = bitbuf = numbit = 0;
0381 while (pkt_len > -2) {
0382 bitstream >>= 8;
0383 bitstream |= ((unsigned int)*bp) << 8;
0384 bitbuf |= ((unsigned int)*bp) << numbit;
0385 notbitstream = ~bitstream;
0386 bp++;
0387 pkt_len--;
0388 if (!pkt_len)
0389 bp = crcarr;
0390 for (j = 0; j < 8; j++)
0391 if (unlikely(!(notbitstream & (0x1f0 << j)))) {
0392 bitstream &= ~(0x100 << j);
0393 bitbuf = (bitbuf & (((2 << j) << numbit) - 1)) |
0394 ((bitbuf & ~(((2 << j) << numbit) - 1)) << 1);
0395 numbit++;
0396 notbitstream = ~bitstream;
0397 }
0398 numbit += 8;
0399 while (numbit >= 8) {
0400 *wp++ = bitbuf;
0401 bitbuf >>= 8;
0402 numbit -= 8;
0403 }
0404 }
0405 bitbuf |= 0x7e7e << numbit;
0406 numbit += 16;
0407 while (numbit >= 8) {
0408 *wp++ = bitbuf;
0409 bitbuf >>= 8;
0410 numbit -= 8;
0411 }
0412 bc->hdlctx.bufptr = bc->hdlctx.buf;
0413 bc->hdlctx.bufcnt = wp - bc->hdlctx.buf;
0414 dev_kfree_skb(skb);
0415 bc->dev->stats.tx_packets++;
0416 }
0417
0418
0419
0420 static int transmit(struct baycom_state *bc, int cnt, unsigned char stat)
0421 {
0422 struct parport *pp = bc->pdev->port;
0423 unsigned char tmp[128];
0424 int i, j;
0425
0426 if (bc->hdlctx.state == tx_tail && !(stat & EPP_PTTBIT))
0427 bc->hdlctx.state = tx_idle;
0428 if (bc->hdlctx.state == tx_idle && bc->hdlctx.calibrate <= 0) {
0429 if (bc->hdlctx.bufcnt <= 0)
0430 encode_hdlc(bc);
0431 if (bc->hdlctx.bufcnt <= 0)
0432 return 0;
0433 if (!bc->ch_params.fulldup) {
0434 if (!(stat & EPP_DCDBIT)) {
0435 bc->hdlctx.slotcnt = bc->ch_params.slottime;
0436 return 0;
0437 }
0438 if ((--bc->hdlctx.slotcnt) > 0)
0439 return 0;
0440 bc->hdlctx.slotcnt = bc->ch_params.slottime;
0441 if ((prandom_u32() % 256) > bc->ch_params.ppersist)
0442 return 0;
0443 }
0444 }
0445 if (bc->hdlctx.state == tx_idle && bc->hdlctx.bufcnt > 0) {
0446 bc->hdlctx.state = tx_keyup;
0447 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_delay);
0448 bc->ptt_keyed++;
0449 }
0450 while (cnt > 0) {
0451 switch (bc->hdlctx.state) {
0452 case tx_keyup:
0453 i = min_t(int, cnt, bc->hdlctx.flags);
0454 cnt -= i;
0455 bc->hdlctx.flags -= i;
0456 if (bc->hdlctx.flags <= 0)
0457 bc->hdlctx.state = tx_data;
0458 memset(tmp, 0x7e, sizeof(tmp));
0459 while (i > 0) {
0460 j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
0461 if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
0462 return -1;
0463 i -= j;
0464 }
0465 break;
0466
0467 case tx_data:
0468 if (bc->hdlctx.bufcnt <= 0) {
0469 encode_hdlc(bc);
0470 if (bc->hdlctx.bufcnt <= 0) {
0471 bc->hdlctx.state = tx_tail;
0472 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_tail);
0473 break;
0474 }
0475 }
0476 i = min_t(int, cnt, bc->hdlctx.bufcnt);
0477 bc->hdlctx.bufcnt -= i;
0478 cnt -= i;
0479 if (i != pp->ops->epp_write_data(pp, bc->hdlctx.bufptr, i, 0))
0480 return -1;
0481 bc->hdlctx.bufptr += i;
0482 break;
0483
0484 case tx_tail:
0485 encode_hdlc(bc);
0486 if (bc->hdlctx.bufcnt > 0) {
0487 bc->hdlctx.state = tx_data;
0488 break;
0489 }
0490 i = min_t(int, cnt, bc->hdlctx.flags);
0491 if (i) {
0492 cnt -= i;
0493 bc->hdlctx.flags -= i;
0494 memset(tmp, 0x7e, sizeof(tmp));
0495 while (i > 0) {
0496 j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
0497 if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
0498 return -1;
0499 i -= j;
0500 }
0501 break;
0502 }
0503 fallthrough;
0504
0505 default:
0506 if (bc->hdlctx.calibrate <= 0)
0507 return 0;
0508 i = min_t(int, cnt, bc->hdlctx.calibrate);
0509 cnt -= i;
0510 bc->hdlctx.calibrate -= i;
0511 memset(tmp, 0, sizeof(tmp));
0512 while (i > 0) {
0513 j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
0514 if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
0515 return -1;
0516 i -= j;
0517 }
0518 break;
0519 }
0520 }
0521 return 0;
0522 }
0523
0524
0525
0526 static void do_rxpacket(struct net_device *dev)
0527 {
0528 struct baycom_state *bc = netdev_priv(dev);
0529 struct sk_buff *skb;
0530 unsigned char *cp;
0531 unsigned pktlen;
0532
0533 if (bc->hdlcrx.bufcnt < 4)
0534 return;
0535 if (!check_crc_ccitt(bc->hdlcrx.buf, bc->hdlcrx.bufcnt))
0536 return;
0537 pktlen = bc->hdlcrx.bufcnt-2+1;
0538 if (!(skb = dev_alloc_skb(pktlen))) {
0539 printk("%s: memory squeeze, dropping packet\n", dev->name);
0540 dev->stats.rx_dropped++;
0541 return;
0542 }
0543 cp = skb_put(skb, pktlen);
0544 *cp++ = 0;
0545 memcpy(cp, bc->hdlcrx.buf, pktlen - 1);
0546 skb->protocol = ax25_type_trans(skb, dev);
0547 netif_rx(skb);
0548 dev->stats.rx_packets++;
0549 }
0550
0551 static int receive(struct net_device *dev, int cnt)
0552 {
0553 struct baycom_state *bc = netdev_priv(dev);
0554 struct parport *pp = bc->pdev->port;
0555 unsigned int bitbuf, notbitstream, bitstream, numbits, state;
0556 unsigned char tmp[128];
0557 unsigned char *cp;
0558 int cnt2, ret = 0;
0559 int j;
0560
0561 numbits = bc->hdlcrx.numbits;
0562 state = bc->hdlcrx.state;
0563 bitstream = bc->hdlcrx.bitstream;
0564 bitbuf = bc->hdlcrx.bitbuf;
0565 while (cnt > 0) {
0566 cnt2 = (cnt > sizeof(tmp)) ? sizeof(tmp) : cnt;
0567 cnt -= cnt2;
0568 if (cnt2 != pp->ops->epp_read_data(pp, tmp, cnt2, 0)) {
0569 ret = -1;
0570 break;
0571 }
0572 cp = tmp;
0573 for (; cnt2 > 0; cnt2--, cp++) {
0574 bitstream >>= 8;
0575 bitstream |= (*cp) << 8;
0576 bitbuf >>= 8;
0577 bitbuf |= (*cp) << 8;
0578 numbits += 8;
0579 notbitstream = ~bitstream;
0580 for (j = 0; j < 8; j++) {
0581
0582
0583 if (unlikely(!(notbitstream & (0x0fc << j)))) {
0584
0585
0586 if (!(notbitstream & (0x1fc << j)))
0587 state = 0;
0588
0589
0590 else if ((bitstream & (0x1fe << j)) == (0x0fc << j)) {
0591 if (state)
0592 do_rxpacket(dev);
0593 bc->hdlcrx.bufcnt = 0;
0594 bc->hdlcrx.bufptr = bc->hdlcrx.buf;
0595 state = 1;
0596 numbits = 7-j;
0597 }
0598 }
0599
0600
0601 else if (unlikely((bitstream & (0x1f8 << j)) == (0xf8 << j))) {
0602 numbits--;
0603 bitbuf = (bitbuf & ((~0xff) << j)) | ((bitbuf & ~((~0xff) << j)) << 1);
0604 }
0605 }
0606 while (state && numbits >= 8) {
0607 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) {
0608 state = 0;
0609 } else {
0610 *(bc->hdlcrx.bufptr)++ = bitbuf >> (16-numbits);
0611 bc->hdlcrx.bufcnt++;
0612 numbits -= 8;
0613 }
0614 }
0615 }
0616 }
0617 bc->hdlcrx.numbits = numbits;
0618 bc->hdlcrx.state = state;
0619 bc->hdlcrx.bitstream = bitstream;
0620 bc->hdlcrx.bitbuf = bitbuf;
0621 return ret;
0622 }
0623
0624
0625
0626 #if defined(__i386__) && !defined(CONFIG_UML)
0627 #include <asm/msr.h>
0628 #define GETTICK(x) \
0629 ({ \
0630 if (boot_cpu_has(X86_FEATURE_TSC)) \
0631 x = (unsigned int)rdtsc(); \
0632 })
0633 #else
0634 #define GETTICK(x)
0635 #endif
0636
0637 static void epp_bh(struct work_struct *work)
0638 {
0639 struct net_device *dev;
0640 struct baycom_state *bc;
0641 struct parport *pp;
0642 unsigned char stat;
0643 unsigned char tmp[2];
0644 unsigned int time1 = 0, time2 = 0, time3 = 0;
0645 int cnt, cnt2;
0646
0647 bc = container_of(work, struct baycom_state, run_work.work);
0648 dev = bc->dev;
0649 if (!bc->work_running)
0650 return;
0651 baycom_int_freq(bc);
0652 pp = bc->pdev->port;
0653
0654 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
0655 goto epptimeout;
0656 bc->stat = stat;
0657 bc->debug_vals.last_pllcorr = stat;
0658 GETTICK(time1);
0659 if (bc->modem == EPP_FPGAEXTSTATUS) {
0660
0661 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE|1;
0662 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
0663 goto epptimeout;
0664 if (pp->ops->epp_read_addr(pp, tmp, 2, 0) != 2)
0665 goto epptimeout;
0666 cnt = tmp[0] | (tmp[1] << 8);
0667 cnt &= 0x7fff;
0668
0669 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE|2;
0670 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
0671 goto epptimeout;
0672 if (pp->ops->epp_read_addr(pp, tmp, 2, 0) != 2)
0673 goto epptimeout;
0674 cnt2 = tmp[0] | (tmp[1] << 8);
0675 cnt2 = 16384 - (cnt2 & 0x7fff);
0676
0677 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
0678 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
0679 goto epptimeout;
0680 if (transmit(bc, cnt2, stat))
0681 goto epptimeout;
0682 GETTICK(time2);
0683 if (receive(dev, cnt))
0684 goto epptimeout;
0685 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
0686 goto epptimeout;
0687 bc->stat = stat;
0688 } else {
0689
0690 switch (stat & (EPP_NTAEF|EPP_NTHF)) {
0691 case EPP_NTHF:
0692 cnt = 2048 - 256;
0693 break;
0694
0695 case EPP_NTAEF:
0696 cnt = 2048 - 1793;
0697 break;
0698
0699 case 0:
0700 cnt = 0;
0701 break;
0702
0703 default:
0704 cnt = 2048 - 1025;
0705 break;
0706 }
0707 if (transmit(bc, cnt, stat))
0708 goto epptimeout;
0709 GETTICK(time2);
0710
0711 while ((stat & (EPP_NRAEF|EPP_NRHF)) != EPP_NRHF) {
0712 switch (stat & (EPP_NRAEF|EPP_NRHF)) {
0713 case EPP_NRAEF:
0714 cnt = 1025;
0715 break;
0716
0717 case 0:
0718 cnt = 1793;
0719 break;
0720
0721 default:
0722 cnt = 256;
0723 break;
0724 }
0725 if (receive(dev, cnt))
0726 goto epptimeout;
0727 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
0728 goto epptimeout;
0729 }
0730 cnt = 0;
0731 if (bc->bitrate < 50000)
0732 cnt = 256;
0733 else if (bc->bitrate < 100000)
0734 cnt = 128;
0735 while (cnt > 0 && stat & EPP_NREF) {
0736 if (receive(dev, 1))
0737 goto epptimeout;
0738 cnt--;
0739 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
0740 goto epptimeout;
0741 }
0742 }
0743 GETTICK(time3);
0744 #ifdef BAYCOM_DEBUG
0745 bc->debug_vals.mod_cycles = time2 - time1;
0746 bc->debug_vals.demod_cycles = time3 - time2;
0747 #endif
0748 schedule_delayed_work(&bc->run_work, 1);
0749 if (!bc->skb)
0750 netif_wake_queue(dev);
0751 return;
0752 epptimeout:
0753 printk(KERN_ERR "%s: EPP timeout!\n", bc_drvname);
0754 }
0755
0756
0757
0758
0759
0760
0761 static int baycom_send_packet(struct sk_buff *skb, struct net_device *dev)
0762 {
0763 struct baycom_state *bc = netdev_priv(dev);
0764
0765 if (skb->protocol == htons(ETH_P_IP))
0766 return ax25_ip_xmit(skb);
0767
0768 if (skb->data[0] != 0) {
0769 do_kiss_params(bc, skb->data, skb->len);
0770 dev_kfree_skb(skb);
0771 return NETDEV_TX_OK;
0772 }
0773 if (bc->skb) {
0774 dev_kfree_skb(skb);
0775 return NETDEV_TX_OK;
0776 }
0777
0778 if (skb->len >= HDLCDRV_MAXFLEN+1 || skb->len < 3) {
0779 dev_kfree_skb(skb);
0780 return NETDEV_TX_OK;
0781 }
0782 netif_stop_queue(dev);
0783 bc->skb = skb;
0784 return NETDEV_TX_OK;
0785 }
0786
0787
0788
0789 static int baycom_set_mac_address(struct net_device *dev, void *addr)
0790 {
0791 struct sockaddr *sa = (struct sockaddr *)addr;
0792
0793
0794 dev_addr_set(dev, sa->sa_data);
0795 return 0;
0796 }
0797
0798
0799
0800 static void epp_wakeup(void *handle)
0801 {
0802 struct net_device *dev = (struct net_device *)handle;
0803 struct baycom_state *bc = netdev_priv(dev);
0804
0805 printk(KERN_DEBUG "baycom_epp: %s: why am I being woken up?\n", dev->name);
0806 if (!parport_claim(bc->pdev))
0807 printk(KERN_DEBUG "baycom_epp: %s: I'm broken.\n", dev->name);
0808 }
0809
0810
0811
0812
0813
0814
0815
0816
0817
0818
0819
0820
0821 static int epp_open(struct net_device *dev)
0822 {
0823 struct baycom_state *bc = netdev_priv(dev);
0824 struct parport *pp = parport_find_base(dev->base_addr);
0825 unsigned int i, j;
0826 unsigned char tmp[128];
0827 unsigned char stat;
0828 unsigned long tstart;
0829 struct pardev_cb par_cb;
0830
0831 if (!pp) {
0832 printk(KERN_ERR "%s: parport at 0x%lx unknown\n", bc_drvname, dev->base_addr);
0833 return -ENXIO;
0834 }
0835 #if 0
0836 if (pp->irq < 0) {
0837 printk(KERN_ERR "%s: parport at 0x%lx has no irq\n", bc_drvname, pp->base);
0838 parport_put_port(pp);
0839 return -ENXIO;
0840 }
0841 #endif
0842 if ((~pp->modes) & (PARPORT_MODE_TRISTATE | PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT)) {
0843 printk(KERN_ERR "%s: parport at 0x%lx cannot be used\n",
0844 bc_drvname, pp->base);
0845 parport_put_port(pp);
0846 return -EIO;
0847 }
0848 memset(&bc->modem, 0, sizeof(bc->modem));
0849 memset(&par_cb, 0, sizeof(par_cb));
0850 par_cb.wakeup = epp_wakeup;
0851 par_cb.private = (void *)dev;
0852 par_cb.flags = PARPORT_DEV_EXCL;
0853 for (i = 0; i < NR_PORTS; i++)
0854 if (baycom_device[i] == dev)
0855 break;
0856
0857 if (i == NR_PORTS) {
0858 pr_err("%s: no device found\n", bc_drvname);
0859 parport_put_port(pp);
0860 return -ENODEV;
0861 }
0862
0863 bc->pdev = parport_register_dev_model(pp, dev->name, &par_cb, i);
0864 parport_put_port(pp);
0865 if (!bc->pdev) {
0866 printk(KERN_ERR "%s: cannot register parport at 0x%lx\n", bc_drvname, pp->base);
0867 return -ENXIO;
0868 }
0869 if (parport_claim(bc->pdev)) {
0870 printk(KERN_ERR "%s: parport at 0x%lx busy\n", bc_drvname, pp->base);
0871 parport_unregister_device(bc->pdev);
0872 return -EBUSY;
0873 }
0874 dev->irq = 0;
0875 INIT_DELAYED_WORK(&bc->run_work, epp_bh);
0876 bc->work_running = 1;
0877 bc->modem = EPP_CONVENTIONAL;
0878 if (eppconfig(bc))
0879 printk(KERN_INFO "%s: no FPGA detected, assuming conventional EPP modem\n", bc_drvname);
0880 else
0881 bc->modem = EPP_FPGAEXTSTATUS;
0882 parport_write_control(pp, LPTCTRL_PROGRAM);
0883
0884 tmp[0] = 0;
0885 tmp[1] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
0886 if (pp->ops->epp_write_addr(pp, tmp, 2, 0) != 2)
0887 goto epptimeout;
0888
0889 tstart = jiffies;
0890 i = 0;
0891 while (time_before(jiffies, tstart + HZ/3)) {
0892 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
0893 goto epptimeout;
0894 if ((stat & (EPP_NRAEF|EPP_NRHF)) == EPP_NRHF) {
0895 schedule();
0896 continue;
0897 }
0898 if (pp->ops->epp_read_data(pp, tmp, 128, 0) != 128)
0899 goto epptimeout;
0900 if (pp->ops->epp_read_data(pp, tmp, 128, 0) != 128)
0901 goto epptimeout;
0902 i += 256;
0903 }
0904 for (j = 0; j < 256; j++) {
0905 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
0906 goto epptimeout;
0907 if (!(stat & EPP_NREF))
0908 break;
0909 if (pp->ops->epp_read_data(pp, tmp, 1, 0) != 1)
0910 goto epptimeout;
0911 i++;
0912 }
0913 tstart = jiffies - tstart;
0914 bc->bitrate = i * (8 * HZ) / tstart;
0915 j = 1;
0916 i = bc->bitrate >> 3;
0917 while (j < 7 && i > 150) {
0918 j++;
0919 i >>= 1;
0920 }
0921 printk(KERN_INFO "%s: autoprobed bitrate: %d int divider: %d int rate: %d\n",
0922 bc_drvname, bc->bitrate, j, bc->bitrate >> (j+2));
0923 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
0924 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
0925 goto epptimeout;
0926
0927
0928
0929 bc->hdlcrx.state = 0;
0930 bc->hdlcrx.numbits = 0;
0931 bc->hdlctx.state = tx_idle;
0932 bc->hdlctx.bufcnt = 0;
0933 bc->hdlctx.slotcnt = bc->ch_params.slottime;
0934 bc->hdlctx.calibrate = 0;
0935
0936 schedule_delayed_work(&bc->run_work, 1);
0937 netif_start_queue(dev);
0938 return 0;
0939
0940 epptimeout:
0941 printk(KERN_ERR "%s: epp timeout during bitrate probe\n", bc_drvname);
0942 parport_write_control(pp, 0);
0943 parport_release(bc->pdev);
0944 parport_unregister_device(bc->pdev);
0945 return -EIO;
0946 }
0947
0948
0949
0950 static int epp_close(struct net_device *dev)
0951 {
0952 struct baycom_state *bc = netdev_priv(dev);
0953 struct parport *pp = bc->pdev->port;
0954 unsigned char tmp[1];
0955
0956 bc->work_running = 0;
0957 cancel_delayed_work_sync(&bc->run_work);
0958 bc->stat = EPP_DCDBIT;
0959 tmp[0] = 0;
0960 pp->ops->epp_write_addr(pp, tmp, 1, 0);
0961 parport_write_control(pp, 0);
0962 parport_release(bc->pdev);
0963 parport_unregister_device(bc->pdev);
0964 dev_kfree_skb(bc->skb);
0965 bc->skb = NULL;
0966 printk(KERN_INFO "%s: close epp at iobase 0x%lx irq %u\n",
0967 bc_drvname, dev->base_addr, dev->irq);
0968 return 0;
0969 }
0970
0971
0972
0973 static int baycom_setmode(struct baycom_state *bc, const char *modestr)
0974 {
0975 const char *cp;
0976
0977 if (strstr(modestr,"intclk"))
0978 bc->cfg.intclk = 1;
0979 if (strstr(modestr,"extclk"))
0980 bc->cfg.intclk = 0;
0981 if (strstr(modestr,"intmodem"))
0982 bc->cfg.extmodem = 0;
0983 if (strstr(modestr,"extmodem"))
0984 bc->cfg.extmodem = 1;
0985 if (strstr(modestr,"loopback"))
0986 bc->cfg.loopback = 1;
0987 if (strstr(modestr, "noloopback"))
0988 bc->cfg.loopback = 0;
0989 if ((cp = strstr(modestr,"fclk="))) {
0990 bc->cfg.fclk = simple_strtoul(cp+5, NULL, 0);
0991 if (bc->cfg.fclk < 1000000)
0992 bc->cfg.fclk = 1000000;
0993 if (bc->cfg.fclk > 25000000)
0994 bc->cfg.fclk = 25000000;
0995 }
0996 if ((cp = strstr(modestr,"bps="))) {
0997 bc->cfg.bps = simple_strtoul(cp+4, NULL, 0);
0998 if (bc->cfg.bps < 1000)
0999 bc->cfg.bps = 1000;
1000 if (bc->cfg.bps > 1500000)
1001 bc->cfg.bps = 1500000;
1002 }
1003 return 0;
1004 }
1005
1006
1007
1008 static int baycom_siocdevprivate(struct net_device *dev, struct ifreq *ifr,
1009 void __user *data, int cmd)
1010 {
1011 struct baycom_state *bc = netdev_priv(dev);
1012 struct hdlcdrv_ioctl hi;
1013
1014 if (cmd != SIOCDEVPRIVATE)
1015 return -ENOIOCTLCMD;
1016
1017 if (copy_from_user(&hi, data, sizeof(hi)))
1018 return -EFAULT;
1019 switch (hi.cmd) {
1020 default:
1021 return -ENOIOCTLCMD;
1022
1023 case HDLCDRVCTL_GETCHANNELPAR:
1024 hi.data.cp.tx_delay = bc->ch_params.tx_delay;
1025 hi.data.cp.tx_tail = bc->ch_params.tx_tail;
1026 hi.data.cp.slottime = bc->ch_params.slottime;
1027 hi.data.cp.ppersist = bc->ch_params.ppersist;
1028 hi.data.cp.fulldup = bc->ch_params.fulldup;
1029 break;
1030
1031 case HDLCDRVCTL_SETCHANNELPAR:
1032 if (!capable(CAP_NET_ADMIN))
1033 return -EACCES;
1034 bc->ch_params.tx_delay = hi.data.cp.tx_delay;
1035 bc->ch_params.tx_tail = hi.data.cp.tx_tail;
1036 bc->ch_params.slottime = hi.data.cp.slottime;
1037 bc->ch_params.ppersist = hi.data.cp.ppersist;
1038 bc->ch_params.fulldup = hi.data.cp.fulldup;
1039 bc->hdlctx.slotcnt = 1;
1040 return 0;
1041
1042 case HDLCDRVCTL_GETMODEMPAR:
1043 hi.data.mp.iobase = dev->base_addr;
1044 hi.data.mp.irq = dev->irq;
1045 hi.data.mp.dma = dev->dma;
1046 hi.data.mp.dma2 = 0;
1047 hi.data.mp.seriobase = 0;
1048 hi.data.mp.pariobase = 0;
1049 hi.data.mp.midiiobase = 0;
1050 break;
1051
1052 case HDLCDRVCTL_SETMODEMPAR:
1053 if ((!capable(CAP_SYS_RAWIO)) || netif_running(dev))
1054 return -EACCES;
1055 dev->base_addr = hi.data.mp.iobase;
1056 dev->irq = 0;
1057 dev->dma = 0;
1058 return 0;
1059
1060 case HDLCDRVCTL_GETSTAT:
1061 hi.data.cs.ptt = !!(bc->stat & EPP_PTTBIT);
1062 hi.data.cs.dcd = !(bc->stat & EPP_DCDBIT);
1063 hi.data.cs.ptt_keyed = bc->ptt_keyed;
1064 hi.data.cs.tx_packets = dev->stats.tx_packets;
1065 hi.data.cs.tx_errors = dev->stats.tx_errors;
1066 hi.data.cs.rx_packets = dev->stats.rx_packets;
1067 hi.data.cs.rx_errors = dev->stats.rx_errors;
1068 break;
1069
1070 case HDLCDRVCTL_OLDGETSTAT:
1071 hi.data.ocs.ptt = !!(bc->stat & EPP_PTTBIT);
1072 hi.data.ocs.dcd = !(bc->stat & EPP_DCDBIT);
1073 hi.data.ocs.ptt_keyed = bc->ptt_keyed;
1074 break;
1075
1076 case HDLCDRVCTL_CALIBRATE:
1077 if (!capable(CAP_SYS_RAWIO))
1078 return -EACCES;
1079 bc->hdlctx.calibrate = hi.data.calibrate * bc->bitrate / 8;
1080 return 0;
1081
1082 case HDLCDRVCTL_DRIVERNAME:
1083 strncpy(hi.data.drivername, "baycom_epp", sizeof(hi.data.drivername));
1084 break;
1085
1086 case HDLCDRVCTL_GETMODE:
1087 sprintf(hi.data.modename, "%sclk,%smodem,fclk=%d,bps=%d%s",
1088 bc->cfg.intclk ? "int" : "ext",
1089 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
1090 bc->cfg.loopback ? ",loopback" : "");
1091 break;
1092
1093 case HDLCDRVCTL_SETMODE:
1094 if (!capable(CAP_NET_ADMIN) || netif_running(dev))
1095 return -EACCES;
1096 hi.data.modename[sizeof(hi.data.modename)-1] = '\0';
1097 return baycom_setmode(bc, hi.data.modename);
1098
1099 case HDLCDRVCTL_MODELIST:
1100 strncpy(hi.data.modename, "intclk,extclk,intmodem,extmodem,divider=x",
1101 sizeof(hi.data.modename));
1102 break;
1103
1104 case HDLCDRVCTL_MODEMPARMASK:
1105 return HDLCDRV_PARMASK_IOBASE;
1106
1107 }
1108 if (copy_to_user(data, &hi, sizeof(hi)))
1109 return -EFAULT;
1110 return 0;
1111 }
1112
1113
1114
1115 static const struct net_device_ops baycom_netdev_ops = {
1116 .ndo_open = epp_open,
1117 .ndo_stop = epp_close,
1118 .ndo_siocdevprivate = baycom_siocdevprivate,
1119 .ndo_start_xmit = baycom_send_packet,
1120 .ndo_set_mac_address = baycom_set_mac_address,
1121 };
1122
1123
1124
1125
1126
1127
1128
1129
1130 static void baycom_probe(struct net_device *dev)
1131 {
1132 const struct hdlcdrv_channel_params dflt_ch_params = {
1133 20, 2, 10, 40, 0
1134 };
1135 struct baycom_state *bc;
1136
1137
1138
1139
1140 bc = netdev_priv(dev);
1141
1142
1143
1144 bc->ch_params = dflt_ch_params;
1145 bc->ptt_keyed = 0;
1146
1147
1148
1149
1150
1151
1152 bc->skb = NULL;
1153
1154 dev->netdev_ops = &baycom_netdev_ops;
1155 dev->header_ops = &ax25_header_ops;
1156
1157 dev->type = ARPHRD_AX25;
1158 dev->hard_header_len = AX25_MAX_HEADER_LEN + AX25_BPQ_HEADER_LEN;
1159 dev->mtu = AX25_DEF_PACLEN;
1160 dev->addr_len = AX25_ADDR_LEN;
1161 memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
1162 dev_addr_set(dev, (u8 *)&null_ax25_address);
1163 dev->tx_queue_len = 16;
1164
1165
1166 dev->flags = 0;
1167 }
1168
1169
1170
1171
1172
1173
1174 static char *mode[NR_PORTS] = { "", };
1175 static int iobase[NR_PORTS] = { 0x378, };
1176
1177 module_param_array(mode, charp, NULL, 0);
1178 MODULE_PARM_DESC(mode, "baycom operating mode");
1179 module_param_hw_array(iobase, int, ioport, NULL, 0);
1180 MODULE_PARM_DESC(iobase, "baycom io base address");
1181
1182 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
1183 MODULE_DESCRIPTION("Baycom epp amateur radio modem driver");
1184 MODULE_LICENSE("GPL");
1185
1186
1187
1188 static int baycom_epp_par_probe(struct pardevice *par_dev)
1189 {
1190 struct device_driver *drv = par_dev->dev.driver;
1191 int len = strlen(drv->name);
1192
1193 if (strncmp(par_dev->name, drv->name, len))
1194 return -ENODEV;
1195
1196 return 0;
1197 }
1198
1199 static struct parport_driver baycom_epp_par_driver = {
1200 .name = "bce",
1201 .probe = baycom_epp_par_probe,
1202 .devmodel = true,
1203 };
1204
1205 static void __init baycom_epp_dev_setup(struct net_device *dev)
1206 {
1207 struct baycom_state *bc = netdev_priv(dev);
1208
1209
1210
1211
1212 bc->dev = dev;
1213 bc->magic = BAYCOM_MAGIC;
1214 bc->cfg.fclk = 19666600;
1215 bc->cfg.bps = 9600;
1216
1217
1218
1219 baycom_probe(dev);
1220 }
1221
1222 static int __init init_baycomepp(void)
1223 {
1224 int i, found = 0, ret;
1225 char set_hw = 1;
1226
1227 printk(bc_drvinfo);
1228
1229 ret = parport_register_driver(&baycom_epp_par_driver);
1230 if (ret)
1231 return ret;
1232
1233
1234
1235
1236 for (i = 0; i < NR_PORTS; i++) {
1237 struct net_device *dev;
1238
1239 dev = alloc_netdev(sizeof(struct baycom_state), "bce%d",
1240 NET_NAME_UNKNOWN, baycom_epp_dev_setup);
1241
1242 if (!dev) {
1243 printk(KERN_WARNING "bce%d : out of memory\n", i);
1244 return found ? 0 : -ENOMEM;
1245 }
1246
1247 sprintf(dev->name, "bce%d", i);
1248 dev->base_addr = iobase[i];
1249
1250 if (!mode[i])
1251 set_hw = 0;
1252 if (!set_hw)
1253 iobase[i] = 0;
1254
1255 if (register_netdev(dev)) {
1256 printk(KERN_WARNING "%s: cannot register net device %s\n", bc_drvname, dev->name);
1257 free_netdev(dev);
1258 break;
1259 }
1260 if (set_hw && baycom_setmode(netdev_priv(dev), mode[i]))
1261 set_hw = 0;
1262 baycom_device[i] = dev;
1263 found++;
1264 }
1265
1266 if (found == 0) {
1267 parport_unregister_driver(&baycom_epp_par_driver);
1268 return -ENXIO;
1269 }
1270
1271 return 0;
1272 }
1273
1274 static void __exit cleanup_baycomepp(void)
1275 {
1276 int i;
1277
1278 for(i = 0; i < NR_PORTS; i++) {
1279 struct net_device *dev = baycom_device[i];
1280
1281 if (dev) {
1282 struct baycom_state *bc = netdev_priv(dev);
1283 if (bc->magic == BAYCOM_MAGIC) {
1284 unregister_netdev(dev);
1285 free_netdev(dev);
1286 } else
1287 printk(paranoia_str, "cleanup_module");
1288 }
1289 }
1290 parport_unregister_driver(&baycom_epp_par_driver);
1291 }
1292
1293 module_init(init_baycomepp);
1294 module_exit(cleanup_baycomepp);
1295
1296
1297
1298 #ifndef MODULE
1299
1300
1301
1302
1303
1304
1305 static int __init baycom_epp_setup(char *str)
1306 {
1307 static unsigned __initdata nr_dev = 0;
1308 int ints[2];
1309
1310 if (nr_dev >= NR_PORTS)
1311 return 0;
1312 str = get_options(str, 2, ints);
1313 if (ints[0] < 1)
1314 return 0;
1315 mode[nr_dev] = str;
1316 iobase[nr_dev] = ints[1];
1317 nr_dev++;
1318 return 1;
1319 }
1320
1321 __setup("baycom_epp=", baycom_epp_setup);
1322
1323 #endif
1324