net/fjes/fjes_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  FUJITSU Extended Socket Network Device driver
0004  *  Copyright (c) 2015 FUJITSU LIMITED
0005  */
0006
0007 #ifndef FJES_REGS_H_
0008 #define FJES_REGS_H_
0009
0010 #include <linux/bitops.h>
0011
0012 #define XSCT_DEVICE_REGISTER_SIZE 0x1000
0013
0014 /* register offset */
0015 /* Information registers */
0016 #define XSCT_OWNER_EPID     0x0000  /* Owner EPID */
0017 #define XSCT_MAX_EP         0x0004  /* Maximum EP */
0018
0019 /* Device Control registers */
0020 #define XSCT_DCTL           0x0010  /* Device Control */
0021
0022 /* Command Control registers */
0023 #define XSCT_CR             0x0020  /* Command request */
0024 #define XSCT_CS             0x0024  /* Command status */
0025 #define XSCT_SHSTSAL        0x0028  /* Share status address Low */
0026 #define XSCT_SHSTSAH        0x002C  /* Share status address High */
0027
0028 #define XSCT_REQBL          0x0034  /* Request Buffer length */
0029 #define XSCT_REQBAL         0x0038  /* Request Buffer Address Low */
0030 #define XSCT_REQBAH         0x003C  /* Request Buffer Address High */
0031
0032 #define XSCT_RESPBL         0x0044  /* Response Buffer Length */
0033 #define XSCT_RESPBAL        0x0048  /* Response Buffer Address Low */
0034 #define XSCT_RESPBAH        0x004C  /* Response Buffer Address High */
0035
0036 /* Interrupt Control registers */
0037 #define XSCT_IS             0x0080  /* Interrupt status */
0038 #define XSCT_IMS            0x0084  /* Interrupt mask set */
0039 #define XSCT_IMC            0x0088  /* Interrupt mask clear */
0040 #define XSCT_IG             0x008C  /* Interrupt generator */
0041 #define XSCT_ICTL           0x0090  /* Interrupt control */
0042
0043 /* register structure */
0044 /* Information registers */
0045 union REG_OWNER_EPID {
0046     struct {
0047         __le32 epid:16;
0048         __le32:16;
0049     } bits;
0050     __le32 reg;
0051 };
0052
0053 union REG_MAX_EP {
0054     struct {
0055         __le32 maxep:16;
0056         __le32:16;
0057     } bits;
0058     __le32 reg;
0059 };
0060
0061 /* Device Control registers */
0062 union REG_DCTL {
0063     struct {
0064         __le32 reset:1;
0065         __le32 rsv0:15;
0066         __le32 rsv1:16;
0067     } bits;
0068     __le32 reg;
0069 };
0070
0071 /* Command Control registers */
0072 union REG_CR {
0073     struct {
0074         __le32 req_code:16;
0075         __le32 err_info:14;
0076         __le32 error:1;
0077         __le32 req_start:1;
0078     } bits;
0079     __le32 reg;
0080 };
0081
0082 union REG_CS {
0083     struct {
0084         __le32 req_code:16;
0085         __le32 rsv0:14;
0086         __le32 busy:1;
0087         __le32 complete:1;
0088     } bits;
0089     __le32 reg;
0090 };
0091
0092 /* Interrupt Control registers */
0093 union REG_ICTL {
0094     struct {
0095         __le32 automak:1;
0096         __le32 rsv0:31;
0097     } bits;
0098     __le32 reg;
0099 };
0100
0101 enum REG_ICTL_MASK {
0102     REG_ICTL_MASK_INFO_UPDATE     = 1 << 20,
0103     REG_ICTL_MASK_DEV_STOP_REQ    = 1 << 19,
0104     REG_ICTL_MASK_TXRX_STOP_REQ   = 1 << 18,
0105     REG_ICTL_MASK_TXRX_STOP_DONE  = 1 << 17,
0106     REG_ICTL_MASK_RX_DATA         = 1 << 16,
0107     REG_ICTL_MASK_ALL             = GENMASK(20, 16),
0108 };
0109
0110 enum REG_IS_MASK {
0111     REG_IS_MASK_IS_ASSERT   = 1 << 31,
0112     REG_IS_MASK_EPID    = GENMASK(15, 0),
0113 };
0114
0115 struct fjes_hw;
0116
0117 u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg);
0118
0119 #define wr32(reg, val) \
0120 do { \
0121     u8 *base = hw->base; \
0122     writel((val), &base[(reg)]); \
0123 } while (0)
0124
0125 #define rd32(reg) (fjes_hw_rd32(hw, reg))
0126
0127 #endif /* FJES_REGS_H_ */