skfp/h/skfbi.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /******************************************************************************
0003  *
0004  *  (C)Copyright 1998,1999 SysKonnect,
0005  *  a business unit of Schneider & Koch & Co. Datensysteme GmbH.
0006  *
0007  *  The information in this file is provided "AS IS" without warranty.
0008  *
0009  ******************************************************************************/
0010
0011 #ifndef _SKFBI_H_
0012 #define _SKFBI_H_
0013
0014 /*
0015  * FDDI-Fx (x := {I(SA), P(CI)})
0016  *  address calculation & function defines
0017  */
0018
0019 /*--------------------------------------------------------------------------*/
0020 #ifdef  PCI
0021
0022 /*
0023  *  (DV)    = only defined for Da Vinci
0024  *  (ML)    = only defined for Monalisa
0025  */
0026
0027
0028 /*
0029  * I2C Address (PCI Config)
0030  *
0031  * Note: The temperature and voltage sensors are relocated on a different
0032  *   I2C bus.
0033  */
0034 #define I2C_ADDR_VPD    0xA0    /* I2C address for the VPD EEPROM */
0035
0036 /*
0037  *  Control Register File:
0038  *  Bank 0
0039  */
0040 #define B0_RAP      0x0000  /*  8 bit register address port */
0041     /* 0x0001 - 0x0003: reserved */
0042 #define B0_CTRL     0x0004  /*  8 bit control register */
0043 #define B0_DAS      0x0005  /*  8 Bit control register (DAS) */
0044 #define B0_LED      0x0006  /*  8 Bit LED register */
0045 #define B0_TST_CTRL 0x0007  /*  8 bit test control register */
0046 #define B0_ISRC     0x0008  /* 32 bit Interrupt source register */
0047 #define B0_IMSK     0x000c  /* 32 bit Interrupt mask register */
0048
0049 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
0050 #define B0_CMDREG1  0x0010  /* write command reg 1 instruction */
0051 #define B0_CMDREG2  0x0014  /* write command reg 2 instruction */
0052 #define B0_ST1U     0x0010  /* read upper 16-bit of status reg 1 */
0053 #define B0_ST1L     0x0014  /* read lower 16-bit of status reg 1 */
0054 #define B0_ST2U     0x0018  /* read upper 16-bit of status reg 2 */
0055 #define B0_ST2L     0x001c  /* read lower 16-bit of status reg 2 */
0056
0057 #define B0_MARR     0x0020  /* r/w the memory read addr register */
0058 #define B0_MARW     0x0024  /* r/w the memory write addr register*/
0059 #define B0_MDRU     0x0028  /* r/w upper 16-bit of mem. data reg */
0060 #define B0_MDRL     0x002c  /* r/w lower 16-bit of mem. data reg */
0061
0062 #define B0_MDREG3   0x0030  /* r/w Mode Register 3 */
0063 #define B0_ST3U     0x0034  /* read upper 16-bit of status reg 3 */
0064 #define B0_ST3L     0x0038  /* read lower 16-bit of status reg 3 */
0065 #define B0_IMSK3U   0x003c  /* r/w upper 16-bit of IMSK reg 3 */
0066 #define B0_IMSK3L   0x0040  /* r/w lower 16-bit of IMSK reg 3 */
0067 #define B0_IVR      0x0044  /* read Interrupt Vector register */
0068 #define B0_IMR      0x0048  /* r/w Interrupt mask register */
0069 /* 0x4c Hidden */
0070
0071 #define B0_CNTRL_A  0x0050  /* control register A (r/w) */
0072 #define B0_CNTRL_B  0x0054  /* control register B (r/w) */
0073 #define B0_INTR_MASK    0x0058  /* interrupt mask (r/w) */
0074 #define B0_XMIT_VECTOR  0x005c  /* transmit vector register (r/w) */
0075
0076 #define B0_STATUS_A 0x0060  /* status register A (read only) */
0077 #define B0_STATUS_B 0x0064  /* status register B (read only) */
0078 #define B0_CNTRL_C  0x0068  /* control register C (r/w) */
0079 #define B0_MDREG1   0x006c  /* r/w Mode Register 1 */
0080
0081 #define B0_R1_CSR   0x0070  /* 32 bit BMU control/status reg (rec q 1) */
0082 #define B0_R2_CSR   0x0074  /* 32 bit BMU control/status reg (rec q 2)(DV)*/
0083 #define B0_XA_CSR   0x0078  /* 32 bit BMU control/status reg (a xmit q) */
0084 #define B0_XS_CSR   0x007c  /* 32 bit BMU control/status reg (s xmit q) */
0085
0086 /*
0087  *  Bank 1
0088  *  - completely empty (this is the RAP Block window)
0089  *  Note: if RAP = 1 this page is reserved
0090  */
0091
0092 /*
0093  *  Bank 2
0094  */
0095 #define B2_MAC_0    0x0100  /*  8 bit MAC address Byte 0 */
0096 #define B2_MAC_1    0x0101  /*  8 bit MAC address Byte 1 */
0097 #define B2_MAC_2    0x0102  /*  8 bit MAC address Byte 2 */
0098 #define B2_MAC_3    0x0103  /*  8 bit MAC address Byte 3 */
0099 #define B2_MAC_4    0x0104  /*  8 bit MAC address Byte 4 */
0100 #define B2_MAC_5    0x0105  /*  8 bit MAC address Byte 5 */
0101 #define B2_MAC_6    0x0106  /*  8 bit MAC address Byte 6 (== 0) (DV) */
0102 #define B2_MAC_7    0x0107  /*  8 bit MAC address Byte 7 (== 0) (DV) */
0103
0104 #define B2_CONN_TYP 0x0108  /*  8 bit Connector type */
0105 #define B2_PMD_TYP  0x0109  /*  8 bit PMD type */
0106                 /* 0x010a - 0x010b: reserved */
0107     /* Eprom registers are currently of no use */
0108 #define B2_E_0      0x010c  /*  8 bit EPROM Byte 0 */
0109 #define B2_E_1      0x010d  /*  8 bit EPROM Byte 1 */
0110 #define B2_E_2      0x010e  /*  8 bit EPROM Byte 2 */
0111 #define B2_E_3      0x010f  /*  8 bit EPROM Byte 3 */
0112 #define B2_FAR      0x0110  /* 32 bit Flash-Prom Address Register/Counter */
0113 #define B2_FDP      0x0114  /*  8 bit Flash-Prom Data Port */
0114                 /* 0x0115 - 0x0117: reserved */
0115 #define B2_LD_CRTL  0x0118  /*  8 bit loader control */
0116 #define B2_LD_TEST  0x0119  /*  8 bit loader test */
0117                 /* 0x011a - 0x011f: reserved */
0118 #define B2_TI_INI   0x0120  /* 32 bit Timer init value */
0119 #define B2_TI_VAL   0x0124  /* 32 bit Timer value */
0120 #define B2_TI_CRTL  0x0128  /*  8 bit Timer control */
0121 #define B2_TI_TEST  0x0129  /*  8 Bit Timer Test */
0122                 /* 0x012a - 0x012f: reserved */
0123 #define B2_WDOG_INI 0x0130  /* 32 bit Watchdog init value */
0124 #define B2_WDOG_VAL 0x0134  /* 32 bit Watchdog value */
0125 #define B2_WDOG_CRTL    0x0138  /*  8 bit Watchdog control */
0126 #define B2_WDOG_TEST    0x0139  /*  8 Bit Watchdog Test */
0127                 /* 0x013a - 0x013f: reserved */
0128 #define B2_RTM_INI  0x0140  /* 32 bit RTM init value */
0129 #define B2_RTM_VAL  0x0144  /* 32 bit RTM value */
0130 #define B2_RTM_CRTL 0x0148  /*  8 bit RTM control */
0131 #define B2_RTM_TEST 0x0149  /*  8 Bit RTM Test */
0132
0133 #define B2_TOK_COUNT    0x014c  /* (ML) 32 bit  Token Counter */
0134 #define B2_DESC_ADDR_H  0x0150  /* (ML) 32 bit  Desciptor Base Addr Reg High */
0135 #define B2_CTRL_2   0x0154  /* (ML)  8 bit  Control Register 2 */
0136 #define B2_IFACE_REG    0x0155  /* (ML)  8 bit  Interface Register */
0137                 /* 0x0156:      reserved */
0138 #define B2_TST_CTRL_2   0x0157  /* (ML)  8 bit  Test Control Register 2 */
0139 #define B2_I2C_CTRL 0x0158  /* (ML) 32 bit  I2C Control Register */
0140 #define B2_I2C_DATA 0x015c  /* (ML) 32 bit  I2C Data Register */
0141
0142 #define B2_IRQ_MOD_INI  0x0160  /* (ML) 32 bit  IRQ Moderation Timer Init Reg. */
0143 #define B2_IRQ_MOD_VAL  0x0164  /* (ML) 32 bit  IRQ Moderation Timer Value */
0144 #define B2_IRQ_MOD_CTRL 0x0168  /* (ML)  8 bit  IRQ Moderation Timer Control */
0145 #define B2_IRQ_MOD_TEST 0x0169  /* (ML)  8 bit  IRQ Moderation Timer Test */
0146                 /* 0x016a - 0x017f: reserved */
0147
0148 /*
0149  *  Bank 3
0150  */
0151 /*
0152  * This is a copy of the Configuration register file (lower half)
0153  */
0154 #define B3_CFG_SPC  0x180
0155
0156 /*
0157  *  Bank 4
0158  */
0159 #define B4_R1_D     0x0200  /*  4*32 bit current receive Descriptor  */
0160 #define B4_R1_DA    0x0210  /*  32 bit current rec desc address      */
0161 #define B4_R1_AC    0x0214  /*  32 bit current receive Address Count */
0162 #define B4_R1_BC    0x0218  /*  32 bit current receive Byte Counter  */
0163 #define B4_R1_CSR   0x021c  /*  32 bit BMU Control/Status Register   */
0164 #define B4_R1_F     0x0220  /*  32 bit flag register             */
0165 #define B4_R1_T1    0x0224  /*  32 bit Test Register 1           */
0166 #define B4_R1_T1_TR 0x0224  /*  8 bit Test Register 1 TR         */
0167 #define B4_R1_T1_WR 0x0225  /*  8 bit Test Register 1 WR         */
0168 #define B4_R1_T1_RD 0x0226  /*  8 bit Test Register 1 RD         */
0169 #define B4_R1_T1_SV 0x0227  /*  8 bit Test Register 1 SV         */
0170 #define B4_R1_T2    0x0228  /*  32 bit Test Register 2           */
0171 #define B4_R1_T3    0x022c  /*  32 bit Test Register 3           */
0172 #define B4_R1_DA_H  0x0230  /* (ML) 32 bit Curr Rx Desc Address High     */
0173 #define B4_R1_AC_H  0x0234  /* (ML) 32 bit Curr Addr Counter High dword  */
0174                 /* 0x0238 - 0x023f: reserved      */
0175                 /* Receive queue 2 is removed on Monalisa */
0176 #define B4_R2_D     0x0240  /* 4*32 bit current receive Descriptor  (q2) */
0177 #define B4_R2_DA    0x0250  /* 32 bit current rec desc address  (q2) */
0178 #define B4_R2_AC    0x0254  /* 32 bit current receive Address Count (q2) */
0179 #define B4_R2_BC    0x0258  /* 32 bit current receive Byte Counter  (q2) */
0180 #define B4_R2_CSR   0x025c  /* 32 bit BMU Control/Status Register   (q2) */
0181 #define B4_R2_F     0x0260  /* 32 bit flag register         (q2) */
0182 #define B4_R2_T1    0x0264  /* 32 bit Test Register 1       (q2) */
0183 #define B4_R2_T1_TR 0x0264  /* 8 bit Test Register 1 TR     (q2) */
0184 #define B4_R2_T1_WR 0x0265  /* 8 bit Test Register 1 WR     (q2) */
0185 #define B4_R2_T1_RD 0x0266  /* 8 bit Test Register 1 RD     (q2) */
0186 #define B4_R2_T1_SV 0x0267  /* 8 bit Test Register 1 SV     (q2) */
0187 #define B4_R2_T2    0x0268  /* 32 bit Test Register 2       (q2) */
0188 #define B4_R2_T3    0x026c  /* 32 bit Test Register 3       (q2) */
0189                 /* 0x0270 - 0x027c: reserved */
0190
0191 /*
0192  *  Bank 5
0193  */
0194 #define B5_XA_D     0x0280  /* 4*32 bit current transmit Descriptor (xa) */
0195 #define B5_XA_DA    0x0290  /* 32 bit current tx desc address   (xa) */
0196 #define B5_XA_AC    0x0294  /* 32 bit current tx Address Count  (xa) */
0197 #define B5_XA_BC    0x0298  /* 32 bit current tx Byte Counter   (xa) */
0198 #define B5_XA_CSR   0x029c  /* 32 bit BMU Control/Status Register   (xa) */
0199 #define B5_XA_F     0x02a0  /* 32 bit flag register         (xa) */
0200 #define B5_XA_T1    0x02a4  /* 32 bit Test Register 1       (xa) */
0201 #define B5_XA_T1_TR 0x02a4  /* 8 bit Test Register 1 TR     (xa) */
0202 #define B5_XA_T1_WR 0x02a5  /* 8 bit Test Register 1 WR     (xa) */
0203 #define B5_XA_T1_RD 0x02a6  /* 8 bit Test Register 1 RD     (xa) */
0204 #define B5_XA_T1_SV 0x02a7  /* 8 bit Test Register 1 SV     (xa) */
0205 #define B5_XA_T2    0x02a8  /* 32 bit Test Register 2       (xa) */
0206 #define B5_XA_T3    0x02ac  /* 32 bit Test Register 3       (xa) */
0207 #define B5_XA_DA_H  0x02b0  /* (ML) 32 bit Curr Tx Desc Address High     */
0208 #define B5_XA_AC_H  0x02b4  /* (ML) 32 bit Curr Addr Counter High dword  */
0209                 /* 0x02b8 - 0x02bc: reserved */
0210 #define B5_XS_D     0x02c0  /* 4*32 bit current transmit Descriptor (xs) */
0211 #define B5_XS_DA    0x02d0  /* 32 bit current tx desc address   (xs) */
0212 #define B5_XS_AC    0x02d4  /* 32 bit current transmit Address Count(xs) */
0213 #define B5_XS_BC    0x02d8  /* 32 bit current transmit Byte Counter (xs) */
0214 #define B5_XS_CSR   0x02dc  /* 32 bit BMU Control/Status Register   (xs) */
0215 #define B5_XS_F     0x02e0  /* 32 bit flag register         (xs) */
0216 #define B5_XS_T1    0x02e4  /* 32 bit Test Register 1       (xs) */
0217 #define B5_XS_T1_TR 0x02e4  /* 8 bit Test Register 1 TR     (xs) */
0218 #define B5_XS_T1_WR 0x02e5  /* 8 bit Test Register 1 WR     (xs) */
0219 #define B5_XS_T1_RD 0x02e6  /* 8 bit Test Register 1 RD     (xs) */
0220 #define B5_XS_T1_SV 0x02e7  /* 8 bit Test Register 1 SV     (xs) */
0221 #define B5_XS_T2    0x02e8  /* 32 bit Test Register 2       (xs) */
0222 #define B5_XS_T3    0x02ec  /* 32 bit Test Register 3       (xs) */
0223 #define B5_XS_DA_H  0x02f0  /* (ML) 32 bit Curr Tx Desc Address High     */
0224 #define B5_XS_AC_H  0x02f4  /* (ML) 32 bit Curr Addr Counter High dword  */
0225                 /* 0x02f8 - 0x02fc: reserved */
0226
0227 /*
0228  *  Bank 6
0229  */
0230 /* External PLC-S registers (SN2 compatibility for DV) */
0231 /* External registers (ML) */
0232 #define B6_EXT_REG  0x300
0233
0234 /*
0235  *  Bank 7
0236  */
0237 /* DAS PLC-S Registers */
0238
0239 /*
0240  *  Bank 8 - 15
0241  */
0242 /* IFCP registers */
0243
0244 /*---------------------------------------------------------------------------*/
0245 /* Definitions of the Bits in the registers */
0246
0247 /*  B0_RAP      16 bit register address port */
0248 #define RAP_RAP     0x0f    /* Bit 3..0:    0 = block0, .., f = block15 */
0249
0250 /*  B0_CTRL     8 bit control register */
0251 #define CTRL_FDDI_CLR   (1<<7)  /* Bit 7: (ML)  Clear FDDI Reset */
0252 #define CTRL_FDDI_SET   (1<<6)  /* Bit 6: (ML)  Set FDDI Reset */
0253 #define CTRL_HPI_CLR    (1<<5)  /* Bit 5:   Clear HPI SM reset */
0254 #define CTRL_HPI_SET    (1<<4)  /* Bit 4:   Set HPI SM reset */
0255 #define CTRL_MRST_CLR   (1<<3)  /* Bit 3:   Clear Master reset */
0256 #define CTRL_MRST_SET   (1<<2)  /* Bit 2:   Set Master reset */
0257 #define CTRL_RST_CLR    (1<<1)  /* Bit 1:   Clear Software reset */
0258 #define CTRL_RST_SET    (1<<0)  /* Bit 0:   Set Software reset */
0259
0260 /*  B0_DAS      8 Bit control register (DAS) */
0261 #define BUS_CLOCK   (1<<7)  /* Bit 7: (ML)  Bus Clock 0/1 = 33/66MHz */
0262 #define BUS_SLOT_SZ (1<<6)  /* Bit 6: (ML)  Slot Size 0/1 = 32/64 bit slot*/
0263                 /* Bit 5..4:    reserved */
0264 #define DAS_AVAIL   (1<<3)  /* Bit 3:   1 = DAS, 0 = SAS */
0265 #define DAS_BYP_ST  (1<<2)  /* Bit 2:   1 = avail,SAS, 0 = not avail */
0266 #define DAS_BYP_INS (1<<1)  /* Bit 1:   1 = insert Bypass */
0267 #define DAS_BYP_RMV (1<<0)  /* Bit 0:   1 = remove Bypass */
0268
0269 /*  B0_LED      8 Bit LED register */
0270                 /* Bit 7..6:    reserved */
0271 #define LED_2_ON    (1<<5)  /* Bit 5:   1 = switch LED_2 on (left,gn)*/
0272 #define LED_2_OFF   (1<<4)  /* Bit 4:   1 = switch LED_2 off */
0273 #define LED_1_ON    (1<<3)  /* Bit 3:   1 = switch LED_1 on (mid,yel)*/
0274 #define LED_1_OFF   (1<<2)  /* Bit 2:   1 = switch LED_1 off */
0275 #define LED_0_ON    (1<<1)  /* Bit 1:   1 = switch LED_0 on (rght,gn)*/
0276 #define LED_0_OFF   (1<<0)  /* Bit 0:   1 = switch LED_0 off */
0277 /* This hardware defines are very ugly therefore we define some others */
0278
0279 #define LED_GA_ON   LED_2_ON    /* S port = A port */
0280 #define LED_GA_OFF  LED_2_OFF   /* S port = A port */
0281 #define LED_MY_ON   LED_1_ON
0282 #define LED_MY_OFF  LED_1_OFF
0283 #define LED_GB_ON   LED_0_ON
0284 #define LED_GB_OFF  LED_0_OFF
0285
0286 /*  B0_TST_CTRL 8 bit test control register */
0287 #define TST_FRC_DPERR_MR    (1<<7)  /* Bit 7:  force DATAPERR on MST RE. */
0288 #define TST_FRC_DPERR_MW    (1<<6)  /* Bit 6:  force DATAPERR on MST WR. */
0289 #define TST_FRC_DPERR_TR    (1<<5)  /* Bit 5:  force DATAPERR on TRG RE. */
0290 #define TST_FRC_DPERR_TW    (1<<4)  /* Bit 4:  force DATAPERR on TRG WR. */
0291 #define TST_FRC_APERR_M     (1<<3)  /* Bit 3:  force ADDRPERR on MST     */
0292 #define TST_FRC_APERR_T     (1<<2)  /* Bit 2:  force ADDRPERR on TRG     */
0293 #define TST_CFG_WRITE_ON    (1<<1)  /* Bit 1:  ena configuration reg. WR */
0294 #define TST_CFG_WRITE_OFF   (1<<0)  /* Bit 0:  dis configuration reg. WR */
0295
0296 /*  B0_ISRC     32 bit Interrupt source register */
0297                     /* Bit 31..28:  reserved         */
0298 #define IS_I2C_READY    (1L<<27)    /* Bit 27: (ML) IRQ on end of I2C tx */
0299 #define IS_IRQ_SW   (1L<<26)    /* Bit 26: (ML) SW forced IRQ        */
0300 #define IS_EXT_REG  (1L<<25)    /* Bit 25: (ML) IRQ from external reg*/
0301 #define IS_IRQ_STAT (1L<<24)    /* Bit 24:  IRQ status exception */
0302                     /*   PERR, RMABORT, RTABORT DATAPERR */
0303 #define IS_IRQ_MST_ERR  (1L<<23)    /* Bit 23:  IRQ master error     */
0304                     /*   RMABORT, RTABORT, DATAPERR      */
0305 #define IS_TIMINT   (1L<<22)    /* Bit 22:  IRQ_TIMER   */
0306 #define IS_TOKEN    (1L<<21)    /* Bit 21:  IRQ_RTM     */
0307 /*
0308  * Note: The DAS is our First Port (!=PA)
0309  */
0310 #define IS_PLINT1   (1L<<20)    /* Bit 20:  IRQ_PHY_DAS */
0311 #define IS_PLINT2   (1L<<19)    /* Bit 19:  IRQ_IFCP_4  */
0312 #define IS_MINTR3   (1L<<18)    /* Bit 18:  IRQ_IFCP_3/IRQ_PHY */
0313 #define IS_MINTR2   (1L<<17)    /* Bit 17:  IRQ_IFCP_2/IRQ_MAC_2 */
0314 #define IS_MINTR1   (1L<<16)    /* Bit 16:  IRQ_IFCP_1/IRQ_MAC_1 */
0315 /* Receive Queue 1 */
0316 #define IS_R1_P     (1L<<15)    /* Bit 15:  Parity Error (q1) */
0317 #define IS_R1_B     (1L<<14)    /* Bit 14:  End of Buffer (q1) */
0318 #define IS_R1_F     (1L<<13)    /* Bit 13:  End of Frame (q1) */
0319 #define IS_R1_C     (1L<<12)    /* Bit 12:  Encoding Error (q1) */
0320 /* Receive Queue 2 */
0321 #define IS_R2_P     (1L<<11)    /* Bit 11: (DV) Parity Error (q2) */
0322 #define IS_R2_B     (1L<<10)    /* Bit 10: (DV) End of Buffer (q2) */
0323 #define IS_R2_F     (1L<<9)     /* Bit  9: (DV) End of Frame (q2) */
0324 #define IS_R2_C     (1L<<8)     /* Bit  8: (DV) Encoding Error (q2) */
0325 /* Asynchronous Transmit queue */
0326                     /* Bit  7:  reserved */
0327 #define IS_XA_B     (1L<<6)     /* Bit  6:  End of Buffer (xa) */
0328 #define IS_XA_F     (1L<<5)     /* Bit  5:  End of Frame (xa) */
0329 #define IS_XA_C     (1L<<4)     /* Bit  4:  Encoding Error (xa) */
0330 /* Synchronous Transmit queue */
0331                     /* Bit  3:  reserved */
0332 #define IS_XS_B     (1L<<2)     /* Bit  2:  End of Buffer (xs) */
0333 #define IS_XS_F     (1L<<1)     /* Bit  1:  End of Frame (xs) */
0334 #define IS_XS_C     (1L<<0)     /* Bit  0:  Encoding Error (xs) */
0335
0336 /*
0337  * Define all valid interrupt source Bits from GET_ISR ()
0338  */
0339 #define ALL_IRSR    0x01ffff77L /* (DV) */
0340 #define ALL_IRSR_ML 0x0ffff077L /* (ML) */
0341
0342
0343 /*  B0_IMSK     32 bit Interrupt mask register */
0344 /*
0345  * The Bit definnition of this register are the same as of the interrupt
0346  * source register. These definition are directly derived from the Hardware
0347  * spec.
0348  */
0349                     /* Bit 31..28:  reserved         */
0350 #define IRQ_I2C_READY   (1L<<27)    /* Bit 27: (ML) IRQ on end of I2C tx */
0351 #define IRQ_SW      (1L<<26)    /* Bit 26: (ML) SW forced IRQ        */
0352 #define IRQ_EXT_REG (1L<<25)    /* Bit 25: (ML) IRQ from external reg*/
0353 #define IRQ_STAT    (1L<<24)    /* Bit 24:  IRQ status exception */
0354                     /*   PERR, RMABORT, RTABORT DATAPERR */
0355 #define IRQ_MST_ERR (1L<<23)    /* Bit 23:  IRQ master error     */
0356                     /*   RMABORT, RTABORT, DATAPERR      */
0357 #define IRQ_TIMER   (1L<<22)    /* Bit 22:  IRQ_TIMER   */
0358 #define IRQ_RTM     (1L<<21)    /* Bit 21:  IRQ_RTM     */
0359 #define IRQ_DAS     (1L<<20)    /* Bit 20:  IRQ_PHY_DAS */
0360 #define IRQ_IFCP_4  (1L<<19)    /* Bit 19:  IRQ_IFCP_4  */
0361 #define IRQ_IFCP_3  (1L<<18)    /* Bit 18:  IRQ_IFCP_3/IRQ_PHY */
0362 #define IRQ_IFCP_2  (1L<<17)    /* Bit 17:  IRQ_IFCP_2/IRQ_MAC_2 */
0363 #define IRQ_IFCP_1  (1L<<16)    /* Bit 16:  IRQ_IFCP_1/IRQ_MAC_1 */
0364 /* Receive Queue 1 */
0365 #define IRQ_R1_P    (1L<<15)    /* Bit 15:  Parity Error (q1) */
0366 #define IRQ_R1_B    (1L<<14)    /* Bit 14:  End of Buffer (q1) */
0367 #define IRQ_R1_F    (1L<<13)    /* Bit 13:  End of Frame (q1) */
0368 #define IRQ_R1_C    (1L<<12)    /* Bit 12:  Encoding Error (q1) */
0369 /* Receive Queue 2 */
0370 #define IRQ_R2_P    (1L<<11)    /* Bit 11: (DV) Parity Error (q2) */
0371 #define IRQ_R2_B    (1L<<10)    /* Bit 10: (DV) End of Buffer (q2) */
0372 #define IRQ_R2_F    (1L<<9)     /* Bit  9: (DV) End of Frame (q2) */
0373 #define IRQ_R2_C    (1L<<8)     /* Bit  8: (DV) Encoding Error (q2) */
0374 /* Asynchronous Transmit queue */
0375                     /* Bit  7:  reserved */
0376 #define IRQ_XA_B    (1L<<6)     /* Bit  6:  End of Buffer (xa) */
0377 #define IRQ_XA_F    (1L<<5)     /* Bit  5:  End of Frame (xa) */
0378 #define IRQ_XA_C    (1L<<4)     /* Bit  4:  Encoding Error (xa) */
0379 /* Synchronous Transmit queue */
0380                     /* Bit  3:  reserved */
0381 #define IRQ_XS_B    (1L<<2)     /* Bit  2:  End of Buffer (xs) */
0382 #define IRQ_XS_F    (1L<<1)     /* Bit  1:  End of Frame (xs) */
0383 #define IRQ_XS_C    (1L<<0)     /* Bit  0:  Encoding Error (xs) */
0384
0385 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
0386 /*  B0_R1_CSR   32 bit BMU control/status reg (rec q 1 ) */
0387 /*  B0_R2_CSR   32 bit BMU control/status reg (rec q 2 ) */
0388 /*  B0_XA_CSR   32 bit BMU control/status reg (a xmit q ) */
0389 /*  B0_XS_CSR   32 bit BMU control/status reg (s xmit q ) */
0390 /* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */
0391
0392 /*  B2_MAC_0    8 bit MAC address Byte 0 */
0393 /*  B2_MAC_1    8 bit MAC address Byte 1 */
0394 /*  B2_MAC_2    8 bit MAC address Byte 2 */
0395 /*  B2_MAC_3    8 bit MAC address Byte 3 */
0396 /*  B2_MAC_4    8 bit MAC address Byte 4 */
0397 /*  B2_MAC_5    8 bit MAC address Byte 5 */
0398 /*  B2_MAC_6    8 bit MAC address Byte 6 (== 0) (DV) */
0399 /*  B2_MAC_7    8 bit MAC address Byte 7 (== 0) (DV) */
0400
0401 /*  B2_CONN_TYP 8 bit Connector type */
0402 /*  B2_PMD_TYP  8 bit PMD type */
0403 /*  Values of connector and PMD type comply to SysKonnect internal std */
0404
0405 /*  The EPROM register are currently of no use */
0406 /*  B2_E_0      8 bit EPROM Byte 0 */
0407 /*  B2_E_1      8 bit EPROM Byte 1 */
0408 /*  B2_E_2      8 bit EPROM Byte 2 */
0409 /*  B2_E_3      8 bit EPROM Byte 3 */
0410
0411 /*  B2_FAR      32 bit Flash-Prom Address Register/Counter */
0412 #define FAR_ADDR    0x1ffffL    /* Bit 16..0:   FPROM Address mask */
0413
0414 /*  B2_FDP      8 bit Flash-Prom Data Port */
0415
0416 /*  B2_LD_CRTL  8 bit loader control */
0417 /*  Bits are currently reserved */
0418
0419 /*  B2_LD_TEST  8 bit loader test */
0420 #define LD_T_ON     (1<<3)  /* Bit 3:    Loader Testmode on */
0421 #define LD_T_OFF    (1<<2)  /* Bit 2:    Loader Testmode off */
0422 #define LD_T_STEP   (1<<1)  /* Bit 1:    Decrement FPROM addr. Counter */
0423 #define LD_START    (1<<0)  /* Bit 0:    Start loading FPROM */
0424
0425 /*  B2_TI_INI   32 bit Timer init value */
0426 /*  B2_TI_VAL   32 bit Timer value */
0427 /*  B2_TI_CRTL  8 bit Timer control */
0428 /*  B2_TI_TEST  8 Bit Timer Test */
0429 /*  B2_WDOG_INI 32 bit Watchdog init value */
0430 /*  B2_WDOG_VAL 32 bit Watchdog value */
0431 /*  B2_WDOG_CRTL    8 bit Watchdog control */
0432 /*  B2_WDOG_TEST    8 Bit Watchdog Test */
0433 /*  B2_RTM_INI  32 bit RTM init value */
0434 /*  B2_RTM_VAL  32 bit RTM value */
0435 /*  B2_RTM_CRTL 8 bit RTM control */
0436 /*  B2_RTM_TEST 8 Bit RTM Test */
0437 /*  B2_<TIM>_CRTL   8 bit <TIM> control */
0438 /*  B2_IRQ_MOD_INI  32 bit IRQ Moderation Timer Init Reg.   (ML) */
0439 /*  B2_IRQ_MOD_VAL  32 bit IRQ Moderation Timer Value   (ML) */
0440 /*  B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control  (ML) */
0441 /*  B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test     (ML) */
0442 #define GET_TOK_CT  (1<<4)  /* Bit 4: Get the Token Counter (RTM) */
0443 #define TIM_RES_TOK (1<<3)  /* Bit 3: RTM Status: 1 == restricted */
0444 #define TIM_ALARM   (1<<3)  /* Bit 3: Timer Alarm (WDOG) */
0445 #define TIM_START   (1<<2)  /* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/
0446 #define TIM_STOP    (1<<1)  /* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */
0447 #define TIM_CL_IRQ  (1<<0)  /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */
0448 /*  B2_<TIM>_TEST   8 Bit <TIM> Test */
0449 #define TIM_T_ON    (1<<2)  /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */
0450 #define TIM_T_OFF   (1<<1)  /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */
0451 #define TIM_T_STEP  (1<<0)  /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */
0452
0453 /*  B2_TOK_COUNT    0x014c  (ML)    32 bit  Token Counter */
0454 /*  B2_DESC_ADDR_H  0x0150  (ML)    32 bit  Desciptor Base Addr Reg High */
0455 /*  B2_CTRL_2   0x0154  (ML)     8 bit  Control Register 2 */
0456                 /* Bit 7..5:    reserved        */
0457 #define CTRL_CL_I2C_IRQ (1<<4)  /* Bit 4:   Clear I2C IRQ       */
0458 #define CTRL_ST_SW_IRQ  (1<<3)  /* Bit 3:   Set IRQ SW Request  */
0459 #define CTRL_CL_SW_IRQ  (1<<2)  /* Bit 2:   Clear IRQ SW Request    */
0460 #define CTRL_STOP_DONE  (1<<1)  /* Bit 1:   Stop Master is finished */
0461 #define CTRL_STOP_MAST  (1<<0)  /* Bit 0:   Command Bit to stop the master*/
0462
0463 /*  B2_IFACE_REG    0x0155  (ML)     8 bit  Interface Register */
0464                 /* Bit 7..3:    reserved        */
0465 #define IF_I2C_DATA_DIR (1<<2)  /* Bit 2:   direction of IF_I2C_DATA*/
0466 #define IF_I2C_DATA (1<<1)  /* Bit 1:   I2C Data Port       */
0467 #define IF_I2C_CLK  (1<<0)  /* Bit 0:   I2C Clock Port      */
0468
0469                 /* 0x0156:      reserved */
0470 /*  B2_TST_CTRL_2   0x0157  (ML)     8 bit  Test Control Register 2 */
0471                     /* Bit 7..4:    reserved */
0472                     /* force the following error on */
0473                     /* the next master read/write   */
0474 #define TST_FRC_DPERR_MR64  (1<<3)  /* Bit 3:   DataPERR RD 64  */
0475 #define TST_FRC_DPERR_MW64  (1<<2)  /* Bit 2:   DataPERR WR 64  */
0476 #define TST_FRC_APERR_1M64  (1<<1)  /* Bit 1:   AddrPERR on 1. phase */
0477 #define TST_FRC_APERR_2M64  (1<<0)  /* Bit 0:   AddrPERR on 2. phase */
0478
0479 /*  B2_I2C_CTRL 0x0158  (ML)    32 bit  I2C Control Register           */
0480 #define I2C_FLAG    (1L<<31)    /* Bit 31:  Start read/write if WR */
0481 #define I2C_ADDR    (0x7fffL<<16)   /* Bit 30..16:  Addr to be read/written*/
0482 #define I2C_DEV_SEL (0x7fL<<9)  /* Bit  9..15:  I2C Device Select      */
0483                     /* Bit  5.. 8:  reserved           */
0484 #define I2C_BURST_LEN   (1L<<4)     /* Bit  4   Burst Len, 1/4 bytes   */
0485 #define I2C_DEV_SIZE    (7L<<1)     /* Bit  1.. 3:  I2C Device Size        */
0486 #define I2C_025K_DEV    (0L<<1)     /*      0: 256 Bytes or smaller*/
0487 #define I2C_05K_DEV (1L<<1)     /*      1: 512  Bytes          */
0488 #define I2C_1K_DEV  (2L<<1)     /*      2: 1024 Bytes          */
0489 #define I2C_2K_DEV  (3L<<1)     /*      3: 2048 Bytes          */
0490 #define I2C_4K_DEV  (4L<<1)     /*      4: 4096 Bytes          */
0491 #define I2C_8K_DEV  (5L<<1)     /*      5: 8192 Bytes          */
0492 #define I2C_16K_DEV (6L<<1)     /*      6: 16384 Bytes         */
0493 #define I2C_32K_DEV (7L<<1)     /*      7: 32768 Bytes         */
0494 #define I2C_STOP_BIT    (1<<0)      /* Bit  0:  Interrupt I2C transfer */
0495
0496 /*
0497  * I2C Addresses
0498  *
0499  * The temperature sensor and the voltage sensor are on the same I2C bus.
0500  * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1
0501  *   in PCI_OUR_REG 1.
0502  */
0503 #define I2C_ADDR_TEMP   0x90    /* I2C Address Temperature Sensor */
0504
0505 /*  B2_I2C_DATA 0x015c  (ML)    32 bit  I2C Data Register */
0506
0507 /*  B4_R1_D     4*32 bit current receive Descriptor (q1) */
0508 /*  B4_R1_DA    32 bit current rec desc address     (q1) */
0509 /*  B4_R1_AC    32 bit current receive Address Count    (q1) */
0510 /*  B4_R1_BC    32 bit current receive Byte Counter (q1) */
0511 /*  B4_R1_CSR   32 bit BMU Control/Status Register  (q1) */
0512 /*  B4_R1_F     32 bit flag register            (q1) */
0513 /*  B4_R1_T1    32 bit Test Register 1          (q1) */
0514 /*  B4_R1_T2    32 bit Test Register 2          (q1) */
0515 /*  B4_R1_T3    32 bit Test Register 3          (q1) */
0516 /*  B4_R2_D     4*32 bit current receive Descriptor (q2) */
0517 /*  B4_R2_DA    32 bit current rec desc address     (q2) */
0518 /*  B4_R2_AC    32 bit current receive Address Count    (q2) */
0519 /*  B4_R2_BC    32 bit current receive Byte Counter (q2) */
0520 /*  B4_R2_CSR   32 bit BMU Control/Status Register  (q2) */
0521 /*  B4_R2_F     32 bit flag register            (q2) */
0522 /*  B4_R2_T1    32 bit Test Register 1          (q2) */
0523 /*  B4_R2_T2    32 bit Test Register 2          (q2) */
0524 /*  B4_R2_T3    32 bit Test Register 3          (q2) */
0525 /*  B5_XA_D     4*32 bit current receive Descriptor (xa) */
0526 /*  B5_XA_DA    32 bit current rec desc address     (xa) */
0527 /*  B5_XA_AC    32 bit current receive Address Count    (xa) */
0528 /*  B5_XA_BC    32 bit current receive Byte Counter (xa) */
0529 /*  B5_XA_CSR   32 bit BMU Control/Status Register  (xa) */
0530 /*  B5_XA_F     32 bit flag register            (xa) */
0531 /*  B5_XA_T1    32 bit Test Register 1          (xa) */
0532 /*  B5_XA_T2    32 bit Test Register 2          (xa) */
0533 /*  B5_XA_T3    32 bit Test Register 3          (xa) */
0534 /*  B5_XS_D     4*32 bit current receive Descriptor (xs) */
0535 /*  B5_XS_DA    32 bit current rec desc address     (xs) */
0536 /*  B5_XS_AC    32 bit current receive Address Count    (xs) */
0537 /*  B5_XS_BC    32 bit current receive Byte Counter (xs) */
0538 /*  B5_XS_CSR   32 bit BMU Control/Status Register  (xs) */
0539 /*  B5_XS_F     32 bit flag register            (xs) */
0540 /*  B5_XS_T1    32 bit Test Register 1          (xs) */
0541 /*  B5_XS_T2    32 bit Test Register 2          (xs) */
0542 /*  B5_XS_T3    32 bit Test Register 3          (xs) */
0543 /*  B5_<xx>_CSR 32 bit BMU Control/Status Register  (xx) */
0544 #define CSR_DESC_CLEAR  (1L<<21)    /* Bit 21:  Clear Reset for Descr */
0545 #define CSR_DESC_SET    (1L<<20)    /* Bit 20:  Set Reset for Descr */
0546 #define CSR_FIFO_CLEAR  (1L<<19)    /* Bit 19:  Clear Reset for FIFO */
0547 #define CSR_FIFO_SET    (1L<<18)    /* Bit 18:  Set Reset for FIFO */
0548 #define CSR_HPI_RUN (1L<<17)    /* Bit 17:  Release HPI SM */
0549 #define CSR_HPI_RST (1L<<16)    /* Bit 16:  Reset HPI SM to Idle */
0550 #define CSR_SV_RUN  (1L<<15)    /* Bit 15:  Release Supervisor SM */
0551 #define CSR_SV_RST  (1L<<14)    /* Bit 14:  Reset Supervisor SM */
0552 #define CSR_DREAD_RUN   (1L<<13)    /* Bit 13:  Release Descr Read SM */
0553 #define CSR_DREAD_RST   (1L<<12)    /* Bit 12:  Reset Descr Read SM */
0554 #define CSR_DWRITE_RUN  (1L<<11)    /* Bit 11:  Rel. Descr Write SM */
0555 #define CSR_DWRITE_RST  (1L<<10)    /* Bit 10:  Reset Descr Write SM */
0556 #define CSR_TRANS_RUN   (1L<<9)     /* Bit 9:   Release Transfer SM */
0557 #define CSR_TRANS_RST   (1L<<8)     /* Bit 8:   Reset Transfer SM */
0558                     /* Bit 7..5: reserved */
0559 #define CSR_START   (1L<<4)     /* Bit 4:   Start Rec/Xmit Queue */
0560 #define CSR_IRQ_CL_P    (1L<<3)     /* Bit 3:   Clear Parity IRQ, Rcv */
0561 #define CSR_IRQ_CL_B    (1L<<2)     /* Bit 2:   Clear EOB IRQ */
0562 #define CSR_IRQ_CL_F    (1L<<1)     /* Bit 1:   Clear EOF IRQ */
0563 #define CSR_IRQ_CL_C    (1L<<0)     /* Bit 0:   Clear ERR IRQ */
0564
0565 #define CSR_SET_RESET   (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\
0566             CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST)
0567 #define CSR_CLR_RESET   (CSR_DESC_CLEAR|CSR_FIFO_CLEAR|CSR_HPI_RUN|CSR_SV_RUN|\
0568             CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN)
0569
0570
0571 /*  B5_<xx>_F   32 bit flag register         (xx) */
0572                     /* Bit 28..31:  reserved          */
0573 #define F_ALM_FULL  (1L<<27)    /* Bit 27: (ML) FIFO almost full      */
0574 #define F_FIFO_EOF  (1L<<26)    /* Bit 26: (ML) Fag bit in FIFO       */
0575 #define F_WM_REACHED    (1L<<25)    /* Bit 25: (ML) Watermark reached     */
0576 #define F_UP_DW_USED    (1L<<24)    /* Bit 24: (ML) Upper Dword used (bug)*/
0577                     /* Bit 23:  reserved          */
0578 #define F_FIFO_LEVEL    (0x1fL<<16) /* Bit 16..22:(ML) # of Qwords in FIFO*/
0579                     /* Bit  8..15:  reserved          */
0580 #define F_ML_WATER_M    0x0000ffL   /* Bit  0.. 7:(ML) Watermark          */
0581 #define FLAG_WATER  0x00001fL   /* Bit 4..0:(DV) Level of req data tr.*/
0582
0583 /*  B5_<xx>_T1  32 bit Test Register 1       (xx) */
0584 /*      Holds four State Machine control Bytes */
0585 #define SM_CRTL_SV  (0xffL<<24) /* Bit 31..24:  Control Supervisor SM */
0586 #define SM_CRTL_RD  (0xffL<<16) /* Bit 23..16:  Control Read Desc SM */
0587 #define SM_CRTL_WR  (0xffL<<8)  /* Bit 15..8:   Control Write Desc SM */
0588 #define SM_CRTL_TR  (0xffL<<0)  /* Bit 7..0:    Control Transfer SM */
0589
0590 /*  B4_<xx>_T1_TR   8 bit Test Register 1 TR        (xx) */
0591 /*  B4_<xx>_T1_WR   8 bit Test Register 1 WR        (xx) */
0592 /*  B4_<xx>_T1_RD   8 bit Test Register 1 RD        (xx) */
0593 /*  B4_<xx>_T1_SV   8 bit Test Register 1 SV        (xx) */
0594 /* The control status byte of each machine looks like ... */
0595 #define SM_STATE    0xf0    /* Bit 7..4:    State which shall be loaded */
0596 #define SM_LOAD     0x08    /* Bit 3:   Load the SM with SM_STATE */
0597 #define SM_TEST_ON  0x04    /* Bit 2:   Switch on SM Test Mode */
0598 #define SM_TEST_OFF 0x02    /* Bit 1:   Go off the Test Mode */
0599 #define SM_STEP     0x01    /* Bit 0:   Step the State Machine */
0600
0601 /* The coding of the states */
0602 #define SM_SV_IDLE  0x0 /* Supervisor   Idle        Tr/Re        */
0603 #define SM_SV_RES_START 0x1 /* Supervisor   Res_Start   Tr/Re        */
0604 #define SM_SV_GET_DESC  0x3 /* Supervisor   Get_Desc    Tr/Re        */
0605 #define SM_SV_CHECK 0x2 /* Supervisor   Check       Tr/Re        */
0606 #define SM_SV_MOV_DATA  0x6 /* Supervisor   Move_Data   Tr/Re        */
0607 #define SM_SV_PUT_DESC  0x7 /* Supervisor   Put_Desc    Tr/Re        */
0608 #define SM_SV_SET_IRQ   0x5 /* Supervisor   Set_Irq     Tr/Re        */
0609
0610 #define SM_RD_IDLE  0x0 /* Read Desc.   Idle        Tr/Re        */
0611 #define SM_RD_LOAD  0x1 /* Read Desc.   Load        Tr/Re        */
0612 #define SM_RD_WAIT_TC   0x3 /* Read Desc.   Wait_TC     Tr/Re        */
0613 #define SM_RD_RST_EOF   0x6 /* Read Desc.   Reset_EOF      Re        */
0614 #define SM_RD_WDONE_R   0x2 /* Read Desc.   Wait_Done      Re        */
0615 #define SM_RD_WDONE_T   0x4 /* Read Desc.   Wait_Done   Tr           */
0616
0617 #define SM_TR_IDLE  0x0 /* Trans. Data  Idle        Tr/Re        */
0618 #define SM_TR_LOAD  0x3 /* Trans. Data  Load        Tr/Re        */
0619 #define SM_TR_LOAD_R_ML 0x1 /* Trans. Data  Load          /Re   (ML) */
0620 #define SM_TR_WAIT_TC   0x2 /* Trans. Data  Wait_TC     Tr/Re        */
0621 #define SM_TR_WDONE 0x4 /* Trans. Data  Wait_Done   Tr/Re        */
0622
0623 #define SM_WR_IDLE  0x0 /* Write Desc.  Idle        Tr/Re        */
0624 #define SM_WR_ABLEN 0x1 /* Write Desc.  Act_Buf_Length  Tr/Re        */
0625 #define SM_WR_LD_A4 0x2 /* Write Desc.  Load_A4        Re        */
0626 #define SM_WR_RES_OWN   0x2 /* Write Desc.  Res_OWN     Tr           */
0627 #define SM_WR_WAIT_EOF  0x3 /* Write Desc.  Wait_EOF       Re        */
0628 #define SM_WR_LD_N2C_R  0x4 /* Write Desc.  Load_N2C       Re        */
0629 #define SM_WR_WAIT_TC_R 0x5 /* Write Desc.  Wait_TC        Re        */
0630 #define SM_WR_WAIT_TC4  0x6 /* Write Desc.  Wait_TC4       Re        */
0631 #define SM_WR_LD_A_T    0x6 /* Write Desc.  Load_A      Tr           */
0632 #define SM_WR_LD_A_R    0x7 /* Write Desc.  Load_A         Re        */
0633 #define SM_WR_WAIT_TC_T 0x7 /* Write Desc.  Wait_TC     Tr           */
0634 #define SM_WR_LD_N2C_T  0xc /* Write Desc.  Load_N2C    Tr           */
0635 #define SM_WR_WDONE_T   0x9 /* Write Desc.  Wait_Done   Tr           */
0636 #define SM_WR_WDONE_R   0xc /* Write Desc.  Wait_Done      Re        */
0637 #define SM_WR_LD_D_AD   0xe /* Write Desc.  Load_Dumr_A    Re   (ML) */
0638 #define SM_WR_WAIT_D_TC 0xf /* Write Desc.  Wait_Dumr_TC       Re   (ML) */
0639
0640 /*  B5_<xx>_T2  32 bit Test Register 2       (xx) */
0641 /* Note: This register is only defined for the transmit queues */
0642                 /* Bit 31..8:   reserved */
0643 #define AC_TEST_ON  (1<<7)  /* Bit 7:   Address Counter Test Mode on */
0644 #define AC_TEST_OFF (1<<6)  /* Bit 6:   Address Counter Test Mode off*/
0645 #define BC_TEST_ON  (1<<5)  /* Bit 5:   Byte Counter Test Mode on */
0646 #define BC_TEST_OFF (1<<4)  /* Bit 4:   Byte Counter Test Mode off */
0647 #define TEST_STEP04 (1<<3)  /* Bit 3:   Inc AC/Dec BC by 4 */
0648 #define TEST_STEP03 (1<<2)  /* Bit 2:   Inc AC/Dec BC by 3 */
0649 #define TEST_STEP02 (1<<1)  /* Bit 1:   Inc AC/Dec BC by 2 */
0650 #define TEST_STEP01 (1<<0)  /* Bit 0:   Inc AC/Dec BC by 1 */
0651
0652 /*  B5_<xx>_T3  32 bit Test Register 3       (xx) */
0653 /* Note: This register is only defined for the transmit queues */
0654                 /* Bit 31..8:   reserved */
0655 #define T3_MUX_2    (1<<7)  /* Bit 7: (ML)  Mux position MSB */
0656 #define T3_VRAM_2   (1<<6)  /* Bit 6: (ML)  Virtual RAM buffer addr MSB */
0657 #define T3_LOOP     (1<<5)  /* Bit 5:   Set Loopback (Xmit) */
0658 #define T3_UNLOOP   (1<<4)  /* Bit 4:   Unset Loopback (Xmit) */
0659 #define T3_MUX      (3<<2)  /* Bit 3..2:    Mux position */
0660 #define T3_VRAM     (3<<0)  /* Bit 1..0:    Virtual RAM buffer Address */
0661
0662
0663 /*
0664  * address transmission from logical to physical offset address on board
0665  */
0666 #define FMA(a)  (0x0400|((a)<<2))   /* FORMAC+ (r/w) (SN3) */
0667 #define P1(a)   (0x0380|((a)<<2))   /* PLC1 (r/w) (DAS) */
0668 #define P2(a)   (0x0600|((a)<<2))   /* PLC2 (r/w) (covered by the SN3) */
0669 #define PRA(a)  (B2_MAC_0 + (a))    /* configuration PROM (MAC address) */
0670
0671 /*
0672  * FlashProm specification
0673  */
0674 #define MAX_PAGES   0x20000L    /* Every byte has a single page */
0675 #define MAX_FADDR   1       /* 1 byte per page */
0676
0677 /*
0678  * Receive / Transmit Buffer Control word
0679  */
0680 #define BMU_OWN     (1UL<<31)   /* OWN bit: 0 == host, 1 == adapter */
0681 #define BMU_STF     (1L<<30)    /* Start of Frame ?     */
0682 #define BMU_EOF     (1L<<29)    /* End of Frame ?       */
0683 #define BMU_EN_IRQ_EOB  (1L<<28)    /* Enable "End of Buffer" IRQ   */
0684 #define BMU_EN_IRQ_EOF  (1L<<27)    /* Enable "End of Frame" IRQ    */
0685 #define BMU_DEV_0   (1L<<26)    /* RX: don't transfer to system mem */
0686 #define BMU_SMT_TX  (1L<<25)    /* TX: if set, buffer type SMT_MBuf */
0687 #define BMU_ST_BUF  (1L<<25)    /* RX: copy of start of frame */
0688 #define BMU_UNUSED  (1L<<24)    /* Set if the Descr is curr unused */
0689 #define BMU_SW      (3L<<24)    /* 2 Bits reserved for SW usage */
0690 #define BMU_CHECK   0x00550000L /* To identify the control word */
0691 #define BMU_BBC     0x0000FFFFL /* R/T Buffer Byte Count        */
0692
0693 /*
0694  * physical address offset + IO-Port base address
0695  */
0696 #ifdef MEM_MAPPED_IO
0697 #define ADDR(a)     (char far *) smc->hw.iop+(a)
0698 #define ADDRS(smc,a)    (char far *) (smc)->hw.iop+(a)
0699 #else
0700 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
0701     (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
0702     (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
0703 #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
0704     ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
0705     ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
0706 #endif
0707
0708 /*
0709  * Define a macro to access the configuration space
0710  */
0711 #define PCI_C(a)    ADDR(B3_CFG_SPC + (a))  /* PCI Config Space */
0712
0713 #define EXT_R(a)    ADDR(B6_EXT_REG + (a))  /* External Registers */
0714
0715 /*
0716  * Define some values needed for the MAC address (PROM)
0717  */
0718 #define SA_MAC      (0) /* start addr. MAC_AD within the PROM */
0719 #define PRA_OFF     (0) /* offset correction when 4th byte reading */
0720
0721 #define SKFDDI_PSZ  8   /* address PROM size */
0722
0723 #define FM_A(a) ADDR(FMA(a))    /* FORMAC Plus physical addr */
0724 #define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */
0725 #define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */
0726 #define PR_A(a) ADDR(PRA(a))    /* config. PROM (MAC address) */
0727
0728 /*
0729  * Macro to read the PROM
0730  */
0731 #define READ_PROM(a)    ((u_char)inp(a))
0732
0733 #define GET_PAGE(bank)  outpd(ADDR(B2_FAR),bank)
0734 #define VPP_ON()
0735 #define VPP_OFF()
0736
0737 /*
0738  * Note: Values of the Interrupt Source Register are defined above
0739  */
0740 #define ISR_A       ADDR(B0_ISRC)
0741 #define GET_ISR()       inpd(ISR_A)
0742 #define GET_ISR_SMP(iop)    inpd((iop)+B0_ISRC)
0743 #define CHECK_ISR()     (inpd(ISR_A) & inpd(ADDR(B0_IMSK)))
0744 #define CHECK_ISR_SMP(iop)  (inpd((iop)+B0_ISRC) & inpd((iop)+B0_IMSK))
0745
0746 #define BUS_CHECK()
0747
0748 /*
0749  * CLI_FBI: Disable Board Interrupts
0750  * STI_FBI: Enable Board Interrupts
0751  */
0752 #ifndef UNIX
0753 #define CLI_FBI()   outpd(ADDR(B0_IMSK),0)
0754 #else
0755 #define CLI_FBI(smc)    outpd(ADDRS((smc),B0_IMSK),0)
0756 #endif
0757
0758 #ifndef UNIX
0759 #define STI_FBI()   outpd(ADDR(B0_IMSK),smc->hw.is_imask)
0760 #else
0761 #define STI_FBI(smc)    outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
0762 #endif
0763
0764 #define CLI_FBI_SMP(iop)    outpd((iop)+B0_IMSK,0)
0765 #define STI_FBI_SMP(smc,iop)    outpd((iop)+B0_IMSK,(smc)->hw.is_imask)
0766
0767 #endif  /* PCI */
0768 /*--------------------------------------------------------------------------*/
0769
0770 /*
0771  * 12 bit transfer (dword) counter:
0772  *  (ISA:   2*trc = number of byte)
0773  *  (EISA:  4*trc = number of byte)
0774  *  (MCA:   4*trc = number of byte)
0775  */
0776 #define MAX_TRANS   (0x0fff)
0777
0778 /*
0779  * PC PIC
0780  */
0781 #define MST_8259 (0x20)
0782 #define SLV_8259 (0xA0)
0783
0784 #define TPS     (18)        /* ticks per second */
0785
0786 /*
0787  * error timer defs
0788  */
0789 #define TN      (4) /* number of supported timer = TN+1 */
0790 #define SNPPND_TIME (5) /* buffer memory access over mem. data reg. */
0791
0792 #define MAC_AD  0x405a0000
0793
0794 #define MODR1   FM_A(FM_MDREG1) /* mode register 1 */
0795 #define MODR2   FM_A(FM_MDREG2) /* mode register 2 */
0796
0797 #define CMDR1   FM_A(FM_CMDREG1)    /* command register 1 */
0798 #define CMDR2   FM_A(FM_CMDREG2)    /* command register 2 */
0799
0800
0801 /*
0802  * function defines
0803  */
0804 #define CLEAR(io,mask)      outpw((io),inpw(io)&(~(mask)))
0805 #define SET(io,mask)        outpw((io),inpw(io)|(mask))
0806 #define GET(io,mask)        (inpw(io)&(mask))
0807 #define SETMASK(io,val,mask)    outpw((io),(inpw(io) & ~(mask)) | (val))
0808
0809 /*
0810  * PHY Port A (PA) = PLC 1
0811  * With SuperNet 3 PHY-A and PHY S are identical.
0812  */
0813 #define PLC(np,reg) (((np) == PA) ? P2_A(reg) : P1_A(reg))
0814
0815 /*
0816  * set memory address register for write and read
0817  */
0818 #define MARW(ma)    outpw(FM_A(FM_MARW),(unsigned int)(ma))
0819 #define MARR(ma)    outpw(FM_A(FM_MARR),(unsigned int)(ma))
0820
0821 /*
0822  * read/write from/to memory data register
0823  */
0824 /* write double word */
0825 #define MDRW(dd)    outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\
0826             outpw(FM_A(FM_MDRL),(unsigned int)(dd))
0827
0828 #ifndef WINNT
0829 /* read double word */
0830 #define MDRR()      (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL)))
0831
0832 /* read FORMAC+ 32-bit status register */
0833 #define GET_ST1()   (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L)))
0834 #define GET_ST2()   (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L)))
0835 #ifdef  SUPERNET_3
0836 #define GET_ST3()   (((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L)))
0837 #endif
0838 #else
0839 /* read double word */
0840 #define MDRR()      inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL)))
0841
0842 /* read FORMAC+ 32-bit status register */
0843 #define GET_ST1()   inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L)))
0844 #define GET_ST2()   inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L)))
0845 #ifdef  SUPERNET_3
0846 #define GET_ST3()   inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L)))
0847 #endif
0848 #endif
0849
0850 /* Special timer macro for 82c54 */
0851                 /* timer access over data bus bit 8..15 */
0852 #define OUT_82c54_TIMER(port,val)   outpw(TI_A(port),(val)<<8)
0853 #define IN_82c54_TIMER(port)        ((inpw(TI_A(port))>>8) & 0xff)
0854
0855
0856 #ifdef  DEBUG
0857 #define DB_MAC(mac,st) {if (debug_mac & 0x1)\
0858                 printf("M") ;\
0859             if (debug_mac & 0x2)\
0860                 printf("\tMAC %d status 0x%08lx\n",mac,st) ;\
0861             if (debug_mac & 0x4)\
0862                 dp_mac(mac,st) ;\
0863 }
0864
0865 #define DB_PLC(p,iev) { if (debug_plc & 0x1)\
0866                 printf("P") ;\
0867             if (debug_plc & 0x2)\
0868                 printf("\tPLC %s Int 0x%04x\n", \
0869                     (p == PA) ? "A" : "B", iev) ;\
0870             if (debug_plc & 0x4)\
0871                 dp_plc(p,iev) ;\
0872 }
0873
0874 #define DB_TIMER() {    if (debug_timer & 0x1)\
0875                 printf("T") ;\
0876             if (debug_timer & 0x2)\
0877                 printf("\tTimer ISR\n") ;\
0878 }
0879
0880 #else   /* no DEBUG */
0881
0882 #define DB_MAC(mac,st)
0883 #define DB_PLC(p,iev)
0884 #define DB_TIMER()
0885
0886 #endif  /* no DEBUG */
0887
0888 #define INC_PTR(sp,cp,ep)   if (++cp == ep) cp = sp
0889 /*
0890  * timer defs
0891  */
0892 #define COUNT(t)    ((t)<<6)    /* counter */
0893 #define RW_OP(o)    ((o)<<4)    /* read/write operation */
0894 #define TMODE(m)    ((m)<<1)    /* timer mode */
0895
0896 #endif