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0011 #ifndef _HWM_
0012 #define _HWM_
0013
0014 #include "mbuf.h"
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0029 #ifndef DRV_BUF_FLUSH
0030 #define DRV_BUF_FLUSH(desc,flag)
0031 #define DDI_DMA_SYNC_FORCPU
0032 #define DDI_DMA_SYNC_FORDEV
0033 #endif
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0035
0036
0037
0038 #define RX_ENABLE_PASS_SMT 21
0039 #define RX_DISABLE_PASS_SMT 22
0040 #define RX_ENABLE_PASS_NSA 23
0041 #define RX_DISABLE_PASS_NSA 24
0042 #define RX_ENABLE_PASS_DB 25
0043 #define RX_DISABLE_PASS_DB 26
0044 #define RX_DISABLE_PASS_ALL 27
0045 #define RX_DISABLE_LLC_PROMISC 28
0046 #define RX_ENABLE_LLC_PROMISC 29
0047
0048
0049 #ifndef DMA_RD
0050 #define DMA_RD 1
0051 #endif
0052 #ifndef DMA_WR
0053 #define DMA_WR 2
0054 #endif
0055 #define SMT_BUF 0x80
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0059
0060 #define EN_IRQ_EOF 0x02
0061 #define LOC_TX 0x04
0062 #define LAST_FRAG 0x08
0063 #define FIRST_FRAG 0x10
0064 #define LAN_TX 0x20
0065 #define RING_DOWN 0x40
0066 #define OUT_OF_TXD 0x80
0067
0068
0069 #ifndef NULL
0070 #define NULL 0
0071 #endif
0072
0073 #define C_INDIC (1L<<25)
0074 #define A_INDIC (1L<<26)
0075 #define RD_FS_LOCAL 0x80
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0080 #define DEBUG_SMTF 1
0081 #define DEBUG_SMT 2
0082 #define DEBUG_ECM 3
0083 #define DEBUG_RMT 4
0084 #define DEBUG_CFM 5
0085 #define DEBUG_PCM 6
0086 #define DEBUG_SBA 7
0087 #define DEBUG_ESS 8
0088
0089 #define DB_HWM_RX 10
0090 #define DB_HWM_TX 11
0091 #define DB_HWM_GEN 12
0092
0093 struct s_mbuf_pool {
0094 #ifndef MB_OUTSIDE_SMC
0095 SMbuf mb[MAX_MBUF] ;
0096 #endif
0097 SMbuf *mb_start ;
0098 SMbuf *mb_free ;
0099 } ;
0100
0101 struct hwm_r {
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0105 u_int len ;
0106 char *mb_pos ;
0107 } ;
0108
0109 struct hw_modul {
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0113 struct s_mbuf_pool mbuf_pool ;
0114 struct hwm_r r ;
0115
0116 union s_fp_descr volatile *descr_p ;
0117
0118 u_short pass_SMT ;
0119 u_short pass_NSA ;
0120 u_short pass_DB ;
0121 u_short pass_llc_promisc ;
0122
0123 SMbuf *llc_rx_pipe ;
0124 SMbuf *llc_rx_tail ;
0125 int queued_rx_frames ;
0126
0127 SMbuf *txd_tx_pipe ;
0128 SMbuf *txd_tx_tail ;
0129 int queued_txd_mb ;
0130
0131 int rx_break ;
0132 int leave_isr ;
0133 int isr_flag ;
0134
0135
0136
0137 struct s_smt_tx_queue *tx_p ;
0138 u_long tx_descr ;
0139 int tx_len ;
0140 SMbuf *tx_mb ;
0141 char *tx_data ;
0142
0143 int detec_count ;
0144 u_long rx_len_error ;
0145 } ;
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0151
0152 #ifdef DEBUG
0153 struct os_debug {
0154 int hwm_rx ;
0155 int hwm_tx ;
0156 int hwm_gen ;
0157 } ;
0158 #endif
0159
0160 #ifdef DEBUG
0161 #ifdef DEBUG_BRD
0162 #define DB_P smc->debug
0163 #else
0164 #define DB_P debug
0165 #endif
0166
0167 #define DB_RX(lev, fmt, ...) \
0168 do { \
0169 if (DB_P.d_os.hwm_rx >= (lev)) \
0170 printf(fmt "\n", ##__VA_ARGS__); \
0171 } while (0)
0172 #define DB_TX(lev, fmt, ...) \
0173 do { \
0174 if (DB_P.d_os.hwm_tx >= (lev)) \
0175 printf(fmt "\n", ##__VA_ARGS__); \
0176 } while (0)
0177 #define DB_GEN(lev, fmt, ...) \
0178 do { \
0179 if (DB_P.d_os.hwm_gen >= (lev)) \
0180 printf(fmt "\n", ##__VA_ARGS__); \
0181 } while (0)
0182 #else
0183 #define DB_RX(lev, fmt, ...) no_printk(fmt "\n", ##__VA_ARGS__)
0184 #define DB_TX(lev, fmt, ...) no_printk(fmt "\n", ##__VA_ARGS__)
0185 #define DB_GEN(lev, fmt, ...) no_printk(fmt "\n", ##__VA_ARGS__)
0186 #endif
0187
0188 #ifndef SK_BREAK
0189 #define SK_BREAK()
0190 #endif
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0209 #define HWM_GET_TX_PHYS(txd) (u_long)AIX_REVERSE((txd)->txd_tbadr)
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0225 #define HWM_GET_TX_LEN(txd) ((int)AIX_REVERSE((txd)->txd_tbctrl)& RD_LENGTH)
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0242 #define HWM_GET_TX_USED(smc,queue) (int) (smc)->hw.fp.tx_q[queue].tx_used
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0260 #define HWM_GET_CURR_TXD(smc,queue) (struct s_smt_fp_txd volatile *)\
0261 (smc)->hw.fp.tx_q[queue].tx_curr_put
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0277 #define HWM_GET_RX_FRAG_LEN(rxd) ((int)AIX_REVERSE((rxd)->rxd_rbctrl)& \
0278 RD_LENGTH)
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0294 #define HWM_GET_RX_PHYS(rxd) (u_long)AIX_REVERSE((rxd)->rxd_rbadr)
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0311 #define HWM_GET_RX_USED(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_used)
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0325 #define HWM_GET_RX_FREE(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_free-1)
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0340 #define HWM_GET_CURR_RXD(smc) (struct s_smt_fp_rxd volatile *)\
0341 (smc)->hw.fp.rx_q[QUEUE_R1].rx_curr_put
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0357 #ifndef HWM_NO_FLOW_CTL
0358 #define HWM_RX_CHECK(smc,low_water) {\
0359 if ((low_water) >= (smc)->hw.fp.rx_q[QUEUE_R1].rx_used) {\
0360 mac_drv_fill_rxd(smc) ;\
0361 }\
0362 }
0363 #else
0364 #define HWM_RX_CHECK(smc,low_water) mac_drv_fill_rxd(smc)
0365 #endif
0366
0367 #ifndef HWM_EBASE
0368 #define HWM_EBASE 500
0369 #endif
0370
0371 #define HWM_E0001 HWM_EBASE + 1
0372 #define HWM_E0001_MSG "HWM: Wrong size of s_rxd_os struct"
0373 #define HWM_E0002 HWM_EBASE + 2
0374 #define HWM_E0002_MSG "HWM: Wrong size of s_txd_os struct"
0375 #define HWM_E0003 HWM_EBASE + 3
0376 #define HWM_E0003_MSG "HWM: smt_free_mbuf() called with NULL pointer"
0377 #define HWM_E0004 HWM_EBASE + 4
0378 #define HWM_E0004_MSG "HWM: Parity error rx queue 1"
0379 #define HWM_E0005 HWM_EBASE + 5
0380 #define HWM_E0005_MSG "HWM: Encoding error rx queue 1"
0381 #define HWM_E0006 HWM_EBASE + 6
0382 #define HWM_E0006_MSG "HWM: Encoding error async tx queue"
0383 #define HWM_E0007 HWM_EBASE + 7
0384 #define HWM_E0007_MSG "HWM: Encoding error sync tx queue"
0385 #define HWM_E0008 HWM_EBASE + 8
0386 #define HWM_E0008_MSG ""
0387 #define HWM_E0009 HWM_EBASE + 9
0388 #define HWM_E0009_MSG "HWM: Out of RxD condition detected"
0389 #define HWM_E0010 HWM_EBASE + 10
0390 #define HWM_E0010_MSG "HWM: A protocol layer has tried to send a frame with an invalid frame control"
0391 #define HWM_E0011 HWM_EBASE + 11
0392 #define HWM_E0011_MSG "HWM: mac_drv_clear_tx_queue was called although the hardware wasn't stopped"
0393 #define HWM_E0012 HWM_EBASE + 12
0394 #define HWM_E0012_MSG "HWM: mac_drv_clear_rx_queue was called although the hardware wasn't stopped"
0395 #define HWM_E0013 HWM_EBASE + 13
0396 #define HWM_E0013_MSG "HWM: mac_drv_repair_descr was called although the hardware wasn't stopped"
0397
0398 #endif