skfp/h/fplustm.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /******************************************************************************
0003  *
0004  *  (C)Copyright 1998,1999 SysKonnect,
0005  *  a business unit of Schneider & Koch & Co. Datensysteme GmbH.
0006  *
0007  *  The information in this file is provided "AS IS" without warranty.
0008  *
0009  ******************************************************************************/
0010
0011 /*
0012  *  AMD Fplus in tag mode data structs
0013  *  defs for fplustm.c
0014  */
0015
0016 #ifndef _FPLUS_
0017 #define _FPLUS_
0018
0019 #ifndef HW_PTR
0020 #define HW_PTR  void __iomem *
0021 #endif
0022
0023 /*
0024  * fplus error statistic structure
0025  */
0026 struct err_st {
0027     u_long err_valid ;      /* memory status valid */
0028     u_long err_abort ;      /* memory status receive abort */
0029     u_long err_e_indicator ;    /* error indicator */
0030     u_long err_crc ;        /* error detected (CRC or length) */
0031     u_long err_llc_frame ;      /* LLC frame */
0032     u_long err_mac_frame ;      /* MAC frame */
0033     u_long err_smt_frame ;      /* SMT frame */
0034     u_long err_imp_frame ;      /* implementer frame */
0035     u_long err_no_buf ;     /* no buffer available */
0036     u_long err_too_long ;       /* longer than max. buffer */
0037     u_long err_bec_stat ;       /* beacon state entered */
0038     u_long err_clm_stat ;       /* claim state entered */
0039     u_long err_sifg_det ;       /* short interframe gap detect */
0040     u_long err_phinv ;      /* PHY invalid */
0041     u_long err_tkiss ;      /* token issued */
0042     u_long err_tkerr ;      /* token error */
0043 } ;
0044
0045 /*
0046  *  Transmit Descriptor struct
0047  */
0048 struct s_smt_fp_txd {
0049     __le32 txd_tbctrl ;     /* transmit buffer control */
0050     __le32 txd_txdscr ;     /* transmit frame status word */
0051     __le32 txd_tbadr ;      /* physical tx buffer address */
0052     __le32 txd_ntdadr ;     /* physical pointer to the next TxD */
0053 #ifdef  ENA_64BIT_SUP
0054     __le32 txd_tbadr_hi ;       /* physical tx buffer addr (high dword)*/
0055 #endif
0056     char far *txd_virt ;        /* virtual pointer to the data frag */
0057                     /* virt pointer to the next TxD */
0058     struct s_smt_fp_txd volatile far *txd_next ;
0059     struct s_txd_os txd_os ;    /* OS - specific struct */
0060 } ;
0061
0062 /*
0063  *  Receive Descriptor struct
0064  */
0065 struct s_smt_fp_rxd {
0066     __le32 rxd_rbctrl ;     /* receive buffer control */
0067     __le32 rxd_rfsw ;       /* receive frame status word */
0068     __le32 rxd_rbadr ;      /* physical rx buffer address */
0069     __le32 rxd_nrdadr ;     /* physical pointer to the next RxD */
0070 #ifdef  ENA_64BIT_SUP
0071     __le32 rxd_rbadr_hi ;       /* physical tx buffer addr (high dword)*/
0072 #endif
0073     char far *rxd_virt ;        /* virtual pointer to the data frag */
0074                     /* virt pointer to the next RxD */
0075     struct s_smt_fp_rxd volatile far *rxd_next ;
0076     struct s_rxd_os rxd_os ;    /* OS - specific struct */
0077 } ;
0078
0079 /*
0080  *  Descriptor Union Definition
0081  */
0082 union s_fp_descr {
0083     struct  s_smt_fp_txd t ;        /* pointer to the TxD */
0084     struct  s_smt_fp_rxd r ;        /* pointer to the RxD */
0085 } ;
0086
0087 /*
0088  *  TxD Ring Control struct
0089  */
0090 struct s_smt_tx_queue {
0091     struct s_smt_fp_txd volatile *tx_curr_put ; /* next free TxD */
0092     struct s_smt_fp_txd volatile *tx_prev_put ; /* shadow put pointer */
0093     struct s_smt_fp_txd volatile *tx_curr_get ; /* next TxD to release*/
0094     u_short tx_free ;           /* count of free TxD's */
0095     u_short tx_used ;           /* count of used TxD's */
0096     HW_PTR tx_bmu_ctl ;         /* BMU addr for tx start */
0097     HW_PTR tx_bmu_dsc ;         /* BMU addr for curr dsc. */
0098 } ;
0099
0100 /*
0101  *  RxD Ring Control struct
0102  */
0103 struct s_smt_rx_queue {
0104     struct s_smt_fp_rxd volatile *rx_curr_put ; /* next RxD to queue into */
0105     struct s_smt_fp_rxd volatile *rx_prev_put ; /* shadow put pointer */
0106     struct s_smt_fp_rxd volatile *rx_curr_get ; /* next RxD to fill */
0107     u_short rx_free ;           /* count of free RxD's */
0108     u_short rx_used ;           /* count of used RxD's */
0109     HW_PTR rx_bmu_ctl ;         /* BMU addr for rx start */
0110     HW_PTR rx_bmu_dsc ;         /* BMU addr for curr dsc. */
0111 } ;
0112
0113 #define VOID_FRAME_OFF      0x00
0114 #define CLAIM_FRAME_OFF     0x08
0115 #define BEACON_FRAME_OFF    0x10
0116 #define DBEACON_FRAME_OFF   0x18
0117 #define RX_FIFO_OFF     0x21        /* to get a prime number for */
0118                         /* the RX_FIFO_SPACE */
0119
0120 #define RBC_MEM_SIZE        0x8000
0121 #define SEND_ASYNC_AS_SYNC  0x1
0122 #define SYNC_TRAFFIC_ON     0x2
0123
0124 /* big FIFO memory */
0125 #define RX_FIFO_SPACE       0x4000 - RX_FIFO_OFF
0126 #define TX_FIFO_SPACE       0x4000
0127
0128 #define TX_SMALL_FIFO       0x0900
0129 #define TX_MEDIUM_FIFO      TX_FIFO_SPACE / 2
0130 #define TX_LARGE_FIFO       TX_FIFO_SPACE - TX_SMALL_FIFO
0131
0132 #define RX_SMALL_FIFO       0x0900
0133 #define RX_LARGE_FIFO       RX_FIFO_SPACE - RX_SMALL_FIFO
0134
0135 struct s_smt_fifo_conf {
0136     u_short rbc_ram_start ;     /* FIFO start address */
0137     u_short rbc_ram_end ;       /* FIFO size */
0138     u_short rx1_fifo_start ;    /* rx queue start address */
0139     u_short rx1_fifo_size ;     /* rx queue size */
0140     u_short rx2_fifo_start ;    /* rx queue start address */
0141     u_short rx2_fifo_size ;     /* rx queue size */
0142     u_short tx_s_start ;        /* sync queue start address */
0143     u_short tx_s_size ;     /* sync queue size */
0144     u_short tx_a0_start ;       /* async queue A0 start address */
0145     u_short tx_a0_size ;        /* async queue A0 size */
0146     u_short fifo_config_mode ;  /* FIFO configuration mode */
0147 } ;
0148
0149 #define FM_ADDRX    (FM_ADDET|FM_EXGPA0|FM_EXGPA1)
0150
0151 struct s_smt_fp {
0152     u_short mdr2init ;      /* mode register 2 init value */
0153     u_short mdr3init ;      /* mode register 3 init value */
0154     u_short frselreg_init ;     /* frame selection register init val */
0155     u_short rx_mode ;       /* address mode broad/multi/promisc */
0156     u_short nsa_mode ;
0157     u_short rx_prom ;
0158     u_short exgpa ;
0159
0160     struct err_st err_stats ;   /* error statistics */
0161
0162     /*
0163      * MAC buffers
0164      */
0165     struct fddi_mac_sf {        /* special frame build buffer */
0166         u_char          mac_fc ;
0167         struct fddi_addr    mac_dest ;
0168         struct fddi_addr    mac_source ;
0169         u_char          mac_info[0x20] ;
0170     } mac_sfb ;
0171
0172
0173     /*
0174      * queues
0175      */
0176 #define QUEUE_S         0
0177 #define QUEUE_A0        1
0178 #define QUEUE_R1        0
0179 #define QUEUE_R2        1
0180 #define USED_QUEUES     2
0181
0182     /*
0183      * queue pointers; points to the queue dependent variables
0184      */
0185     struct s_smt_tx_queue *tx[USED_QUEUES] ;
0186     struct s_smt_rx_queue *rx[USED_QUEUES] ;
0187
0188     /*
0189      * queue dependent variables
0190      */
0191     struct s_smt_tx_queue tx_q[USED_QUEUES] ;
0192     struct s_smt_rx_queue rx_q[USED_QUEUES] ;
0193
0194     /*
0195      * FIFO configuration struct
0196      */
0197     struct  s_smt_fifo_conf fifo ;
0198
0199     /* last formac status */
0200     u_short  s2u ;
0201     u_short  s2l ;
0202
0203     /* calculated FORMAC+ reg.addr. */
0204     HW_PTR  fm_st1u ;
0205     HW_PTR  fm_st1l ;
0206     HW_PTR  fm_st2u ;
0207     HW_PTR  fm_st2l ;
0208     HW_PTR  fm_st3u ;
0209     HW_PTR  fm_st3l ;
0210
0211
0212     /*
0213      * multicast table
0214      */
0215 #define FPMAX_MULTICAST 32
0216 #define SMT_MAX_MULTI   4
0217     struct {
0218         struct s_fpmc {
0219             struct fddi_addr    a ; /* mc address */
0220             u_char          n ; /* usage counter */
0221             u_char          perm ;  /* flag: permanent */
0222         } table[FPMAX_MULTICAST] ;
0223     } mc ;
0224     struct fddi_addr    group_addr ;
0225     u_long  func_addr ;     /* functional address */
0226     int smt_slots_used ;    /* count of table entries for the SMT */
0227     int os_slots_used ;     /* count of table entries */
0228                     /* used by the os-specific module */
0229 } ;
0230
0231 /*
0232  * modes for mac_set_rx_mode()
0233  */
0234 #define RX_ENABLE_ALLMULTI  1   /* enable all multicasts */
0235 #define RX_DISABLE_ALLMULTI 2   /* disable "enable all multicasts" */
0236 #define RX_ENABLE_PROMISC   3   /* enable promiscuous */
0237 #define RX_DISABLE_PROMISC  4   /* disable promiscuous */
0238 #define RX_ENABLE_NSA       5   /* enable reception of NSA frames */
0239 #define RX_DISABLE_NSA      6   /* disable reception of NSA frames */
0240
0241
0242 /*
0243  * support for byte reversal in AIX
0244  * (descriptors and pointers must be byte reversed in memory
0245  *  CPU is big endian; M-Channel is little endian)
0246  */
0247 #ifdef  AIX
0248 #define MDR_REV
0249 #define AIX_REVERSE(x)      ((((x)<<24L)&0xff000000L)   +   \
0250                  (((x)<< 8L)&0x00ff0000L)   +   \
0251                  (((x)>> 8L)&0x0000ff00L)   +   \
0252                  (((x)>>24L)&0x000000ffL))
0253 #else
0254 #ifndef AIX_REVERSE
0255 #define AIX_REVERSE(x)  (x)
0256 #endif
0257 #endif
0258
0259 #ifdef  MDR_REV
0260 #define MDR_REVERSE(x)      ((((x)<<24L)&0xff000000L)   +   \
0261                  (((x)<< 8L)&0x00ff0000L)   +   \
0262                  (((x)>> 8L)&0x0000ff00L)   +   \
0263                  (((x)>>24L)&0x000000ffL))
0264 #else
0265 #ifndef MDR_REVERSE
0266 #define MDR_REVERSE(x)  (x)
0267 #endif
0268 #endif
0269
0270 #endif