Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*  FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
0003  *
0004  *  Copyright (c) 2018  Maciej W. Rozycki
0005  *
0006  *  This program is free software; you can redistribute it and/or
0007  *  modify it under the terms of the GNU General Public License
0008  *  as published by the Free Software Foundation; either version
0009  *  2 of the License, or (at your option) any later version.
0010  *
0011  *  References:
0012  *
0013  *  Dave Sawyer & Phil Weeks & Frank Itkowsky,
0014  *  "DEC FDDIcontroller 700 Port Specification",
0015  *  Revision 1.1, Digital Equipment Corporation
0016  */
0017 
0018 /* ------------------------------------------------------------------------- */
0019 /* FZA configurable parameters.                                              */
0020 
0021 /* The number of transmit ring descriptors; either 0 for 512 or 1 for 1024.  */
0022 #define FZA_RING_TX_MODE 0
0023 
0024 /* The number of receive ring descriptors; from 2 up to 256.  */
0025 #define FZA_RING_RX_SIZE 256
0026 
0027 /* End of FZA configurable parameters.  No need to change anything below.    */
0028 /* ------------------------------------------------------------------------- */
0029 
0030 #include <linux/delay.h>
0031 #include <linux/device.h>
0032 #include <linux/dma-mapping.h>
0033 #include <linux/init.h>
0034 #include <linux/interrupt.h>
0035 #include <linux/io.h>
0036 #include <linux/io-64-nonatomic-lo-hi.h>
0037 #include <linux/ioport.h>
0038 #include <linux/kernel.h>
0039 #include <linux/list.h>
0040 #include <linux/module.h>
0041 #include <linux/netdevice.h>
0042 #include <linux/fddidevice.h>
0043 #include <linux/sched.h>
0044 #include <linux/skbuff.h>
0045 #include <linux/spinlock.h>
0046 #include <linux/stat.h>
0047 #include <linux/tc.h>
0048 #include <linux/timer.h>
0049 #include <linux/types.h>
0050 #include <linux/wait.h>
0051 
0052 #include <asm/barrier.h>
0053 
0054 #include "defza.h"
0055 
0056 #define DRV_NAME "defza"
0057 #define DRV_VERSION "v.1.1.4"
0058 #define DRV_RELDATE "Oct  6 2018"
0059 
0060 static const char version[] =
0061     DRV_NAME ": " DRV_VERSION "  " DRV_RELDATE "  Maciej W. Rozycki\n";
0062 
0063 MODULE_AUTHOR("Maciej W. Rozycki <macro@orcam.me.uk>");
0064 MODULE_DESCRIPTION("DEC FDDIcontroller 700 (DEFZA-xx) driver");
0065 MODULE_LICENSE("GPL");
0066 
0067 static int loopback;
0068 module_param(loopback, int, 0644);
0069 
0070 /* Ring Purger Multicast */
0071 static u8 hw_addr_purger[8] = { 0x09, 0x00, 0x2b, 0x02, 0x01, 0x05 };
0072 /* Directed Beacon Multicast */
0073 static u8 hw_addr_beacon[8] = { 0x01, 0x80, 0xc2, 0x00, 0x01, 0x00 };
0074 
0075 /* Shorthands for MMIO accesses that we require to be strongly ordered
0076  * WRT preceding MMIO accesses.
0077  */
0078 #define readw_o readw_relaxed
0079 #define readl_o readl_relaxed
0080 
0081 #define writew_o writew_relaxed
0082 #define writel_o writel_relaxed
0083 
0084 /* Shorthands for MMIO accesses that we are happy with being weakly ordered
0085  * WRT preceding MMIO accesses.
0086  */
0087 #define readw_u readw_relaxed
0088 #define readl_u readl_relaxed
0089 #define readq_u readq_relaxed
0090 
0091 #define writew_u writew_relaxed
0092 #define writel_u writel_relaxed
0093 #define writeq_u writeq_relaxed
0094 
0095 static inline struct sk_buff *fza_alloc_skb_irq(struct net_device *dev,
0096                         unsigned int length)
0097 {
0098     return __netdev_alloc_skb(dev, length, GFP_ATOMIC);
0099 }
0100 
0101 static inline struct sk_buff *fza_alloc_skb(struct net_device *dev,
0102                         unsigned int length)
0103 {
0104     return __netdev_alloc_skb(dev, length, GFP_KERNEL);
0105 }
0106 
0107 static inline void fza_skb_align(struct sk_buff *skb, unsigned int v)
0108 {
0109     unsigned long x, y;
0110 
0111     x = (unsigned long)skb->data;
0112     y = ALIGN(x, v);
0113 
0114     skb_reserve(skb, y - x);
0115 }
0116 
0117 static inline void fza_reads(const void __iomem *from, void *to,
0118                  unsigned long size)
0119 {
0120     if (sizeof(unsigned long) == 8) {
0121         const u64 __iomem *src = from;
0122         const u32 __iomem *src_trail;
0123         u64 *dst = to;
0124         u32 *dst_trail;
0125 
0126         for (size = (size + 3) / 4; size > 1; size -= 2)
0127             *dst++ = readq_u(src++);
0128         if (size) {
0129             src_trail = (u32 __iomem *)src;
0130             dst_trail = (u32 *)dst;
0131             *dst_trail = readl_u(src_trail);
0132         }
0133     } else {
0134         const u32 __iomem *src = from;
0135         u32 *dst = to;
0136 
0137         for (size = (size + 3) / 4; size; size--)
0138             *dst++ = readl_u(src++);
0139     }
0140 }
0141 
0142 static inline void fza_writes(const void *from, void __iomem *to,
0143                   unsigned long size)
0144 {
0145     if (sizeof(unsigned long) == 8) {
0146         const u64 *src = from;
0147         const u32 *src_trail;
0148         u64 __iomem *dst = to;
0149         u32 __iomem *dst_trail;
0150 
0151         for (size = (size + 3) / 4; size > 1; size -= 2)
0152             writeq_u(*src++, dst++);
0153         if (size) {
0154             src_trail = (u32 *)src;
0155             dst_trail = (u32 __iomem *)dst;
0156             writel_u(*src_trail, dst_trail);
0157         }
0158     } else {
0159         const u32 *src = from;
0160         u32 __iomem *dst = to;
0161 
0162         for (size = (size + 3) / 4; size; size--)
0163             writel_u(*src++, dst++);
0164     }
0165 }
0166 
0167 static inline void fza_moves(const void __iomem *from, void __iomem *to,
0168                  unsigned long size)
0169 {
0170     if (sizeof(unsigned long) == 8) {
0171         const u64 __iomem *src = from;
0172         const u32 __iomem *src_trail;
0173         u64 __iomem *dst = to;
0174         u32 __iomem *dst_trail;
0175 
0176         for (size = (size + 3) / 4; size > 1; size -= 2)
0177             writeq_u(readq_u(src++), dst++);
0178         if (size) {
0179             src_trail = (u32 __iomem *)src;
0180             dst_trail = (u32 __iomem *)dst;
0181             writel_u(readl_u(src_trail), dst_trail);
0182         }
0183     } else {
0184         const u32 __iomem *src = from;
0185         u32 __iomem *dst = to;
0186 
0187         for (size = (size + 3) / 4; size; size--)
0188             writel_u(readl_u(src++), dst++);
0189     }
0190 }
0191 
0192 static inline void fza_zeros(void __iomem *to, unsigned long size)
0193 {
0194     if (sizeof(unsigned long) == 8) {
0195         u64 __iomem *dst = to;
0196         u32 __iomem *dst_trail;
0197 
0198         for (size = (size + 3) / 4; size > 1; size -= 2)
0199             writeq_u(0, dst++);
0200         if (size) {
0201             dst_trail = (u32 __iomem *)dst;
0202             writel_u(0, dst_trail);
0203         }
0204     } else {
0205         u32 __iomem *dst = to;
0206 
0207         for (size = (size + 3) / 4; size; size--)
0208             writel_u(0, dst++);
0209     }
0210 }
0211 
0212 static inline void fza_regs_dump(struct fza_private *fp)
0213 {
0214     pr_debug("%s: iomem registers:\n", fp->name);
0215     pr_debug(" reset:           0x%04x\n", readw_o(&fp->regs->reset));
0216     pr_debug(" interrupt event: 0x%04x\n", readw_u(&fp->regs->int_event));
0217     pr_debug(" status:          0x%04x\n", readw_u(&fp->regs->status));
0218     pr_debug(" interrupt mask:  0x%04x\n", readw_u(&fp->regs->int_mask));
0219     pr_debug(" control A:       0x%04x\n", readw_u(&fp->regs->control_a));
0220     pr_debug(" control B:       0x%04x\n", readw_u(&fp->regs->control_b));
0221 }
0222 
0223 static inline void fza_do_reset(struct fza_private *fp)
0224 {
0225     /* Reset the board. */
0226     writew_o(FZA_RESET_INIT, &fp->regs->reset);
0227     readw_o(&fp->regs->reset);  /* Synchronize. */
0228     readw_o(&fp->regs->reset);  /* Read it back for a small delay. */
0229     writew_o(FZA_RESET_CLR, &fp->regs->reset);
0230 
0231     /* Enable all interrupt events we handle. */
0232     writew_o(fp->int_mask, &fp->regs->int_mask);
0233     readw_o(&fp->regs->int_mask);   /* Synchronize. */
0234 }
0235 
0236 static inline void fza_do_shutdown(struct fza_private *fp)
0237 {
0238     /* Disable the driver mode. */
0239     writew_o(FZA_CONTROL_B_IDLE, &fp->regs->control_b);
0240 
0241     /* And reset the board. */
0242     writew_o(FZA_RESET_INIT, &fp->regs->reset);
0243     readw_o(&fp->regs->reset);  /* Synchronize. */
0244     writew_o(FZA_RESET_CLR, &fp->regs->reset);
0245     readw_o(&fp->regs->reset);  /* Synchronize. */
0246 }
0247 
0248 static int fza_reset(struct fza_private *fp)
0249 {
0250     unsigned long flags;
0251     uint status, state;
0252     long t;
0253 
0254     pr_info("%s: resetting the board...\n", fp->name);
0255 
0256     spin_lock_irqsave(&fp->lock, flags);
0257     fp->state_chg_flag = 0;
0258     fza_do_reset(fp);
0259     spin_unlock_irqrestore(&fp->lock, flags);
0260 
0261     /* DEC says RESET needs up to 30 seconds to complete.  My DEFZA-AA
0262      * rev. C03 happily finishes in 9.7 seconds. :-)  But we need to
0263      * be on the safe side...
0264      */
0265     t = wait_event_timeout(fp->state_chg_wait, fp->state_chg_flag,
0266                    45 * HZ);
0267     status = readw_u(&fp->regs->status);
0268     state = FZA_STATUS_GET_STATE(status);
0269     if (fp->state_chg_flag == 0) {
0270         pr_err("%s: RESET timed out!, state %x\n", fp->name, state);
0271         return -EIO;
0272     }
0273     if (state != FZA_STATE_UNINITIALIZED) {
0274         pr_err("%s: RESET failed!, state %x, failure ID %x\n",
0275                fp->name, state, FZA_STATUS_GET_TEST(status));
0276         return -EIO;
0277     }
0278     pr_info("%s: OK\n", fp->name);
0279     pr_debug("%s: RESET: %lums elapsed\n", fp->name,
0280          (45 * HZ - t) * 1000 / HZ);
0281 
0282     return 0;
0283 }
0284 
0285 static struct fza_ring_cmd __iomem *fza_cmd_send(struct net_device *dev,
0286                          int command)
0287 {
0288     struct fza_private *fp = netdev_priv(dev);
0289     struct fza_ring_cmd __iomem *ring = fp->ring_cmd + fp->ring_cmd_index;
0290     unsigned int old_mask, new_mask;
0291     union fza_cmd_buf __iomem *buf;
0292     struct netdev_hw_addr *ha;
0293     int i;
0294 
0295     old_mask = fp->int_mask;
0296     new_mask = old_mask & ~FZA_MASK_STATE_CHG;
0297     writew_u(new_mask, &fp->regs->int_mask);
0298     readw_o(&fp->regs->int_mask);           /* Synchronize. */
0299     fp->int_mask = new_mask;
0300 
0301     buf = fp->mmio + readl_u(&ring->buffer);
0302 
0303     if ((readl_u(&ring->cmd_own) & FZA_RING_OWN_MASK) !=
0304         FZA_RING_OWN_HOST) {
0305         pr_warn("%s: command buffer full, command: %u!\n", fp->name,
0306             command);
0307         return NULL;
0308     }
0309 
0310     switch (command) {
0311     case FZA_RING_CMD_INIT:
0312         writel_u(FZA_RING_TX_MODE, &buf->init.tx_mode);
0313         writel_u(FZA_RING_RX_SIZE, &buf->init.hst_rx_size);
0314         fza_zeros(&buf->init.counters, sizeof(buf->init.counters));
0315         break;
0316 
0317     case FZA_RING_CMD_MODCAM:
0318         i = 0;
0319         fza_writes(&hw_addr_purger, &buf->cam.hw_addr[i++],
0320                sizeof(*buf->cam.hw_addr));
0321         fza_writes(&hw_addr_beacon, &buf->cam.hw_addr[i++],
0322                sizeof(*buf->cam.hw_addr));
0323         netdev_for_each_mc_addr(ha, dev) {
0324             if (i >= FZA_CMD_CAM_SIZE)
0325                 break;
0326             fza_writes(ha->addr, &buf->cam.hw_addr[i++],
0327                    sizeof(*buf->cam.hw_addr));
0328         }
0329         while (i < FZA_CMD_CAM_SIZE)
0330             fza_zeros(&buf->cam.hw_addr[i++],
0331                   sizeof(*buf->cam.hw_addr));
0332         break;
0333 
0334     case FZA_RING_CMD_PARAM:
0335         writel_u(loopback, &buf->param.loop_mode);
0336         writel_u(fp->t_max, &buf->param.t_max);
0337         writel_u(fp->t_req, &buf->param.t_req);
0338         writel_u(fp->tvx, &buf->param.tvx);
0339         writel_u(fp->lem_threshold, &buf->param.lem_threshold);
0340         fza_writes(&fp->station_id, &buf->param.station_id,
0341                sizeof(buf->param.station_id));
0342         /* Convert to milliseconds due to buggy firmware. */
0343         writel_u(fp->rtoken_timeout / 12500,
0344              &buf->param.rtoken_timeout);
0345         writel_u(fp->ring_purger, &buf->param.ring_purger);
0346         break;
0347 
0348     case FZA_RING_CMD_MODPROM:
0349         if (dev->flags & IFF_PROMISC) {
0350             writel_u(1, &buf->modprom.llc_prom);
0351             writel_u(1, &buf->modprom.smt_prom);
0352         } else {
0353             writel_u(0, &buf->modprom.llc_prom);
0354             writel_u(0, &buf->modprom.smt_prom);
0355         }
0356         if (dev->flags & IFF_ALLMULTI ||
0357             netdev_mc_count(dev) > FZA_CMD_CAM_SIZE - 2)
0358             writel_u(1, &buf->modprom.llc_multi);
0359         else
0360             writel_u(0, &buf->modprom.llc_multi);
0361         writel_u(1, &buf->modprom.llc_bcast);
0362         break;
0363     }
0364 
0365     /* Trigger the command. */
0366     writel_u(FZA_RING_OWN_FZA | command, &ring->cmd_own);
0367     writew_o(FZA_CONTROL_A_CMD_POLL, &fp->regs->control_a);
0368 
0369     fp->ring_cmd_index = (fp->ring_cmd_index + 1) % FZA_RING_CMD_SIZE;
0370 
0371     fp->int_mask = old_mask;
0372     writew_u(fp->int_mask, &fp->regs->int_mask);
0373 
0374     return ring;
0375 }
0376 
0377 static int fza_init_send(struct net_device *dev,
0378              struct fza_cmd_init *__iomem *init)
0379 {
0380     struct fza_private *fp = netdev_priv(dev);
0381     struct fza_ring_cmd __iomem *ring;
0382     unsigned long flags;
0383     u32 stat;
0384     long t;
0385 
0386     spin_lock_irqsave(&fp->lock, flags);
0387     fp->cmd_done_flag = 0;
0388     ring = fza_cmd_send(dev, FZA_RING_CMD_INIT);
0389     spin_unlock_irqrestore(&fp->lock, flags);
0390     if (!ring)
0391         /* This should never happen in the uninitialized state,
0392          * so do not try to recover and just consider it fatal.
0393          */
0394         return -ENOBUFS;
0395 
0396     /* INIT may take quite a long time (160ms for my C03). */
0397     t = wait_event_timeout(fp->cmd_done_wait, fp->cmd_done_flag, 3 * HZ);
0398     if (fp->cmd_done_flag == 0) {
0399         pr_err("%s: INIT command timed out!, state %x\n", fp->name,
0400                FZA_STATUS_GET_STATE(readw_u(&fp->regs->status)));
0401         return -EIO;
0402     }
0403     stat = readl_u(&ring->stat);
0404     if (stat != FZA_RING_STAT_SUCCESS) {
0405         pr_err("%s: INIT command failed!, status %02x, state %x\n",
0406                fp->name, stat,
0407                FZA_STATUS_GET_STATE(readw_u(&fp->regs->status)));
0408         return -EIO;
0409     }
0410     pr_debug("%s: INIT: %lums elapsed\n", fp->name,
0411          (3 * HZ - t) * 1000 / HZ);
0412 
0413     if (init)
0414         *init = fp->mmio + readl_u(&ring->buffer);
0415     return 0;
0416 }
0417 
0418 static void fza_rx_init(struct fza_private *fp)
0419 {
0420     int i;
0421 
0422     /* Fill the host receive descriptor ring. */
0423     for (i = 0; i < FZA_RING_RX_SIZE; i++) {
0424         writel_o(0, &fp->ring_hst_rx[i].rmc);
0425         writel_o((fp->rx_dma[i] + 0x1000) >> 9,
0426              &fp->ring_hst_rx[i].buffer1);
0427         writel_o(fp->rx_dma[i] >> 9 | FZA_RING_OWN_FZA,
0428              &fp->ring_hst_rx[i].buf0_own);
0429     }
0430 }
0431 
0432 static void fza_set_rx_mode(struct net_device *dev)
0433 {
0434     fza_cmd_send(dev, FZA_RING_CMD_MODCAM);
0435     fza_cmd_send(dev, FZA_RING_CMD_MODPROM);
0436 }
0437 
0438 union fza_buffer_txp {
0439     struct fza_buffer_tx *data_ptr;
0440     struct fza_buffer_tx __iomem *mmio_ptr;
0441 };
0442 
0443 static int fza_do_xmit(union fza_buffer_txp ub, int len,
0444                struct net_device *dev, int smt)
0445 {
0446     struct fza_private *fp = netdev_priv(dev);
0447     struct fza_buffer_tx __iomem *rmc_tx_ptr;
0448     int i, first, frag_len, left_len;
0449     u32 own, rmc;
0450 
0451     if (((((fp->ring_rmc_txd_index - 1 + fp->ring_rmc_tx_size) -
0452            fp->ring_rmc_tx_index) % fp->ring_rmc_tx_size) *
0453          FZA_TX_BUFFER_SIZE) < len)
0454         return 1;
0455 
0456     first = fp->ring_rmc_tx_index;
0457 
0458     left_len = len;
0459     frag_len = FZA_TX_BUFFER_SIZE;
0460     /* First descriptor is relinquished last. */
0461     own = FZA_RING_TX_OWN_HOST;
0462     /* First descriptor carries frame length; we don't use cut-through. */
0463     rmc = FZA_RING_TX_SOP | FZA_RING_TX_VBC | len;
0464     do {
0465         i = fp->ring_rmc_tx_index;
0466         rmc_tx_ptr = &fp->buffer_tx[i];
0467 
0468         if (left_len < FZA_TX_BUFFER_SIZE)
0469             frag_len = left_len;
0470         left_len -= frag_len;
0471 
0472         /* Length must be a multiple of 4 as only word writes are
0473          * permitted!
0474          */
0475         frag_len = (frag_len + 3) & ~3;
0476         if (smt)
0477             fza_moves(ub.mmio_ptr, rmc_tx_ptr, frag_len);
0478         else
0479             fza_writes(ub.data_ptr, rmc_tx_ptr, frag_len);
0480 
0481         if (left_len == 0)
0482             rmc |= FZA_RING_TX_EOP;     /* Mark last frag. */
0483 
0484         writel_o(rmc, &fp->ring_rmc_tx[i].rmc);
0485         writel_o(own, &fp->ring_rmc_tx[i].own);
0486 
0487         ub.data_ptr++;
0488         fp->ring_rmc_tx_index = (fp->ring_rmc_tx_index + 1) %
0489                     fp->ring_rmc_tx_size;
0490 
0491         /* Settings for intermediate frags. */
0492         own = FZA_RING_TX_OWN_RMC;
0493         rmc = 0;
0494     } while (left_len > 0);
0495 
0496     if (((((fp->ring_rmc_txd_index - 1 + fp->ring_rmc_tx_size) -
0497            fp->ring_rmc_tx_index) % fp->ring_rmc_tx_size) *
0498          FZA_TX_BUFFER_SIZE) < dev->mtu + dev->hard_header_len) {
0499         netif_stop_queue(dev);
0500         pr_debug("%s: queue stopped\n", fp->name);
0501     }
0502 
0503     writel_o(FZA_RING_TX_OWN_RMC, &fp->ring_rmc_tx[first].own);
0504 
0505     /* Go, go, go! */
0506     writew_o(FZA_CONTROL_A_TX_POLL, &fp->regs->control_a);
0507 
0508     return 0;
0509 }
0510 
0511 static int fza_do_recv_smt(struct fza_buffer_tx *data_ptr, int len,
0512                u32 rmc, struct net_device *dev)
0513 {
0514     struct fza_private *fp = netdev_priv(dev);
0515     struct fza_buffer_tx __iomem *smt_rx_ptr;
0516     u32 own;
0517     int i;
0518 
0519     i = fp->ring_smt_rx_index;
0520     own = readl_o(&fp->ring_smt_rx[i].own);
0521     if ((own & FZA_RING_OWN_MASK) == FZA_RING_OWN_FZA)
0522         return 1;
0523 
0524     smt_rx_ptr = fp->mmio + readl_u(&fp->ring_smt_rx[i].buffer);
0525 
0526     /* Length must be a multiple of 4 as only word writes are permitted! */
0527     fza_writes(data_ptr, smt_rx_ptr, (len + 3) & ~3);
0528 
0529     writel_o(rmc, &fp->ring_smt_rx[i].rmc);
0530     writel_o(FZA_RING_OWN_FZA, &fp->ring_smt_rx[i].own);
0531 
0532     fp->ring_smt_rx_index =
0533         (fp->ring_smt_rx_index + 1) % fp->ring_smt_rx_size;
0534 
0535     /* Grab it! */
0536     writew_o(FZA_CONTROL_A_SMT_RX_POLL, &fp->regs->control_a);
0537 
0538     return 0;
0539 }
0540 
0541 static void fza_tx(struct net_device *dev)
0542 {
0543     struct fza_private *fp = netdev_priv(dev);
0544     u32 own, rmc;
0545     int i;
0546 
0547     while (1) {
0548         i = fp->ring_rmc_txd_index;
0549         if (i == fp->ring_rmc_tx_index)
0550             break;
0551         own = readl_o(&fp->ring_rmc_tx[i].own);
0552         if ((own & FZA_RING_OWN_MASK) == FZA_RING_TX_OWN_RMC)
0553             break;
0554 
0555         rmc = readl_u(&fp->ring_rmc_tx[i].rmc);
0556         /* Only process the first descriptor. */
0557         if ((rmc & FZA_RING_TX_SOP) != 0) {
0558             if ((rmc & FZA_RING_TX_DCC_MASK) ==
0559                 FZA_RING_TX_DCC_SUCCESS) {
0560                 int pkt_len = (rmc & FZA_RING_PBC_MASK) - 3;
0561                                 /* Omit PRH. */
0562 
0563                 fp->stats.tx_packets++;
0564                 fp->stats.tx_bytes += pkt_len;
0565             } else {
0566                 fp->stats.tx_errors++;
0567                 switch (rmc & FZA_RING_TX_DCC_MASK) {
0568                 case FZA_RING_TX_DCC_DTP_SOP:
0569                 case FZA_RING_TX_DCC_DTP:
0570                 case FZA_RING_TX_DCC_ABORT:
0571                     fp->stats.tx_aborted_errors++;
0572                     break;
0573                 case FZA_RING_TX_DCC_UNDRRUN:
0574                     fp->stats.tx_fifo_errors++;
0575                     break;
0576                 case FZA_RING_TX_DCC_PARITY:
0577                 default:
0578                     break;
0579                 }
0580             }
0581         }
0582 
0583         fp->ring_rmc_txd_index = (fp->ring_rmc_txd_index + 1) %
0584                      fp->ring_rmc_tx_size;
0585     }
0586 
0587     if (((((fp->ring_rmc_txd_index - 1 + fp->ring_rmc_tx_size) -
0588            fp->ring_rmc_tx_index) % fp->ring_rmc_tx_size) *
0589          FZA_TX_BUFFER_SIZE) >= dev->mtu + dev->hard_header_len) {
0590         if (fp->queue_active) {
0591             netif_wake_queue(dev);
0592             pr_debug("%s: queue woken\n", fp->name);
0593         }
0594     }
0595 }
0596 
0597 static inline int fza_rx_err(struct fza_private *fp,
0598                  const u32 rmc, const u8 fc)
0599 {
0600     int len, min_len, max_len;
0601 
0602     len = rmc & FZA_RING_PBC_MASK;
0603 
0604     if (unlikely((rmc & FZA_RING_RX_BAD) != 0)) {
0605         fp->stats.rx_errors++;
0606 
0607         /* Check special status codes. */
0608         if ((rmc & (FZA_RING_RX_CRC | FZA_RING_RX_RRR_MASK |
0609                 FZA_RING_RX_DA_MASK | FZA_RING_RX_SA_MASK)) ==
0610              (FZA_RING_RX_CRC | FZA_RING_RX_RRR_DADDR |
0611               FZA_RING_RX_DA_CAM | FZA_RING_RX_SA_ALIAS)) {
0612             if (len >= 8190)
0613                 fp->stats.rx_length_errors++;
0614             return 1;
0615         }
0616         if ((rmc & (FZA_RING_RX_CRC | FZA_RING_RX_RRR_MASK |
0617                 FZA_RING_RX_DA_MASK | FZA_RING_RX_SA_MASK)) ==
0618              (FZA_RING_RX_CRC | FZA_RING_RX_RRR_DADDR |
0619               FZA_RING_RX_DA_CAM | FZA_RING_RX_SA_CAM)) {
0620             /* Halt the interface to trigger a reset. */
0621             writew_o(FZA_CONTROL_A_HALT, &fp->regs->control_a);
0622             readw_o(&fp->regs->control_a);  /* Synchronize. */
0623             return 1;
0624         }
0625 
0626         /* Check the MAC status. */
0627         switch (rmc & FZA_RING_RX_RRR_MASK) {
0628         case FZA_RING_RX_RRR_OK:
0629             if ((rmc & FZA_RING_RX_CRC) != 0)
0630                 fp->stats.rx_crc_errors++;
0631             else if ((rmc & FZA_RING_RX_FSC_MASK) == 0 ||
0632                  (rmc & FZA_RING_RX_FSB_ERR) != 0)
0633                 fp->stats.rx_frame_errors++;
0634             return 1;
0635         case FZA_RING_RX_RRR_SADDR:
0636         case FZA_RING_RX_RRR_DADDR:
0637         case FZA_RING_RX_RRR_ABORT:
0638             /* Halt the interface to trigger a reset. */
0639             writew_o(FZA_CONTROL_A_HALT, &fp->regs->control_a);
0640             readw_o(&fp->regs->control_a);  /* Synchronize. */
0641             return 1;
0642         case FZA_RING_RX_RRR_LENGTH:
0643             fp->stats.rx_frame_errors++;
0644             return 1;
0645         default:
0646             return 1;
0647         }
0648     }
0649 
0650     /* Packet received successfully; validate the length. */
0651     switch (fc & FDDI_FC_K_FORMAT_MASK) {
0652     case FDDI_FC_K_FORMAT_MANAGEMENT:
0653         if ((fc & FDDI_FC_K_CLASS_MASK) == FDDI_FC_K_CLASS_ASYNC)
0654             min_len = 37;
0655         else
0656             min_len = 17;
0657         break;
0658     case FDDI_FC_K_FORMAT_LLC:
0659         min_len = 20;
0660         break;
0661     default:
0662         min_len = 17;
0663         break;
0664     }
0665     max_len = 4495;
0666     if (len < min_len || len > max_len) {
0667         fp->stats.rx_errors++;
0668         fp->stats.rx_length_errors++;
0669         return 1;
0670     }
0671 
0672     return 0;
0673 }
0674 
0675 static void fza_rx(struct net_device *dev)
0676 {
0677     struct fza_private *fp = netdev_priv(dev);
0678     struct sk_buff *skb, *newskb;
0679     struct fza_fddihdr *frame;
0680     dma_addr_t dma, newdma;
0681     u32 own, rmc, buf;
0682     int i, len;
0683     u8 fc;
0684 
0685     while (1) {
0686         i = fp->ring_hst_rx_index;
0687         own = readl_o(&fp->ring_hst_rx[i].buf0_own);
0688         if ((own & FZA_RING_OWN_MASK) == FZA_RING_OWN_FZA)
0689             break;
0690 
0691         rmc = readl_u(&fp->ring_hst_rx[i].rmc);
0692         skb = fp->rx_skbuff[i];
0693         dma = fp->rx_dma[i];
0694 
0695         /* The RMC doesn't count the preamble and the starting
0696          * delimiter.  We fix it up here for a total of 3 octets.
0697          */
0698         dma_rmb();
0699         len = (rmc & FZA_RING_PBC_MASK) + 3;
0700         frame = (struct fza_fddihdr *)skb->data;
0701 
0702         /* We need to get at real FC. */
0703         dma_sync_single_for_cpu(fp->bdev,
0704                     dma +
0705                     ((u8 *)&frame->hdr.fc - (u8 *)frame),
0706                     sizeof(frame->hdr.fc),
0707                     DMA_FROM_DEVICE);
0708         fc = frame->hdr.fc;
0709 
0710         if (fza_rx_err(fp, rmc, fc))
0711             goto err_rx;
0712 
0713         /* We have to 512-byte-align RX buffers... */
0714         newskb = fza_alloc_skb_irq(dev, FZA_RX_BUFFER_SIZE + 511);
0715         if (newskb) {
0716             fza_skb_align(newskb, 512);
0717             newdma = dma_map_single(fp->bdev, newskb->data,
0718                         FZA_RX_BUFFER_SIZE,
0719                         DMA_FROM_DEVICE);
0720             if (dma_mapping_error(fp->bdev, newdma)) {
0721                 dev_kfree_skb_irq(newskb);
0722                 newskb = NULL;
0723             }
0724         }
0725         if (newskb) {
0726             int pkt_len = len - 7;  /* Omit P, SD and FCS. */
0727             int is_multi;
0728             int rx_stat;
0729 
0730             dma_unmap_single(fp->bdev, dma, FZA_RX_BUFFER_SIZE,
0731                      DMA_FROM_DEVICE);
0732 
0733             /* Queue SMT frames to the SMT receive ring. */
0734             if ((fc & (FDDI_FC_K_CLASS_MASK |
0735                    FDDI_FC_K_FORMAT_MASK)) ==
0736                  (FDDI_FC_K_CLASS_ASYNC |
0737                   FDDI_FC_K_FORMAT_MANAGEMENT) &&
0738                 (rmc & FZA_RING_RX_DA_MASK) !=
0739                  FZA_RING_RX_DA_PROM) {
0740                 if (fza_do_recv_smt((struct fza_buffer_tx *)
0741                             skb->data, len, rmc,
0742                             dev)) {
0743                     writel_o(FZA_CONTROL_A_SMT_RX_OVFL,
0744                          &fp->regs->control_a);
0745                 }
0746             }
0747 
0748             is_multi = ((frame->hdr.daddr[0] & 0x01) != 0);
0749 
0750             skb_reserve(skb, 3);    /* Skip over P and SD. */
0751             skb_put(skb, pkt_len);  /* And cut off FCS. */
0752             skb->protocol = fddi_type_trans(skb, dev);
0753 
0754             rx_stat = netif_rx(skb);
0755             if (rx_stat != NET_RX_DROP) {
0756                 fp->stats.rx_packets++;
0757                 fp->stats.rx_bytes += pkt_len;
0758                 if (is_multi)
0759                     fp->stats.multicast++;
0760             } else {
0761                 fp->stats.rx_dropped++;
0762             }
0763 
0764             skb = newskb;
0765             dma = newdma;
0766             fp->rx_skbuff[i] = skb;
0767             fp->rx_dma[i] = dma;
0768         } else {
0769             fp->stats.rx_dropped++;
0770             pr_notice("%s: memory squeeze, dropping packet\n",
0771                   fp->name);
0772         }
0773 
0774 err_rx:
0775         writel_o(0, &fp->ring_hst_rx[i].rmc);
0776         buf = (dma + 0x1000) >> 9;
0777         writel_o(buf, &fp->ring_hst_rx[i].buffer1);
0778         buf = dma >> 9 | FZA_RING_OWN_FZA;
0779         writel_o(buf, &fp->ring_hst_rx[i].buf0_own);
0780         fp->ring_hst_rx_index =
0781             (fp->ring_hst_rx_index + 1) % fp->ring_hst_rx_size;
0782     }
0783 }
0784 
0785 static void fza_tx_smt(struct net_device *dev)
0786 {
0787     struct fza_private *fp = netdev_priv(dev);
0788     struct fza_buffer_tx __iomem *smt_tx_ptr;
0789     int i, len;
0790     u32 own;
0791 
0792     while (1) {
0793         i = fp->ring_smt_tx_index;
0794         own = readl_o(&fp->ring_smt_tx[i].own);
0795         if ((own & FZA_RING_OWN_MASK) == FZA_RING_OWN_FZA)
0796             break;
0797 
0798         smt_tx_ptr = fp->mmio + readl_u(&fp->ring_smt_tx[i].buffer);
0799         len = readl_u(&fp->ring_smt_tx[i].rmc) & FZA_RING_PBC_MASK;
0800 
0801         if (!netif_queue_stopped(dev)) {
0802             if (dev_nit_active(dev)) {
0803                 struct fza_buffer_tx *skb_data_ptr;
0804                 struct sk_buff *skb;
0805 
0806                 /* Length must be a multiple of 4 as only word
0807                  * reads are permitted!
0808                  */
0809                 skb = fza_alloc_skb_irq(dev, (len + 3) & ~3);
0810                 if (!skb)
0811                     goto err_no_skb;    /* Drop. */
0812 
0813                 skb_data_ptr = (struct fza_buffer_tx *)
0814                            skb->data;
0815 
0816                 fza_reads(smt_tx_ptr, skb_data_ptr,
0817                       (len + 3) & ~3);
0818                 skb->dev = dev;
0819                 skb_reserve(skb, 3);    /* Skip over PRH. */
0820                 skb_put(skb, len - 3);
0821                 skb_reset_network_header(skb);
0822 
0823                 dev_queue_xmit_nit(skb, dev);
0824 
0825                 dev_kfree_skb_irq(skb);
0826 
0827 err_no_skb:
0828                 ;
0829             }
0830 
0831             /* Queue the frame to the RMC transmit ring. */
0832             fza_do_xmit((union fza_buffer_txp)
0833                     { .mmio_ptr = smt_tx_ptr },
0834                     len, dev, 1);
0835         }
0836 
0837         writel_o(FZA_RING_OWN_FZA, &fp->ring_smt_tx[i].own);
0838         fp->ring_smt_tx_index =
0839             (fp->ring_smt_tx_index + 1) % fp->ring_smt_tx_size;
0840     }
0841 }
0842 
0843 static void fza_uns(struct net_device *dev)
0844 {
0845     struct fza_private *fp = netdev_priv(dev);
0846     u32 own;
0847     int i;
0848 
0849     while (1) {
0850         i = fp->ring_uns_index;
0851         own = readl_o(&fp->ring_uns[i].own);
0852         if ((own & FZA_RING_OWN_MASK) == FZA_RING_OWN_FZA)
0853             break;
0854 
0855         if (readl_u(&fp->ring_uns[i].id) == FZA_RING_UNS_RX_OVER) {
0856             fp->stats.rx_errors++;
0857             fp->stats.rx_over_errors++;
0858         }
0859 
0860         writel_o(FZA_RING_OWN_FZA, &fp->ring_uns[i].own);
0861         fp->ring_uns_index =
0862             (fp->ring_uns_index + 1) % FZA_RING_UNS_SIZE;
0863     }
0864 }
0865 
0866 static void fza_tx_flush(struct net_device *dev)
0867 {
0868     struct fza_private *fp = netdev_priv(dev);
0869     u32 own;
0870     int i;
0871 
0872     /* Clean up the SMT TX ring. */
0873     i = fp->ring_smt_tx_index;
0874     do {
0875         writel_o(FZA_RING_OWN_FZA, &fp->ring_smt_tx[i].own);
0876         fp->ring_smt_tx_index =
0877             (fp->ring_smt_tx_index + 1) % fp->ring_smt_tx_size;
0878 
0879     } while (i != fp->ring_smt_tx_index);
0880 
0881     /* Clean up the RMC TX ring. */
0882     i = fp->ring_rmc_tx_index;
0883     do {
0884         own = readl_o(&fp->ring_rmc_tx[i].own);
0885         if ((own & FZA_RING_OWN_MASK) == FZA_RING_TX_OWN_RMC) {
0886             u32 rmc = readl_u(&fp->ring_rmc_tx[i].rmc);
0887 
0888             writel_u(rmc | FZA_RING_TX_DTP,
0889                  &fp->ring_rmc_tx[i].rmc);
0890         }
0891         fp->ring_rmc_tx_index =
0892             (fp->ring_rmc_tx_index + 1) % fp->ring_rmc_tx_size;
0893 
0894     } while (i != fp->ring_rmc_tx_index);
0895 
0896     /* Done. */
0897     writew_o(FZA_CONTROL_A_FLUSH_DONE, &fp->regs->control_a);
0898 }
0899 
0900 static irqreturn_t fza_interrupt(int irq, void *dev_id)
0901 {
0902     struct net_device *dev = dev_id;
0903     struct fza_private *fp = netdev_priv(dev);
0904     uint int_event;
0905 
0906     /* Get interrupt events. */
0907     int_event = readw_o(&fp->regs->int_event) & fp->int_mask;
0908     if (int_event == 0)
0909         return IRQ_NONE;
0910 
0911     /* Clear the events. */
0912     writew_u(int_event, &fp->regs->int_event);
0913 
0914     /* Now handle the events.  The order matters. */
0915 
0916     /* Command finished interrupt. */
0917     if ((int_event & FZA_EVENT_CMD_DONE) != 0) {
0918         fp->irq_count_cmd_done++;
0919 
0920         spin_lock(&fp->lock);
0921         fp->cmd_done_flag = 1;
0922         wake_up(&fp->cmd_done_wait);
0923         spin_unlock(&fp->lock);
0924     }
0925 
0926     /* Transmit finished interrupt. */
0927     if ((int_event & FZA_EVENT_TX_DONE) != 0) {
0928         fp->irq_count_tx_done++;
0929         fza_tx(dev);
0930     }
0931 
0932     /* Host receive interrupt. */
0933     if ((int_event & FZA_EVENT_RX_POLL) != 0) {
0934         fp->irq_count_rx_poll++;
0935         fza_rx(dev);
0936     }
0937 
0938     /* SMT transmit interrupt. */
0939     if ((int_event & FZA_EVENT_SMT_TX_POLL) != 0) {
0940         fp->irq_count_smt_tx_poll++;
0941         fza_tx_smt(dev);
0942     }
0943 
0944     /* Transmit ring flush request. */
0945     if ((int_event & FZA_EVENT_FLUSH_TX) != 0) {
0946         fp->irq_count_flush_tx++;
0947         fza_tx_flush(dev);
0948     }
0949 
0950     /* Link status change interrupt. */
0951     if ((int_event & FZA_EVENT_LINK_ST_CHG) != 0) {
0952         uint status;
0953 
0954         fp->irq_count_link_st_chg++;
0955         status = readw_u(&fp->regs->status);
0956         if (FZA_STATUS_GET_LINK(status) == FZA_LINK_ON) {
0957             netif_carrier_on(dev);
0958             pr_info("%s: link available\n", fp->name);
0959         } else {
0960             netif_carrier_off(dev);
0961             pr_info("%s: link unavailable\n", fp->name);
0962         }
0963     }
0964 
0965     /* Unsolicited event interrupt. */
0966     if ((int_event & FZA_EVENT_UNS_POLL) != 0) {
0967         fp->irq_count_uns_poll++;
0968         fza_uns(dev);
0969     }
0970 
0971     /* State change interrupt. */
0972     if ((int_event & FZA_EVENT_STATE_CHG) != 0) {
0973         uint status, state;
0974 
0975         fp->irq_count_state_chg++;
0976 
0977         status = readw_u(&fp->regs->status);
0978         state = FZA_STATUS_GET_STATE(status);
0979         pr_debug("%s: state change: %x\n", fp->name, state);
0980         switch (state) {
0981         case FZA_STATE_RESET:
0982             break;
0983 
0984         case FZA_STATE_UNINITIALIZED:
0985             netif_carrier_off(dev);
0986             del_timer_sync(&fp->reset_timer);
0987             fp->ring_cmd_index = 0;
0988             fp->ring_uns_index = 0;
0989             fp->ring_rmc_tx_index = 0;
0990             fp->ring_rmc_txd_index = 0;
0991             fp->ring_hst_rx_index = 0;
0992             fp->ring_smt_tx_index = 0;
0993             fp->ring_smt_rx_index = 0;
0994             if (fp->state > state) {
0995                 pr_info("%s: OK\n", fp->name);
0996                 fza_cmd_send(dev, FZA_RING_CMD_INIT);
0997             }
0998             break;
0999 
1000         case FZA_STATE_INITIALIZED:
1001             if (fp->state > state) {
1002                 fza_set_rx_mode(dev);
1003                 fza_cmd_send(dev, FZA_RING_CMD_PARAM);
1004             }
1005             break;
1006 
1007         case FZA_STATE_RUNNING:
1008         case FZA_STATE_MAINTENANCE:
1009             fp->state = state;
1010             fza_rx_init(fp);
1011             fp->queue_active = 1;
1012             netif_wake_queue(dev);
1013             pr_debug("%s: queue woken\n", fp->name);
1014             break;
1015 
1016         case FZA_STATE_HALTED:
1017             fp->queue_active = 0;
1018             netif_stop_queue(dev);
1019             pr_debug("%s: queue stopped\n", fp->name);
1020             del_timer_sync(&fp->reset_timer);
1021             pr_warn("%s: halted, reason: %x\n", fp->name,
1022                 FZA_STATUS_GET_HALT(status));
1023             fza_regs_dump(fp);
1024             pr_info("%s: resetting the board...\n", fp->name);
1025             fza_do_reset(fp);
1026             fp->timer_state = 0;
1027             fp->reset_timer.expires = jiffies + 45 * HZ;
1028             add_timer(&fp->reset_timer);
1029             break;
1030 
1031         default:
1032             pr_warn("%s: undefined state: %x\n", fp->name, state);
1033             break;
1034         }
1035 
1036         spin_lock(&fp->lock);
1037         fp->state_chg_flag = 1;
1038         wake_up(&fp->state_chg_wait);
1039         spin_unlock(&fp->lock);
1040     }
1041 
1042     return IRQ_HANDLED;
1043 }
1044 
1045 static void fza_reset_timer(struct timer_list *t)
1046 {
1047     struct fza_private *fp = from_timer(fp, t, reset_timer);
1048 
1049     if (!fp->timer_state) {
1050         pr_err("%s: RESET timed out!\n", fp->name);
1051         pr_info("%s: trying harder...\n", fp->name);
1052 
1053         /* Assert the board reset. */
1054         writew_o(FZA_RESET_INIT, &fp->regs->reset);
1055         readw_o(&fp->regs->reset);      /* Synchronize. */
1056 
1057         fp->timer_state = 1;
1058         fp->reset_timer.expires = jiffies + HZ;
1059     } else {
1060         /* Clear the board reset. */
1061         writew_u(FZA_RESET_CLR, &fp->regs->reset);
1062 
1063         /* Enable all interrupt events we handle. */
1064         writew_o(fp->int_mask, &fp->regs->int_mask);
1065         readw_o(&fp->regs->int_mask);       /* Synchronize. */
1066 
1067         fp->timer_state = 0;
1068         fp->reset_timer.expires = jiffies + 45 * HZ;
1069     }
1070     add_timer(&fp->reset_timer);
1071 }
1072 
1073 static int fza_set_mac_address(struct net_device *dev, void *addr)
1074 {
1075     return -EOPNOTSUPP;
1076 }
1077 
1078 static netdev_tx_t fza_start_xmit(struct sk_buff *skb, struct net_device *dev)
1079 {
1080     struct fza_private *fp = netdev_priv(dev);
1081     unsigned int old_mask, new_mask;
1082     int ret;
1083     u8 fc;
1084 
1085     skb_push(skb, 3);           /* Make room for PRH. */
1086 
1087     /* Decode FC to set PRH. */
1088     fc = skb->data[3];
1089     skb->data[0] = 0;
1090     skb->data[1] = 0;
1091     skb->data[2] = FZA_PRH2_NORMAL;
1092     if ((fc & FDDI_FC_K_CLASS_MASK) == FDDI_FC_K_CLASS_SYNC)
1093         skb->data[0] |= FZA_PRH0_FRAME_SYNC;
1094     switch (fc & FDDI_FC_K_FORMAT_MASK) {
1095     case FDDI_FC_K_FORMAT_MANAGEMENT:
1096         if ((fc & FDDI_FC_K_CONTROL_MASK) == 0) {
1097             /* Token. */
1098             skb->data[0] |= FZA_PRH0_TKN_TYPE_IMM;
1099             skb->data[1] |= FZA_PRH1_TKN_SEND_NONE;
1100         } else {
1101             /* SMT or MAC. */
1102             skb->data[0] |= FZA_PRH0_TKN_TYPE_UNR;
1103             skb->data[1] |= FZA_PRH1_TKN_SEND_UNR;
1104         }
1105         skb->data[1] |= FZA_PRH1_CRC_NORMAL;
1106         break;
1107     case FDDI_FC_K_FORMAT_LLC:
1108     case FDDI_FC_K_FORMAT_FUTURE:
1109         skb->data[0] |= FZA_PRH0_TKN_TYPE_UNR;
1110         skb->data[1] |= FZA_PRH1_CRC_NORMAL | FZA_PRH1_TKN_SEND_UNR;
1111         break;
1112     case FDDI_FC_K_FORMAT_IMPLEMENTOR:
1113         skb->data[0] |= FZA_PRH0_TKN_TYPE_UNR;
1114         skb->data[1] |= FZA_PRH1_TKN_SEND_ORIG;
1115         break;
1116     }
1117 
1118     /* SMT transmit interrupts may sneak frames into the RMC
1119      * transmit ring.  We disable them while queueing a frame
1120      * to maintain consistency.
1121      */
1122     old_mask = fp->int_mask;
1123     new_mask = old_mask & ~FZA_MASK_SMT_TX_POLL;
1124     writew_u(new_mask, &fp->regs->int_mask);
1125     readw_o(&fp->regs->int_mask);           /* Synchronize. */
1126     fp->int_mask = new_mask;
1127     ret = fza_do_xmit((union fza_buffer_txp)
1128               { .data_ptr = (struct fza_buffer_tx *)skb->data },
1129               skb->len, dev, 0);
1130     fp->int_mask = old_mask;
1131     writew_u(fp->int_mask, &fp->regs->int_mask);
1132 
1133     if (ret) {
1134         /* Probably an SMT packet filled the remaining space,
1135          * so just stop the queue, but don't report it as an error.
1136          */
1137         netif_stop_queue(dev);
1138         pr_debug("%s: queue stopped\n", fp->name);
1139         fp->stats.tx_dropped++;
1140     }
1141 
1142     dev_kfree_skb(skb);
1143 
1144     return ret;
1145 }
1146 
1147 static int fza_open(struct net_device *dev)
1148 {
1149     struct fza_private *fp = netdev_priv(dev);
1150     struct fza_ring_cmd __iomem *ring;
1151     struct sk_buff *skb;
1152     unsigned long flags;
1153     dma_addr_t dma;
1154     int ret, i;
1155     u32 stat;
1156     long t;
1157 
1158     for (i = 0; i < FZA_RING_RX_SIZE; i++) {
1159         /* We have to 512-byte-align RX buffers... */
1160         skb = fza_alloc_skb(dev, FZA_RX_BUFFER_SIZE + 511);
1161         if (skb) {
1162             fza_skb_align(skb, 512);
1163             dma = dma_map_single(fp->bdev, skb->data,
1164                          FZA_RX_BUFFER_SIZE,
1165                          DMA_FROM_DEVICE);
1166             if (dma_mapping_error(fp->bdev, dma)) {
1167                 dev_kfree_skb(skb);
1168                 skb = NULL;
1169             }
1170         }
1171         if (!skb) {
1172             for (--i; i >= 0; i--) {
1173                 dma_unmap_single(fp->bdev, fp->rx_dma[i],
1174                          FZA_RX_BUFFER_SIZE,
1175                          DMA_FROM_DEVICE);
1176                 dev_kfree_skb(fp->rx_skbuff[i]);
1177                 fp->rx_dma[i] = 0;
1178                 fp->rx_skbuff[i] = NULL;
1179             }
1180             return -ENOMEM;
1181         }
1182         fp->rx_skbuff[i] = skb;
1183         fp->rx_dma[i] = dma;
1184     }
1185 
1186     ret = fza_init_send(dev, NULL);
1187     if (ret != 0)
1188         return ret;
1189 
1190     /* Purger and Beacon multicasts need to be supplied before PARAM. */
1191     fza_set_rx_mode(dev);
1192 
1193     spin_lock_irqsave(&fp->lock, flags);
1194     fp->cmd_done_flag = 0;
1195     ring = fza_cmd_send(dev, FZA_RING_CMD_PARAM);
1196     spin_unlock_irqrestore(&fp->lock, flags);
1197     if (!ring)
1198         return -ENOBUFS;
1199 
1200     t = wait_event_timeout(fp->cmd_done_wait, fp->cmd_done_flag, 3 * HZ);
1201     if (fp->cmd_done_flag == 0) {
1202         pr_err("%s: PARAM command timed out!, state %x\n", fp->name,
1203                FZA_STATUS_GET_STATE(readw_u(&fp->regs->status)));
1204         return -EIO;
1205     }
1206     stat = readl_u(&ring->stat);
1207     if (stat != FZA_RING_STAT_SUCCESS) {
1208         pr_err("%s: PARAM command failed!, status %02x, state %x\n",
1209                fp->name, stat,
1210                FZA_STATUS_GET_STATE(readw_u(&fp->regs->status)));
1211         return -EIO;
1212     }
1213     pr_debug("%s: PARAM: %lums elapsed\n", fp->name,
1214          (3 * HZ - t) * 1000 / HZ);
1215 
1216     return 0;
1217 }
1218 
1219 static int fza_close(struct net_device *dev)
1220 {
1221     struct fza_private *fp = netdev_priv(dev);
1222     unsigned long flags;
1223     uint state;
1224     long t;
1225     int i;
1226 
1227     netif_stop_queue(dev);
1228     pr_debug("%s: queue stopped\n", fp->name);
1229 
1230     del_timer_sync(&fp->reset_timer);
1231     spin_lock_irqsave(&fp->lock, flags);
1232     fp->state = FZA_STATE_UNINITIALIZED;
1233     fp->state_chg_flag = 0;
1234     /* Shut the interface down. */
1235     writew_o(FZA_CONTROL_A_SHUT, &fp->regs->control_a);
1236     readw_o(&fp->regs->control_a);          /* Synchronize. */
1237     spin_unlock_irqrestore(&fp->lock, flags);
1238 
1239     /* DEC says SHUT needs up to 10 seconds to complete. */
1240     t = wait_event_timeout(fp->state_chg_wait, fp->state_chg_flag,
1241                    15 * HZ);
1242     state = FZA_STATUS_GET_STATE(readw_o(&fp->regs->status));
1243     if (fp->state_chg_flag == 0) {
1244         pr_err("%s: SHUT timed out!, state %x\n", fp->name, state);
1245         return -EIO;
1246     }
1247     if (state != FZA_STATE_UNINITIALIZED) {
1248         pr_err("%s: SHUT failed!, state %x\n", fp->name, state);
1249         return -EIO;
1250     }
1251     pr_debug("%s: SHUT: %lums elapsed\n", fp->name,
1252          (15 * HZ - t) * 1000 / HZ);
1253 
1254     for (i = 0; i < FZA_RING_RX_SIZE; i++)
1255         if (fp->rx_skbuff[i]) {
1256             dma_unmap_single(fp->bdev, fp->rx_dma[i],
1257                      FZA_RX_BUFFER_SIZE, DMA_FROM_DEVICE);
1258             dev_kfree_skb(fp->rx_skbuff[i]);
1259             fp->rx_dma[i] = 0;
1260             fp->rx_skbuff[i] = NULL;
1261         }
1262 
1263     return 0;
1264 }
1265 
1266 static struct net_device_stats *fza_get_stats(struct net_device *dev)
1267 {
1268     struct fza_private *fp = netdev_priv(dev);
1269 
1270     return &fp->stats;
1271 }
1272 
1273 static int fza_probe(struct device *bdev)
1274 {
1275     static const struct net_device_ops netdev_ops = {
1276         .ndo_open = fza_open,
1277         .ndo_stop = fza_close,
1278         .ndo_start_xmit = fza_start_xmit,
1279         .ndo_set_rx_mode = fza_set_rx_mode,
1280         .ndo_set_mac_address = fza_set_mac_address,
1281         .ndo_get_stats = fza_get_stats,
1282     };
1283     static int version_printed;
1284     char rom_rev[4], fw_rev[4], rmc_rev[4];
1285     struct tc_dev *tdev = to_tc_dev(bdev);
1286     struct fza_cmd_init __iomem *init;
1287     resource_size_t start, len;
1288     struct net_device *dev;
1289     struct fza_private *fp;
1290     uint smt_ver, pmd_type;
1291     void __iomem *mmio;
1292     uint hw_addr[2];
1293     int ret, i;
1294 
1295     if (!version_printed) {
1296         pr_info("%s", version);
1297         version_printed = 1;
1298     }
1299 
1300     dev = alloc_fddidev(sizeof(*fp));
1301     if (!dev)
1302         return -ENOMEM;
1303     SET_NETDEV_DEV(dev, bdev);
1304 
1305     fp = netdev_priv(dev);
1306     dev_set_drvdata(bdev, dev);
1307 
1308     fp->bdev = bdev;
1309     fp->name = dev_name(bdev);
1310 
1311     /* Request the I/O MEM resource. */
1312     start = tdev->resource.start;
1313     len = tdev->resource.end - start + 1;
1314     if (!request_mem_region(start, len, dev_name(bdev))) {
1315         pr_err("%s: cannot reserve MMIO region\n", fp->name);
1316         ret = -EBUSY;
1317         goto err_out_kfree;
1318     }
1319 
1320     /* MMIO mapping setup. */
1321     mmio = ioremap(start, len);
1322     if (!mmio) {
1323         pr_err("%s: cannot map MMIO\n", fp->name);
1324         ret = -ENOMEM;
1325         goto err_out_resource;
1326     }
1327 
1328     /* Initialize the new device structure. */
1329     switch (loopback) {
1330     case FZA_LOOP_NORMAL:
1331     case FZA_LOOP_INTERN:
1332     case FZA_LOOP_EXTERN:
1333         break;
1334     default:
1335         loopback = FZA_LOOP_NORMAL;
1336     }
1337 
1338     fp->mmio = mmio;
1339     dev->irq = tdev->interrupt;
1340 
1341     pr_info("%s: DEC FDDIcontroller 700 or 700-C at 0x%08llx, irq %d\n",
1342         fp->name, (long long)tdev->resource.start, dev->irq);
1343     pr_debug("%s: mapped at: 0x%p\n", fp->name, mmio);
1344 
1345     fp->regs = mmio + FZA_REG_BASE;
1346     fp->ring_cmd = mmio + FZA_RING_CMD;
1347     fp->ring_uns = mmio + FZA_RING_UNS;
1348 
1349     init_waitqueue_head(&fp->state_chg_wait);
1350     init_waitqueue_head(&fp->cmd_done_wait);
1351     spin_lock_init(&fp->lock);
1352     fp->int_mask = FZA_MASK_NORMAL;
1353 
1354     timer_setup(&fp->reset_timer, fza_reset_timer, 0);
1355 
1356     /* Sanitize the board. */
1357     fza_regs_dump(fp);
1358     fza_do_shutdown(fp);
1359 
1360     ret = request_irq(dev->irq, fza_interrupt, IRQF_SHARED, fp->name, dev);
1361     if (ret != 0) {
1362         pr_err("%s: unable to get IRQ %d!\n", fp->name, dev->irq);
1363         goto err_out_map;
1364     }
1365 
1366     /* Enable the driver mode. */
1367     writew_o(FZA_CONTROL_B_DRIVER, &fp->regs->control_b);
1368 
1369     /* For some reason transmit done interrupts can trigger during
1370      * reset.  This avoids a division error in the handler.
1371      */
1372     fp->ring_rmc_tx_size = FZA_RING_TX_SIZE;
1373 
1374     ret = fza_reset(fp);
1375     if (ret != 0)
1376         goto err_out_irq;
1377 
1378     ret = fza_init_send(dev, &init);
1379     if (ret != 0)
1380         goto err_out_irq;
1381 
1382     fza_reads(&init->hw_addr, &hw_addr, sizeof(hw_addr));
1383     dev_addr_set(dev, (u8 *)&hw_addr);
1384 
1385     fza_reads(&init->rom_rev, &rom_rev, sizeof(rom_rev));
1386     fza_reads(&init->fw_rev, &fw_rev, sizeof(fw_rev));
1387     fza_reads(&init->rmc_rev, &rmc_rev, sizeof(rmc_rev));
1388     for (i = 3; i >= 0 && rom_rev[i] == ' '; i--)
1389         rom_rev[i] = 0;
1390     for (i = 3; i >= 0 && fw_rev[i] == ' '; i--)
1391         fw_rev[i] = 0;
1392     for (i = 3; i >= 0 && rmc_rev[i] == ' '; i--)
1393         rmc_rev[i] = 0;
1394 
1395     fp->ring_rmc_tx = mmio + readl_u(&init->rmc_tx);
1396     fp->ring_rmc_tx_size = readl_u(&init->rmc_tx_size);
1397     fp->ring_hst_rx = mmio + readl_u(&init->hst_rx);
1398     fp->ring_hst_rx_size = readl_u(&init->hst_rx_size);
1399     fp->ring_smt_tx = mmio + readl_u(&init->smt_tx);
1400     fp->ring_smt_tx_size = readl_u(&init->smt_tx_size);
1401     fp->ring_smt_rx = mmio + readl_u(&init->smt_rx);
1402     fp->ring_smt_rx_size = readl_u(&init->smt_rx_size);
1403 
1404     fp->buffer_tx = mmio + FZA_TX_BUFFER_ADDR(readl_u(&init->rmc_tx));
1405 
1406     fp->t_max = readl_u(&init->def_t_max);
1407     fp->t_req = readl_u(&init->def_t_req);
1408     fp->tvx = readl_u(&init->def_tvx);
1409     fp->lem_threshold = readl_u(&init->lem_threshold);
1410     fza_reads(&init->def_station_id, &fp->station_id,
1411           sizeof(fp->station_id));
1412     fp->rtoken_timeout = readl_u(&init->rtoken_timeout);
1413     fp->ring_purger = readl_u(&init->ring_purger);
1414 
1415     smt_ver = readl_u(&init->smt_ver);
1416     pmd_type = readl_u(&init->pmd_type);
1417 
1418     pr_debug("%s: INIT parameters:\n", fp->name);
1419     pr_debug("        tx_mode: %u\n", readl_u(&init->tx_mode));
1420     pr_debug("    hst_rx_size: %u\n", readl_u(&init->hst_rx_size));
1421     pr_debug("        rmc_rev: %.4s\n", rmc_rev);
1422     pr_debug("        rom_rev: %.4s\n", rom_rev);
1423     pr_debug("         fw_rev: %.4s\n", fw_rev);
1424     pr_debug("       mop_type: %u\n", readl_u(&init->mop_type));
1425     pr_debug("         hst_rx: 0x%08x\n", readl_u(&init->hst_rx));
1426     pr_debug("         rmc_tx: 0x%08x\n", readl_u(&init->rmc_tx));
1427     pr_debug("    rmc_tx_size: %u\n", readl_u(&init->rmc_tx_size));
1428     pr_debug("         smt_tx: 0x%08x\n", readl_u(&init->smt_tx));
1429     pr_debug("    smt_tx_size: %u\n", readl_u(&init->smt_tx_size));
1430     pr_debug("         smt_rx: 0x%08x\n", readl_u(&init->smt_rx));
1431     pr_debug("    smt_rx_size: %u\n", readl_u(&init->smt_rx_size));
1432     /* TC systems are always LE, so don't bother swapping. */
1433     pr_debug("        hw_addr: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
1434          (readl_u(&init->hw_addr[0]) >> 0) & 0xff,
1435          (readl_u(&init->hw_addr[0]) >> 8) & 0xff,
1436          (readl_u(&init->hw_addr[0]) >> 16) & 0xff,
1437          (readl_u(&init->hw_addr[0]) >> 24) & 0xff,
1438          (readl_u(&init->hw_addr[1]) >> 0) & 0xff,
1439          (readl_u(&init->hw_addr[1]) >> 8) & 0xff,
1440          (readl_u(&init->hw_addr[1]) >> 16) & 0xff,
1441          (readl_u(&init->hw_addr[1]) >> 24) & 0xff);
1442     pr_debug("      def_t_req: %u\n", readl_u(&init->def_t_req));
1443     pr_debug("        def_tvx: %u\n", readl_u(&init->def_tvx));
1444     pr_debug("      def_t_max: %u\n", readl_u(&init->def_t_max));
1445     pr_debug("  lem_threshold: %u\n", readl_u(&init->lem_threshold));
1446     /* Don't bother swapping, see above. */
1447     pr_debug(" def_station_id: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
1448          (readl_u(&init->def_station_id[0]) >> 0) & 0xff,
1449          (readl_u(&init->def_station_id[0]) >> 8) & 0xff,
1450          (readl_u(&init->def_station_id[0]) >> 16) & 0xff,
1451          (readl_u(&init->def_station_id[0]) >> 24) & 0xff,
1452          (readl_u(&init->def_station_id[1]) >> 0) & 0xff,
1453          (readl_u(&init->def_station_id[1]) >> 8) & 0xff,
1454          (readl_u(&init->def_station_id[1]) >> 16) & 0xff,
1455          (readl_u(&init->def_station_id[1]) >> 24) & 0xff);
1456     pr_debug("   pmd_type_alt: %u\n", readl_u(&init->pmd_type_alt));
1457     pr_debug("        smt_ver: %u\n", readl_u(&init->smt_ver));
1458     pr_debug(" rtoken_timeout: %u\n", readl_u(&init->rtoken_timeout));
1459     pr_debug("    ring_purger: %u\n", readl_u(&init->ring_purger));
1460     pr_debug("    smt_ver_max: %u\n", readl_u(&init->smt_ver_max));
1461     pr_debug("    smt_ver_min: %u\n", readl_u(&init->smt_ver_min));
1462     pr_debug("       pmd_type: %u\n", readl_u(&init->pmd_type));
1463 
1464     pr_info("%s: model %s, address %pMF\n",
1465         fp->name,
1466         pmd_type == FZA_PMD_TYPE_TW ?
1467             "700-C (DEFZA-CA), ThinWire PMD selected" :
1468             pmd_type == FZA_PMD_TYPE_STP ?
1469                 "700-C (DEFZA-CA), STP PMD selected" :
1470                 "700 (DEFZA-AA), MMF PMD",
1471         dev->dev_addr);
1472     pr_info("%s: ROM rev. %.4s, firmware rev. %.4s, RMC rev. %.4s, "
1473         "SMT ver. %u\n", fp->name, rom_rev, fw_rev, rmc_rev, smt_ver);
1474 
1475     /* Now that we fetched initial parameters just shut the interface
1476      * until opened.
1477      */
1478     ret = fza_close(dev);
1479     if (ret != 0)
1480         goto err_out_irq;
1481 
1482     /* The FZA-specific entries in the device structure. */
1483     dev->netdev_ops = &netdev_ops;
1484 
1485     ret = register_netdev(dev);
1486     if (ret != 0)
1487         goto err_out_irq;
1488 
1489     pr_info("%s: registered as %s\n", fp->name, dev->name);
1490     fp->name = (const char *)dev->name;
1491 
1492     get_device(bdev);
1493     return 0;
1494 
1495 err_out_irq:
1496     del_timer_sync(&fp->reset_timer);
1497     fza_do_shutdown(fp);
1498     free_irq(dev->irq, dev);
1499 
1500 err_out_map:
1501     iounmap(mmio);
1502 
1503 err_out_resource:
1504     release_mem_region(start, len);
1505 
1506 err_out_kfree:
1507     pr_err("%s: initialization failure, aborting!\n", fp->name);
1508     free_netdev(dev);
1509     return ret;
1510 }
1511 
1512 static int fza_remove(struct device *bdev)
1513 {
1514     struct net_device *dev = dev_get_drvdata(bdev);
1515     struct fza_private *fp = netdev_priv(dev);
1516     struct tc_dev *tdev = to_tc_dev(bdev);
1517     resource_size_t start, len;
1518 
1519     put_device(bdev);
1520 
1521     unregister_netdev(dev);
1522 
1523     del_timer_sync(&fp->reset_timer);
1524     fza_do_shutdown(fp);
1525     free_irq(dev->irq, dev);
1526 
1527     iounmap(fp->mmio);
1528 
1529     start = tdev->resource.start;
1530     len = tdev->resource.end - start + 1;
1531     release_mem_region(start, len);
1532 
1533     free_netdev(dev);
1534 
1535     return 0;
1536 }
1537 
1538 static struct tc_device_id const fza_tc_table[] = {
1539     { "DEC     ", "PMAF-AA " },
1540     { }
1541 };
1542 MODULE_DEVICE_TABLE(tc, fza_tc_table);
1543 
1544 static struct tc_driver fza_driver = {
1545     .id_table   = fza_tc_table,
1546     .driver     = {
1547         .name   = "defza",
1548         .bus    = &tc_bus_type,
1549         .probe  = fza_probe,
1550         .remove = fza_remove,
1551     },
1552 };
1553 
1554 static int fza_init(void)
1555 {
1556     return tc_register_driver(&fza_driver);
1557 }
1558 
1559 static void fza_exit(void)
1560 {
1561     tc_unregister_driver(&fza_driver);
1562 }
1563 
1564 module_init(fza_init);
1565 module_exit(fza_exit);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!