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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Intel IXP4xx Ethernet driver for Linux
0004  *
0005  * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
0006  *
0007  * Ethernet port config (0x00 is not present on IXP42X):
0008  *
0009  * logical port     0x00        0x10        0x20
0010  * NPE          0 (NPE-A)   1 (NPE-B)   2 (NPE-C)
0011  * physical PortId  2       0       1
0012  * TX queue     23      24      25
0013  * RX-free queue    26      27      28
0014  * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
0015  *
0016  * Queue entries:
0017  * bits 0 -> 1  - NPE ID (RX and TX-done)
0018  * bits 0 -> 2  - priority (TX, per 802.1D)
0019  * bits 3 -> 4  - port ID (user-set?)
0020  * bits 5 -> 31 - physical descriptor address
0021  */
0022 
0023 #include <linux/delay.h>
0024 #include <linux/dma-mapping.h>
0025 #include <linux/dmapool.h>
0026 #include <linux/etherdevice.h>
0027 #include <linux/io.h>
0028 #include <linux/kernel.h>
0029 #include <linux/net_tstamp.h>
0030 #include <linux/of.h>
0031 #include <linux/of_mdio.h>
0032 #include <linux/of_net.h>
0033 #include <linux/phy.h>
0034 #include <linux/platform_device.h>
0035 #include <linux/ptp_classify.h>
0036 #include <linux/slab.h>
0037 #include <linux/module.h>
0038 #include <linux/soc/ixp4xx/npe.h>
0039 #include <linux/soc/ixp4xx/qmgr.h>
0040 #include <linux/soc/ixp4xx/cpu.h>
0041 #include <linux/types.h>
0042 
0043 #define IXP4XX_ETH_NPEA     0x00
0044 #define IXP4XX_ETH_NPEB     0x10
0045 #define IXP4XX_ETH_NPEC     0x20
0046 
0047 #include "ixp46x_ts.h"
0048 
0049 #define DEBUG_DESC      0
0050 #define DEBUG_RX        0
0051 #define DEBUG_TX        0
0052 #define DEBUG_PKT_BYTES     0
0053 #define DEBUG_MDIO      0
0054 #define DEBUG_CLOSE     0
0055 
0056 #define DRV_NAME        "ixp4xx_eth"
0057 
0058 #define MAX_NPES        3
0059 
0060 #define RX_DESCS        64 /* also length of all RX queues */
0061 #define TX_DESCS        16 /* also length of all TX queues */
0062 #define TXDONE_QUEUE_LEN    64 /* dwords */
0063 
0064 #define POOL_ALLOC_SIZE     (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
0065 #define REGS_SIZE       0x1000
0066 #define MAX_MRU         1536 /* 0x600 */
0067 #define RX_BUFF_SIZE        ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
0068 
0069 #define NAPI_WEIGHT     16
0070 #define MDIO_INTERVAL       (3 * HZ)
0071 #define MAX_MDIO_RETRIES    100 /* microseconds, typically 30 cycles */
0072 #define MAX_CLOSE_WAIT      1000 /* microseconds, typically 2-3 cycles */
0073 
0074 #define NPE_ID(port_id)     ((port_id) >> 4)
0075 #define PHYSICAL_ID(port_id)    ((NPE_ID(port_id) + 2) % 3)
0076 #define TX_QUEUE(port_id)   (NPE_ID(port_id) + 23)
0077 #define RXFREE_QUEUE(port_id)   (NPE_ID(port_id) + 26)
0078 #define TXDONE_QUEUE        31
0079 
0080 #define PTP_SLAVE_MODE      1
0081 #define PTP_MASTER_MODE     2
0082 #define PORT2CHANNEL(p)     NPE_ID(p->id)
0083 
0084 /* TX Control Registers */
0085 #define TX_CNTRL0_TX_EN     0x01
0086 #define TX_CNTRL0_HALFDUPLEX    0x02
0087 #define TX_CNTRL0_RETRY     0x04
0088 #define TX_CNTRL0_PAD_EN    0x08
0089 #define TX_CNTRL0_APPEND_FCS    0x10
0090 #define TX_CNTRL0_2DEFER    0x20
0091 #define TX_CNTRL0_RMII      0x40 /* reduced MII */
0092 #define TX_CNTRL1_RETRIES   0x0F /* 4 bits */
0093 
0094 /* RX Control Registers */
0095 #define RX_CNTRL0_RX_EN     0x01
0096 #define RX_CNTRL0_PADSTRIP_EN   0x02
0097 #define RX_CNTRL0_SEND_FCS  0x04
0098 #define RX_CNTRL0_PAUSE_EN  0x08
0099 #define RX_CNTRL0_LOOP_EN   0x10
0100 #define RX_CNTRL0_ADDR_FLTR_EN  0x20
0101 #define RX_CNTRL0_RX_RUNT_EN    0x40
0102 #define RX_CNTRL0_BCAST_DIS 0x80
0103 #define RX_CNTRL1_DEFER_EN  0x01
0104 
0105 /* Core Control Register */
0106 #define CORE_RESET      0x01
0107 #define CORE_RX_FIFO_FLUSH  0x02
0108 #define CORE_TX_FIFO_FLUSH  0x04
0109 #define CORE_SEND_JAM       0x08
0110 #define CORE_MDC_EN     0x10 /* MDIO using NPE-B ETH-0 only */
0111 
0112 #define DEFAULT_TX_CNTRL0   (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY |    \
0113                  TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
0114                  TX_CNTRL0_2DEFER)
0115 #define DEFAULT_RX_CNTRL0   RX_CNTRL0_RX_EN
0116 #define DEFAULT_CORE_CNTRL  CORE_MDC_EN
0117 
0118 
0119 /* NPE message codes */
0120 #define NPE_GETSTATUS           0x00
0121 #define NPE_EDB_SETPORTADDRESS      0x01
0122 #define NPE_EDB_GETMACADDRESSDATABASE   0x02
0123 #define NPE_EDB_SETMACADDRESSSDATABASE  0x03
0124 #define NPE_GETSTATS            0x04
0125 #define NPE_RESETSTATS          0x05
0126 #define NPE_SETMAXFRAMELENGTHS      0x06
0127 #define NPE_VLAN_SETRXTAGMODE       0x07
0128 #define NPE_VLAN_SETDEFAULTRXVID    0x08
0129 #define NPE_VLAN_SETPORTVLANTABLEENTRY  0x09
0130 #define NPE_VLAN_SETPORTVLANTABLERANGE  0x0A
0131 #define NPE_VLAN_SETRXQOSENTRY      0x0B
0132 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
0133 #define NPE_STP_SETBLOCKINGSTATE    0x0D
0134 #define NPE_FW_SETFIREWALLMODE      0x0E
0135 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
0136 #define NPE_PC_SETAPMACTABLE        0x11
0137 #define NPE_SETLOOPBACK_MODE        0x12
0138 #define NPE_PC_SETBSSIDTABLE        0x13
0139 #define NPE_ADDRESS_FILTER_CONFIG   0x14
0140 #define NPE_APPENDFCSCONFIG     0x15
0141 #define NPE_NOTIFY_MAC_RECOVERY_DONE    0x16
0142 #define NPE_MAC_RECOVERY_START      0x17
0143 
0144 
0145 #ifdef __ARMEB__
0146 typedef struct sk_buff buffer_t;
0147 #define free_buffer dev_kfree_skb
0148 #define free_buffer_irq dev_consume_skb_irq
0149 #else
0150 typedef void buffer_t;
0151 #define free_buffer kfree
0152 #define free_buffer_irq kfree
0153 #endif
0154 
0155 /* Information about built-in Ethernet MAC interfaces */
0156 struct eth_plat_info {
0157     u8 phy;     /* MII PHY ID, 0 - 31 */
0158     u8 rxq;     /* configurable, currently 0 - 31 only */
0159     u8 txreadyq;
0160     u8 hwaddr[ETH_ALEN];
0161     u8 npe;     /* NPE instance used by this interface */
0162     bool has_mdio;  /* If this instance has an MDIO bus */
0163 };
0164 
0165 struct eth_regs {
0166     u32 tx_control[2], __res1[2];       /* 000 */
0167     u32 rx_control[2], __res2[2];       /* 010 */
0168     u32 random_seed, __res3[3];     /* 020 */
0169     u32 partial_empty_threshold, __res4;    /* 030 */
0170     u32 partial_full_threshold, __res5; /* 038 */
0171     u32 tx_start_bytes, __res6[3];      /* 040 */
0172     u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
0173     u32 tx_2part_deferral[2], __res8[2];    /* 060 */
0174     u32 slot_time, __res9[3];       /* 070 */
0175     u32 mdio_command[4];            /* 080 */
0176     u32 mdio_status[4];         /* 090 */
0177     u32 mcast_mask[6], __res10[2];      /* 0A0 */
0178     u32 mcast_addr[6], __res11[2];      /* 0C0 */
0179     u32 int_clock_threshold, __res12[3];    /* 0E0 */
0180     u32 hw_addr[6], __res13[61];        /* 0F0 */
0181     u32 core_control;           /* 1FC */
0182 };
0183 
0184 struct port {
0185     struct eth_regs __iomem *regs;
0186     struct ixp46x_ts_regs __iomem *timesync_regs;
0187     int phc_index;
0188     struct npe *npe;
0189     struct net_device *netdev;
0190     struct napi_struct napi;
0191     struct eth_plat_info *plat;
0192     buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
0193     struct desc *desc_tab;  /* coherent */
0194     dma_addr_t desc_tab_phys;
0195     int id;         /* logical port ID */
0196     int speed, duplex;
0197     u8 firmware[4];
0198     int hwts_tx_en;
0199     int hwts_rx_en;
0200 };
0201 
0202 /* NPE message structure */
0203 struct msg {
0204 #ifdef __ARMEB__
0205     u8 cmd, eth_id, byte2, byte3;
0206     u8 byte4, byte5, byte6, byte7;
0207 #else
0208     u8 byte3, byte2, eth_id, cmd;
0209     u8 byte7, byte6, byte5, byte4;
0210 #endif
0211 };
0212 
0213 /* Ethernet packet descriptor */
0214 struct desc {
0215     u32 next;       /* pointer to next buffer, unused */
0216 
0217 #ifdef __ARMEB__
0218     u16 buf_len;        /* buffer length */
0219     u16 pkt_len;        /* packet length */
0220     u32 data;       /* pointer to data buffer in RAM */
0221     u8 dest_id;
0222     u8 src_id;
0223     u16 flags;
0224     u8 qos;
0225     u8 padlen;
0226     u16 vlan_tci;
0227 #else
0228     u16 pkt_len;        /* packet length */
0229     u16 buf_len;        /* buffer length */
0230     u32 data;       /* pointer to data buffer in RAM */
0231     u16 flags;
0232     u8 src_id;
0233     u8 dest_id;
0234     u16 vlan_tci;
0235     u8 padlen;
0236     u8 qos;
0237 #endif
0238 
0239 #ifdef __ARMEB__
0240     u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
0241     u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
0242     u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
0243 #else
0244     u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
0245     u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
0246     u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
0247 #endif
0248 };
0249 
0250 
0251 #define rx_desc_phys(port, n)   ((port)->desc_tab_phys +        \
0252                  (n) * sizeof(struct desc))
0253 #define rx_desc_ptr(port, n)    (&(port)->desc_tab[n])
0254 
0255 #define tx_desc_phys(port, n)   ((port)->desc_tab_phys +        \
0256                  ((n) + RX_DESCS) * sizeof(struct desc))
0257 #define tx_desc_ptr(port, n)    (&(port)->desc_tab[(n) + RX_DESCS])
0258 
0259 #ifndef __ARMEB__
0260 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
0261 {
0262     int i;
0263     for (i = 0; i < cnt; i++)
0264         dest[i] = swab32(src[i]);
0265 }
0266 #endif
0267 
0268 static DEFINE_SPINLOCK(mdio_lock);
0269 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
0270 static struct mii_bus *mdio_bus;
0271 static struct device_node *mdio_bus_np;
0272 static int ports_open;
0273 static struct port *npe_port_tab[MAX_NPES];
0274 static struct dma_pool *dma_pool;
0275 
0276 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
0277 {
0278     u8 *data = skb->data;
0279     unsigned int offset;
0280     u16 *hi, *id;
0281     u32 lo;
0282 
0283     if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4)
0284         return 0;
0285 
0286     offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
0287 
0288     if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
0289         return 0;
0290 
0291     hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
0292     id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
0293 
0294     memcpy(&lo, &hi[1], sizeof(lo));
0295 
0296     return (uid_hi == ntohs(*hi) &&
0297         uid_lo == ntohl(lo) &&
0298         seqid  == ntohs(*id));
0299 }
0300 
0301 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
0302 {
0303     struct skb_shared_hwtstamps *shhwtstamps;
0304     struct ixp46x_ts_regs *regs;
0305     u64 ns;
0306     u32 ch, hi, lo, val;
0307     u16 uid, seq;
0308 
0309     if (!port->hwts_rx_en)
0310         return;
0311 
0312     ch = PORT2CHANNEL(port);
0313 
0314     regs = port->timesync_regs;
0315 
0316     val = __raw_readl(&regs->channel[ch].ch_event);
0317 
0318     if (!(val & RX_SNAPSHOT_LOCKED))
0319         return;
0320 
0321     lo = __raw_readl(&regs->channel[ch].src_uuid_lo);
0322     hi = __raw_readl(&regs->channel[ch].src_uuid_hi);
0323 
0324     uid = hi & 0xffff;
0325     seq = (hi >> 16) & 0xffff;
0326 
0327     if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
0328         goto out;
0329 
0330     lo = __raw_readl(&regs->channel[ch].rx_snap_lo);
0331     hi = __raw_readl(&regs->channel[ch].rx_snap_hi);
0332     ns = ((u64) hi) << 32;
0333     ns |= lo;
0334     ns <<= TICKS_NS_SHIFT;
0335 
0336     shhwtstamps = skb_hwtstamps(skb);
0337     memset(shhwtstamps, 0, sizeof(*shhwtstamps));
0338     shhwtstamps->hwtstamp = ns_to_ktime(ns);
0339 out:
0340     __raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
0341 }
0342 
0343 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
0344 {
0345     struct skb_shared_hwtstamps shhwtstamps;
0346     struct ixp46x_ts_regs *regs;
0347     struct skb_shared_info *shtx;
0348     u64 ns;
0349     u32 ch, cnt, hi, lo, val;
0350 
0351     shtx = skb_shinfo(skb);
0352     if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
0353         shtx->tx_flags |= SKBTX_IN_PROGRESS;
0354     else
0355         return;
0356 
0357     ch = PORT2CHANNEL(port);
0358 
0359     regs = port->timesync_regs;
0360 
0361     /*
0362      * This really stinks, but we have to poll for the Tx time stamp.
0363      * Usually, the time stamp is ready after 4 to 6 microseconds.
0364      */
0365     for (cnt = 0; cnt < 100; cnt++) {
0366         val = __raw_readl(&regs->channel[ch].ch_event);
0367         if (val & TX_SNAPSHOT_LOCKED)
0368             break;
0369         udelay(1);
0370     }
0371     if (!(val & TX_SNAPSHOT_LOCKED)) {
0372         shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
0373         return;
0374     }
0375 
0376     lo = __raw_readl(&regs->channel[ch].tx_snap_lo);
0377     hi = __raw_readl(&regs->channel[ch].tx_snap_hi);
0378     ns = ((u64) hi) << 32;
0379     ns |= lo;
0380     ns <<= TICKS_NS_SHIFT;
0381 
0382     memset(&shhwtstamps, 0, sizeof(shhwtstamps));
0383     shhwtstamps.hwtstamp = ns_to_ktime(ns);
0384     skb_tstamp_tx(skb, &shhwtstamps);
0385 
0386     __raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
0387 }
0388 
0389 static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
0390 {
0391     struct hwtstamp_config cfg;
0392     struct ixp46x_ts_regs *regs;
0393     struct port *port = netdev_priv(netdev);
0394     int ret;
0395     int ch;
0396 
0397     if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
0398         return -EFAULT;
0399 
0400     ret = ixp46x_ptp_find(&port->timesync_regs, &port->phc_index);
0401     if (ret)
0402         return ret;
0403 
0404     ch = PORT2CHANNEL(port);
0405     regs = port->timesync_regs;
0406 
0407     if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
0408         return -ERANGE;
0409 
0410     switch (cfg.rx_filter) {
0411     case HWTSTAMP_FILTER_NONE:
0412         port->hwts_rx_en = 0;
0413         break;
0414     case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
0415         port->hwts_rx_en = PTP_SLAVE_MODE;
0416         __raw_writel(0, &regs->channel[ch].ch_control);
0417         break;
0418     case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
0419         port->hwts_rx_en = PTP_MASTER_MODE;
0420         __raw_writel(MASTER_MODE, &regs->channel[ch].ch_control);
0421         break;
0422     default:
0423         return -ERANGE;
0424     }
0425 
0426     port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
0427 
0428     /* Clear out any old time stamps. */
0429     __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
0430              &regs->channel[ch].ch_event);
0431 
0432     return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
0433 }
0434 
0435 static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
0436 {
0437     struct hwtstamp_config cfg;
0438     struct port *port = netdev_priv(netdev);
0439 
0440     cfg.flags = 0;
0441     cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
0442 
0443     switch (port->hwts_rx_en) {
0444     case 0:
0445         cfg.rx_filter = HWTSTAMP_FILTER_NONE;
0446         break;
0447     case PTP_SLAVE_MODE:
0448         cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
0449         break;
0450     case PTP_MASTER_MODE:
0451         cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
0452         break;
0453     default:
0454         WARN_ON_ONCE(1);
0455         return -ERANGE;
0456     }
0457 
0458     return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
0459 }
0460 
0461 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
0462                int write, u16 cmd)
0463 {
0464     int cycles = 0;
0465 
0466     if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
0467         printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
0468         return -1;
0469     }
0470 
0471     if (write) {
0472         __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
0473         __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
0474     }
0475     __raw_writel(((phy_id << 5) | location) & 0xFF,
0476              &mdio_regs->mdio_command[2]);
0477     __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
0478              &mdio_regs->mdio_command[3]);
0479 
0480     while ((cycles < MAX_MDIO_RETRIES) &&
0481            (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
0482         udelay(1);
0483         cycles++;
0484     }
0485 
0486     if (cycles == MAX_MDIO_RETRIES) {
0487         printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
0488                phy_id);
0489         return -1;
0490     }
0491 
0492 #if DEBUG_MDIO
0493     printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
0494            phy_id, write ? "write" : "read", cycles);
0495 #endif
0496 
0497     if (write)
0498         return 0;
0499 
0500     if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
0501 #if DEBUG_MDIO
0502         printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
0503                phy_id);
0504 #endif
0505         return 0xFFFF; /* don't return error */
0506     }
0507 
0508     return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
0509         ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
0510 }
0511 
0512 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
0513 {
0514     unsigned long flags;
0515     int ret;
0516 
0517     spin_lock_irqsave(&mdio_lock, flags);
0518     ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
0519     spin_unlock_irqrestore(&mdio_lock, flags);
0520 #if DEBUG_MDIO
0521     printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
0522            phy_id, location, ret);
0523 #endif
0524     return ret;
0525 }
0526 
0527 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
0528                  u16 val)
0529 {
0530     unsigned long flags;
0531     int ret;
0532 
0533     spin_lock_irqsave(&mdio_lock, flags);
0534     ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
0535     spin_unlock_irqrestore(&mdio_lock, flags);
0536 #if DEBUG_MDIO
0537     printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
0538            bus->name, phy_id, location, val, ret);
0539 #endif
0540     return ret;
0541 }
0542 
0543 static int ixp4xx_mdio_register(struct eth_regs __iomem *regs)
0544 {
0545     int err;
0546 
0547     if (!(mdio_bus = mdiobus_alloc()))
0548         return -ENOMEM;
0549 
0550     mdio_regs = regs;
0551     __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
0552     mdio_bus->name = "IXP4xx MII Bus";
0553     mdio_bus->read = &ixp4xx_mdio_read;
0554     mdio_bus->write = &ixp4xx_mdio_write;
0555     snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
0556 
0557     err = of_mdiobus_register(mdio_bus, mdio_bus_np);
0558     if (err)
0559         mdiobus_free(mdio_bus);
0560     return err;
0561 }
0562 
0563 static void ixp4xx_mdio_remove(void)
0564 {
0565     mdiobus_unregister(mdio_bus);
0566     mdiobus_free(mdio_bus);
0567 }
0568 
0569 
0570 static void ixp4xx_adjust_link(struct net_device *dev)
0571 {
0572     struct port *port = netdev_priv(dev);
0573     struct phy_device *phydev = dev->phydev;
0574 
0575     if (!phydev->link) {
0576         if (port->speed) {
0577             port->speed = 0;
0578             printk(KERN_INFO "%s: link down\n", dev->name);
0579         }
0580         return;
0581     }
0582 
0583     if (port->speed == phydev->speed && port->duplex == phydev->duplex)
0584         return;
0585 
0586     port->speed = phydev->speed;
0587     port->duplex = phydev->duplex;
0588 
0589     if (port->duplex)
0590         __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
0591                  &port->regs->tx_control[0]);
0592     else
0593         __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
0594                  &port->regs->tx_control[0]);
0595 
0596     netdev_info(dev, "%s: link up, speed %u Mb/s, %s duplex\n",
0597             dev->name, port->speed, port->duplex ? "full" : "half");
0598 }
0599 
0600 
0601 static inline void debug_pkt(struct net_device *dev, const char *func,
0602                  u8 *data, int len)
0603 {
0604 #if DEBUG_PKT_BYTES
0605     int i;
0606 
0607     netdev_debug(dev, "%s(%i) ", func, len);
0608     for (i = 0; i < len; i++) {
0609         if (i >= DEBUG_PKT_BYTES)
0610             break;
0611         printk("%s%02X",
0612                ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
0613                data[i]);
0614     }
0615     printk("\n");
0616 #endif
0617 }
0618 
0619 
0620 static inline void debug_desc(u32 phys, struct desc *desc)
0621 {
0622 #if DEBUG_DESC
0623     printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
0624            " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
0625            phys, desc->next, desc->buf_len, desc->pkt_len,
0626            desc->data, desc->dest_id, desc->src_id, desc->flags,
0627            desc->qos, desc->padlen, desc->vlan_tci,
0628            desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
0629            desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
0630            desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
0631            desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
0632 #endif
0633 }
0634 
0635 static inline int queue_get_desc(unsigned int queue, struct port *port,
0636                  int is_tx)
0637 {
0638     u32 phys, tab_phys, n_desc;
0639     struct desc *tab;
0640 
0641     if (!(phys = qmgr_get_entry(queue)))
0642         return -1;
0643 
0644     phys &= ~0x1F; /* mask out non-address bits */
0645     tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
0646     tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
0647     n_desc = (phys - tab_phys) / sizeof(struct desc);
0648     BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
0649     debug_desc(phys, &tab[n_desc]);
0650     BUG_ON(tab[n_desc].next);
0651     return n_desc;
0652 }
0653 
0654 static inline void queue_put_desc(unsigned int queue, u32 phys,
0655                   struct desc *desc)
0656 {
0657     debug_desc(phys, desc);
0658     BUG_ON(phys & 0x1F);
0659     qmgr_put_entry(queue, phys);
0660     /* Don't check for queue overflow here, we've allocated sufficient
0661        length and queues >= 32 don't support this check anyway. */
0662 }
0663 
0664 
0665 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
0666 {
0667 #ifdef __ARMEB__
0668     dma_unmap_single(&port->netdev->dev, desc->data,
0669              desc->buf_len, DMA_TO_DEVICE);
0670 #else
0671     dma_unmap_single(&port->netdev->dev, desc->data & ~3,
0672              ALIGN((desc->data & 3) + desc->buf_len, 4),
0673              DMA_TO_DEVICE);
0674 #endif
0675 }
0676 
0677 
0678 static void eth_rx_irq(void *pdev)
0679 {
0680     struct net_device *dev = pdev;
0681     struct port *port = netdev_priv(dev);
0682 
0683 #if DEBUG_RX
0684     printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
0685 #endif
0686     qmgr_disable_irq(port->plat->rxq);
0687     napi_schedule(&port->napi);
0688 }
0689 
0690 static int eth_poll(struct napi_struct *napi, int budget)
0691 {
0692     struct port *port = container_of(napi, struct port, napi);
0693     struct net_device *dev = port->netdev;
0694     unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
0695     int received = 0;
0696 
0697 #if DEBUG_RX
0698     netdev_debug(dev, "eth_poll\n");
0699 #endif
0700 
0701     while (received < budget) {
0702         struct sk_buff *skb;
0703         struct desc *desc;
0704         int n;
0705 #ifdef __ARMEB__
0706         struct sk_buff *temp;
0707         u32 phys;
0708 #endif
0709 
0710         if ((n = queue_get_desc(rxq, port, 0)) < 0) {
0711 #if DEBUG_RX
0712             netdev_debug(dev, "eth_poll napi_complete\n");
0713 #endif
0714             napi_complete(napi);
0715             qmgr_enable_irq(rxq);
0716             if (!qmgr_stat_below_low_watermark(rxq) &&
0717                 napi_reschedule(napi)) { /* not empty again */
0718 #if DEBUG_RX
0719                 netdev_debug(dev, "eth_poll napi_reschedule succeeded\n");
0720 #endif
0721                 qmgr_disable_irq(rxq);
0722                 continue;
0723             }
0724 #if DEBUG_RX
0725             netdev_debug(dev, "eth_poll all done\n");
0726 #endif
0727             return received; /* all work done */
0728         }
0729 
0730         desc = rx_desc_ptr(port, n);
0731 
0732 #ifdef __ARMEB__
0733         if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
0734             phys = dma_map_single(&dev->dev, skb->data,
0735                           RX_BUFF_SIZE, DMA_FROM_DEVICE);
0736             if (dma_mapping_error(&dev->dev, phys)) {
0737                 dev_kfree_skb(skb);
0738                 skb = NULL;
0739             }
0740         }
0741 #else
0742         skb = netdev_alloc_skb(dev,
0743                        ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
0744 #endif
0745 
0746         if (!skb) {
0747             dev->stats.rx_dropped++;
0748             /* put the desc back on RX-ready queue */
0749             desc->buf_len = MAX_MRU;
0750             desc->pkt_len = 0;
0751             queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
0752             continue;
0753         }
0754 
0755         /* process received frame */
0756 #ifdef __ARMEB__
0757         temp = skb;
0758         skb = port->rx_buff_tab[n];
0759         dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
0760                  RX_BUFF_SIZE, DMA_FROM_DEVICE);
0761 #else
0762         dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
0763                     RX_BUFF_SIZE, DMA_FROM_DEVICE);
0764         memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
0765                   ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
0766 #endif
0767         skb_reserve(skb, NET_IP_ALIGN);
0768         skb_put(skb, desc->pkt_len);
0769 
0770         debug_pkt(dev, "eth_poll", skb->data, skb->len);
0771 
0772         ixp_rx_timestamp(port, skb);
0773         skb->protocol = eth_type_trans(skb, dev);
0774         dev->stats.rx_packets++;
0775         dev->stats.rx_bytes += skb->len;
0776         netif_receive_skb(skb);
0777 
0778         /* put the new buffer on RX-free queue */
0779 #ifdef __ARMEB__
0780         port->rx_buff_tab[n] = temp;
0781         desc->data = phys + NET_IP_ALIGN;
0782 #endif
0783         desc->buf_len = MAX_MRU;
0784         desc->pkt_len = 0;
0785         queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
0786         received++;
0787     }
0788 
0789 #if DEBUG_RX
0790     netdev_debug(dev, "eth_poll(): end, not all work done\n");
0791 #endif
0792     return received;        /* not all work done */
0793 }
0794 
0795 
0796 static void eth_txdone_irq(void *unused)
0797 {
0798     u32 phys;
0799 
0800 #if DEBUG_TX
0801     printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
0802 #endif
0803     while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
0804         u32 npe_id, n_desc;
0805         struct port *port;
0806         struct desc *desc;
0807         int start;
0808 
0809         npe_id = phys & 3;
0810         BUG_ON(npe_id >= MAX_NPES);
0811         port = npe_port_tab[npe_id];
0812         BUG_ON(!port);
0813         phys &= ~0x1F; /* mask out non-address bits */
0814         n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
0815         BUG_ON(n_desc >= TX_DESCS);
0816         desc = tx_desc_ptr(port, n_desc);
0817         debug_desc(phys, desc);
0818 
0819         if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
0820             port->netdev->stats.tx_packets++;
0821             port->netdev->stats.tx_bytes += desc->pkt_len;
0822 
0823             dma_unmap_tx(port, desc);
0824 #if DEBUG_TX
0825             printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
0826                    port->netdev->name, port->tx_buff_tab[n_desc]);
0827 #endif
0828             free_buffer_irq(port->tx_buff_tab[n_desc]);
0829             port->tx_buff_tab[n_desc] = NULL;
0830         }
0831 
0832         start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
0833         queue_put_desc(port->plat->txreadyq, phys, desc);
0834         if (start) { /* TX-ready queue was empty */
0835 #if DEBUG_TX
0836             printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
0837                    port->netdev->name);
0838 #endif
0839             netif_wake_queue(port->netdev);
0840         }
0841     }
0842 }
0843 
0844 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
0845 {
0846     struct port *port = netdev_priv(dev);
0847     unsigned int txreadyq = port->plat->txreadyq;
0848     int len, offset, bytes, n;
0849     void *mem;
0850     u32 phys;
0851     struct desc *desc;
0852 
0853 #if DEBUG_TX
0854     netdev_debug(dev, "eth_xmit\n");
0855 #endif
0856 
0857     if (unlikely(skb->len > MAX_MRU)) {
0858         dev_kfree_skb(skb);
0859         dev->stats.tx_errors++;
0860         return NETDEV_TX_OK;
0861     }
0862 
0863     debug_pkt(dev, "eth_xmit", skb->data, skb->len);
0864 
0865     len = skb->len;
0866 #ifdef __ARMEB__
0867     offset = 0; /* no need to keep alignment */
0868     bytes = len;
0869     mem = skb->data;
0870 #else
0871     offset = (uintptr_t)skb->data & 3; /* keep 32-bit alignment */
0872     bytes = ALIGN(offset + len, 4);
0873     if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
0874         dev_kfree_skb(skb);
0875         dev->stats.tx_dropped++;
0876         return NETDEV_TX_OK;
0877     }
0878     memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
0879 #endif
0880 
0881     phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
0882     if (dma_mapping_error(&dev->dev, phys)) {
0883         dev_kfree_skb(skb);
0884 #ifndef __ARMEB__
0885         kfree(mem);
0886 #endif
0887         dev->stats.tx_dropped++;
0888         return NETDEV_TX_OK;
0889     }
0890 
0891     n = queue_get_desc(txreadyq, port, 1);
0892     BUG_ON(n < 0);
0893     desc = tx_desc_ptr(port, n);
0894 
0895 #ifdef __ARMEB__
0896     port->tx_buff_tab[n] = skb;
0897 #else
0898     port->tx_buff_tab[n] = mem;
0899 #endif
0900     desc->data = phys + offset;
0901     desc->buf_len = desc->pkt_len = len;
0902 
0903     /* NPE firmware pads short frames with zeros internally */
0904     wmb();
0905     queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
0906 
0907     if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
0908 #if DEBUG_TX
0909         netdev_debug(dev, "eth_xmit queue full\n");
0910 #endif
0911         netif_stop_queue(dev);
0912         /* we could miss TX ready interrupt */
0913         /* really empty in fact */
0914         if (!qmgr_stat_below_low_watermark(txreadyq)) {
0915 #if DEBUG_TX
0916             netdev_debug(dev, "eth_xmit ready again\n");
0917 #endif
0918             netif_wake_queue(dev);
0919         }
0920     }
0921 
0922 #if DEBUG_TX
0923     netdev_debug(dev, "eth_xmit end\n");
0924 #endif
0925 
0926     ixp_tx_timestamp(port, skb);
0927     skb_tx_timestamp(skb);
0928 
0929 #ifndef __ARMEB__
0930     dev_kfree_skb(skb);
0931 #endif
0932     return NETDEV_TX_OK;
0933 }
0934 
0935 
0936 static void eth_set_mcast_list(struct net_device *dev)
0937 {
0938     struct port *port = netdev_priv(dev);
0939     struct netdev_hw_addr *ha;
0940     u8 diffs[ETH_ALEN], *addr;
0941     int i;
0942     static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
0943 
0944     if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) {
0945         for (i = 0; i < ETH_ALEN; i++) {
0946             __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
0947             __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
0948         }
0949         __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
0950             &port->regs->rx_control[0]);
0951         return;
0952     }
0953 
0954     if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
0955         __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
0956                  &port->regs->rx_control[0]);
0957         return;
0958     }
0959 
0960     eth_zero_addr(diffs);
0961 
0962     addr = NULL;
0963     netdev_for_each_mc_addr(ha, dev) {
0964         if (!addr)
0965             addr = ha->addr; /* first MAC address */
0966         for (i = 0; i < ETH_ALEN; i++)
0967             diffs[i] |= addr[i] ^ ha->addr[i];
0968     }
0969 
0970     for (i = 0; i < ETH_ALEN; i++) {
0971         __raw_writel(addr[i], &port->regs->mcast_addr[i]);
0972         __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
0973     }
0974 
0975     __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
0976              &port->regs->rx_control[0]);
0977 }
0978 
0979 
0980 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
0981 {
0982     if (!netif_running(dev))
0983         return -EINVAL;
0984 
0985     if (cpu_is_ixp46x()) {
0986         if (cmd == SIOCSHWTSTAMP)
0987             return hwtstamp_set(dev, req);
0988         if (cmd == SIOCGHWTSTAMP)
0989             return hwtstamp_get(dev, req);
0990     }
0991 
0992     return phy_mii_ioctl(dev->phydev, req, cmd);
0993 }
0994 
0995 /* ethtool support */
0996 
0997 static void ixp4xx_get_drvinfo(struct net_device *dev,
0998                    struct ethtool_drvinfo *info)
0999 {
1000     struct port *port = netdev_priv(dev);
1001 
1002     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1003     snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
1004          port->firmware[0], port->firmware[1],
1005          port->firmware[2], port->firmware[3]);
1006     strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
1007 }
1008 
1009 static int ixp4xx_get_ts_info(struct net_device *dev,
1010                   struct ethtool_ts_info *info)
1011 {
1012     struct port *port = netdev_priv(dev);
1013 
1014     if (port->phc_index < 0)
1015         ixp46x_ptp_find(&port->timesync_regs, &port->phc_index);
1016 
1017     info->phc_index = port->phc_index;
1018 
1019     if (info->phc_index < 0) {
1020         info->so_timestamping =
1021             SOF_TIMESTAMPING_TX_SOFTWARE |
1022             SOF_TIMESTAMPING_RX_SOFTWARE |
1023             SOF_TIMESTAMPING_SOFTWARE;
1024         return 0;
1025     }
1026     info->so_timestamping =
1027         SOF_TIMESTAMPING_TX_HARDWARE |
1028         SOF_TIMESTAMPING_RX_HARDWARE |
1029         SOF_TIMESTAMPING_RAW_HARDWARE;
1030     info->tx_types =
1031         (1 << HWTSTAMP_TX_OFF) |
1032         (1 << HWTSTAMP_TX_ON);
1033     info->rx_filters =
1034         (1 << HWTSTAMP_FILTER_NONE) |
1035         (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1036         (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
1037     return 0;
1038 }
1039 
1040 static const struct ethtool_ops ixp4xx_ethtool_ops = {
1041     .get_drvinfo = ixp4xx_get_drvinfo,
1042     .nway_reset = phy_ethtool_nway_reset,
1043     .get_link = ethtool_op_get_link,
1044     .get_ts_info = ixp4xx_get_ts_info,
1045     .get_link_ksettings = phy_ethtool_get_link_ksettings,
1046     .set_link_ksettings = phy_ethtool_set_link_ksettings,
1047 };
1048 
1049 
1050 static int request_queues(struct port *port)
1051 {
1052     int err;
1053 
1054     err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
1055                  "%s:RX-free", port->netdev->name);
1056     if (err)
1057         return err;
1058 
1059     err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
1060                  "%s:RX", port->netdev->name);
1061     if (err)
1062         goto rel_rxfree;
1063 
1064     err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
1065                  "%s:TX", port->netdev->name);
1066     if (err)
1067         goto rel_rx;
1068 
1069     err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
1070                  "%s:TX-ready", port->netdev->name);
1071     if (err)
1072         goto rel_tx;
1073 
1074     /* TX-done queue handles skbs sent out by the NPEs */
1075     if (!ports_open) {
1076         err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
1077                      "%s:TX-done", DRV_NAME);
1078         if (err)
1079             goto rel_txready;
1080     }
1081     return 0;
1082 
1083 rel_txready:
1084     qmgr_release_queue(port->plat->txreadyq);
1085 rel_tx:
1086     qmgr_release_queue(TX_QUEUE(port->id));
1087 rel_rx:
1088     qmgr_release_queue(port->plat->rxq);
1089 rel_rxfree:
1090     qmgr_release_queue(RXFREE_QUEUE(port->id));
1091     printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1092            port->netdev->name);
1093     return err;
1094 }
1095 
1096 static void release_queues(struct port *port)
1097 {
1098     qmgr_release_queue(RXFREE_QUEUE(port->id));
1099     qmgr_release_queue(port->plat->rxq);
1100     qmgr_release_queue(TX_QUEUE(port->id));
1101     qmgr_release_queue(port->plat->txreadyq);
1102 
1103     if (!ports_open)
1104         qmgr_release_queue(TXDONE_QUEUE);
1105 }
1106 
1107 static int init_queues(struct port *port)
1108 {
1109     int i;
1110 
1111     if (!ports_open) {
1112         dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
1113                        POOL_ALLOC_SIZE, 32, 0);
1114         if (!dma_pool)
1115             return -ENOMEM;
1116     }
1117 
1118     port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL, &port->desc_tab_phys);
1119     if (!port->desc_tab)
1120         return -ENOMEM;
1121     memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1122     memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1123 
1124     /* Setup RX buffers */
1125     for (i = 0; i < RX_DESCS; i++) {
1126         struct desc *desc = rx_desc_ptr(port, i);
1127         buffer_t *buff; /* skb or kmalloc()ated memory */
1128         void *data;
1129 #ifdef __ARMEB__
1130         if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1131             return -ENOMEM;
1132         data = buff->data;
1133 #else
1134         if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1135             return -ENOMEM;
1136         data = buff;
1137 #endif
1138         desc->buf_len = MAX_MRU;
1139         desc->data = dma_map_single(&port->netdev->dev, data,
1140                         RX_BUFF_SIZE, DMA_FROM_DEVICE);
1141         if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1142             free_buffer(buff);
1143             return -EIO;
1144         }
1145         desc->data += NET_IP_ALIGN;
1146         port->rx_buff_tab[i] = buff;
1147     }
1148 
1149     return 0;
1150 }
1151 
1152 static void destroy_queues(struct port *port)
1153 {
1154     int i;
1155 
1156     if (port->desc_tab) {
1157         for (i = 0; i < RX_DESCS; i++) {
1158             struct desc *desc = rx_desc_ptr(port, i);
1159             buffer_t *buff = port->rx_buff_tab[i];
1160             if (buff) {
1161                 dma_unmap_single(&port->netdev->dev,
1162                          desc->data - NET_IP_ALIGN,
1163                          RX_BUFF_SIZE, DMA_FROM_DEVICE);
1164                 free_buffer(buff);
1165             }
1166         }
1167         for (i = 0; i < TX_DESCS; i++) {
1168             struct desc *desc = tx_desc_ptr(port, i);
1169             buffer_t *buff = port->tx_buff_tab[i];
1170             if (buff) {
1171                 dma_unmap_tx(port, desc);
1172                 free_buffer(buff);
1173             }
1174         }
1175         dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1176         port->desc_tab = NULL;
1177     }
1178 
1179     if (!ports_open && dma_pool) {
1180         dma_pool_destroy(dma_pool);
1181         dma_pool = NULL;
1182     }
1183 }
1184 
1185 static int eth_open(struct net_device *dev)
1186 {
1187     struct port *port = netdev_priv(dev);
1188     struct npe *npe = port->npe;
1189     struct msg msg;
1190     int i, err;
1191 
1192     if (!npe_running(npe)) {
1193         err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1194         if (err)
1195             return err;
1196 
1197         if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1198             netdev_err(dev, "%s not responding\n", npe_name(npe));
1199             return -EIO;
1200         }
1201         port->firmware[0] = msg.byte4;
1202         port->firmware[1] = msg.byte5;
1203         port->firmware[2] = msg.byte6;
1204         port->firmware[3] = msg.byte7;
1205     }
1206 
1207     memset(&msg, 0, sizeof(msg));
1208     msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1209     msg.eth_id = port->id;
1210     msg.byte5 = port->plat->rxq | 0x80;
1211     msg.byte7 = port->plat->rxq << 4;
1212     for (i = 0; i < 8; i++) {
1213         msg.byte3 = i;
1214         if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1215             return -EIO;
1216     }
1217 
1218     msg.cmd = NPE_EDB_SETPORTADDRESS;
1219     msg.eth_id = PHYSICAL_ID(port->id);
1220     msg.byte2 = dev->dev_addr[0];
1221     msg.byte3 = dev->dev_addr[1];
1222     msg.byte4 = dev->dev_addr[2];
1223     msg.byte5 = dev->dev_addr[3];
1224     msg.byte6 = dev->dev_addr[4];
1225     msg.byte7 = dev->dev_addr[5];
1226     if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1227         return -EIO;
1228 
1229     memset(&msg, 0, sizeof(msg));
1230     msg.cmd = NPE_FW_SETFIREWALLMODE;
1231     msg.eth_id = port->id;
1232     if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1233         return -EIO;
1234 
1235     if ((err = request_queues(port)) != 0)
1236         return err;
1237 
1238     if ((err = init_queues(port)) != 0) {
1239         destroy_queues(port);
1240         release_queues(port);
1241         return err;
1242     }
1243 
1244     port->speed = 0;    /* force "link up" message */
1245     phy_start(dev->phydev);
1246 
1247     for (i = 0; i < ETH_ALEN; i++)
1248         __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1249     __raw_writel(0x08, &port->regs->random_seed);
1250     __raw_writel(0x12, &port->regs->partial_empty_threshold);
1251     __raw_writel(0x30, &port->regs->partial_full_threshold);
1252     __raw_writel(0x08, &port->regs->tx_start_bytes);
1253     __raw_writel(0x15, &port->regs->tx_deferral);
1254     __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1255     __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1256     __raw_writel(0x80, &port->regs->slot_time);
1257     __raw_writel(0x01, &port->regs->int_clock_threshold);
1258 
1259     /* Populate queues with buffers, no failure after this point */
1260     for (i = 0; i < TX_DESCS; i++)
1261         queue_put_desc(port->plat->txreadyq,
1262                    tx_desc_phys(port, i), tx_desc_ptr(port, i));
1263 
1264     for (i = 0; i < RX_DESCS; i++)
1265         queue_put_desc(RXFREE_QUEUE(port->id),
1266                    rx_desc_phys(port, i), rx_desc_ptr(port, i));
1267 
1268     __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1269     __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1270     __raw_writel(0, &port->regs->rx_control[1]);
1271     __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1272 
1273     napi_enable(&port->napi);
1274     eth_set_mcast_list(dev);
1275     netif_start_queue(dev);
1276 
1277     qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1278              eth_rx_irq, dev);
1279     if (!ports_open) {
1280         qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1281                  eth_txdone_irq, NULL);
1282         qmgr_enable_irq(TXDONE_QUEUE);
1283     }
1284     ports_open++;
1285     /* we may already have RX data, enables IRQ */
1286     napi_schedule(&port->napi);
1287     return 0;
1288 }
1289 
1290 static int eth_close(struct net_device *dev)
1291 {
1292     struct port *port = netdev_priv(dev);
1293     struct msg msg;
1294     int buffs = RX_DESCS; /* allocated RX buffers */
1295     int i;
1296 
1297     ports_open--;
1298     qmgr_disable_irq(port->plat->rxq);
1299     napi_disable(&port->napi);
1300     netif_stop_queue(dev);
1301 
1302     while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1303         buffs--;
1304 
1305     memset(&msg, 0, sizeof(msg));
1306     msg.cmd = NPE_SETLOOPBACK_MODE;
1307     msg.eth_id = port->id;
1308     msg.byte3 = 1;
1309     if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1310         netdev_crit(dev, "unable to enable loopback\n");
1311 
1312     i = 0;
1313     do {            /* drain RX buffers */
1314         while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1315             buffs--;
1316         if (!buffs)
1317             break;
1318         if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1319             /* we have to inject some packet */
1320             struct desc *desc;
1321             u32 phys;
1322             int n = queue_get_desc(port->plat->txreadyq, port, 1);
1323             BUG_ON(n < 0);
1324             desc = tx_desc_ptr(port, n);
1325             phys = tx_desc_phys(port, n);
1326             desc->buf_len = desc->pkt_len = 1;
1327             wmb();
1328             queue_put_desc(TX_QUEUE(port->id), phys, desc);
1329         }
1330         udelay(1);
1331     } while (++i < MAX_CLOSE_WAIT);
1332 
1333     if (buffs)
1334         netdev_crit(dev, "unable to drain RX queue, %i buffer(s)"
1335                 " left in NPE\n", buffs);
1336 #if DEBUG_CLOSE
1337     if (!buffs)
1338         netdev_debug(dev, "draining RX queue took %i cycles\n", i);
1339 #endif
1340 
1341     buffs = TX_DESCS;
1342     while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1343         buffs--; /* cancel TX */
1344 
1345     i = 0;
1346     do {
1347         while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1348             buffs--;
1349         if (!buffs)
1350             break;
1351     } while (++i < MAX_CLOSE_WAIT);
1352 
1353     if (buffs)
1354         netdev_crit(dev, "unable to drain TX queue, %i buffer(s) "
1355                 "left in NPE\n", buffs);
1356 #if DEBUG_CLOSE
1357     if (!buffs)
1358         netdev_debug(dev, "draining TX queues took %i cycles\n", i);
1359 #endif
1360 
1361     msg.byte3 = 0;
1362     if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1363         netdev_crit(dev, "unable to disable loopback\n");
1364 
1365     phy_stop(dev->phydev);
1366 
1367     if (!ports_open)
1368         qmgr_disable_irq(TXDONE_QUEUE);
1369     destroy_queues(port);
1370     release_queues(port);
1371     return 0;
1372 }
1373 
1374 static const struct net_device_ops ixp4xx_netdev_ops = {
1375     .ndo_open = eth_open,
1376     .ndo_stop = eth_close,
1377     .ndo_start_xmit = eth_xmit,
1378     .ndo_set_rx_mode = eth_set_mcast_list,
1379     .ndo_eth_ioctl = eth_ioctl,
1380     .ndo_set_mac_address = eth_mac_addr,
1381     .ndo_validate_addr = eth_validate_addr,
1382 };
1383 
1384 static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)
1385 {
1386     struct device_node *np = dev->of_node;
1387     struct of_phandle_args queue_spec;
1388     struct of_phandle_args npe_spec;
1389     struct device_node *mdio_np;
1390     struct eth_plat_info *plat;
1391     u8 mac[ETH_ALEN];
1392     int ret;
1393 
1394     plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
1395     if (!plat)
1396         return NULL;
1397 
1398     ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0,
1399                            &npe_spec);
1400     if (ret) {
1401         dev_err(dev, "no NPE engine specified\n");
1402         return NULL;
1403     }
1404     /* NPE ID 0x00, 0x10, 0x20... */
1405     plat->npe = (npe_spec.args[0] << 4);
1406 
1407     /* Check if this device has an MDIO bus */
1408     mdio_np = of_get_child_by_name(np, "mdio");
1409     if (mdio_np) {
1410         plat->has_mdio = true;
1411         mdio_bus_np = mdio_np;
1412         /* DO NOT put the mdio_np, it will be used */
1413     }
1414 
1415     /* Get the rx queue as a resource from queue manager */
1416     ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0,
1417                            &queue_spec);
1418     if (ret) {
1419         dev_err(dev, "no rx queue phandle\n");
1420         return NULL;
1421     }
1422     plat->rxq = queue_spec.args[0];
1423 
1424     /* Get the txready queue as resource from queue manager */
1425     ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0,
1426                            &queue_spec);
1427     if (ret) {
1428         dev_err(dev, "no txready queue phandle\n");
1429         return NULL;
1430     }
1431     plat->txreadyq = queue_spec.args[0];
1432 
1433     ret = of_get_mac_address(np, mac);
1434     if (!ret) {
1435         dev_info(dev, "Setting macaddr from DT %pM\n", mac);
1436         memcpy(plat->hwaddr, mac, ETH_ALEN);
1437     }
1438 
1439     return plat;
1440 }
1441 
1442 static int ixp4xx_eth_probe(struct platform_device *pdev)
1443 {
1444     struct phy_device *phydev = NULL;
1445     struct device *dev = &pdev->dev;
1446     struct device_node *np = dev->of_node;
1447     struct eth_plat_info *plat;
1448     struct net_device *ndev;
1449     struct port *port;
1450     int err;
1451 
1452     plat = ixp4xx_of_get_platdata(dev);
1453     if (!plat)
1454         return -ENODEV;
1455 
1456     if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port))))
1457         return -ENOMEM;
1458 
1459     SET_NETDEV_DEV(ndev, dev);
1460     port = netdev_priv(ndev);
1461     port->netdev = ndev;
1462     port->id = plat->npe;
1463     port->phc_index = -1;
1464 
1465     /* Get the port resource and remap */
1466     port->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1467     if (IS_ERR(port->regs))
1468         return PTR_ERR(port->regs);
1469 
1470     /* Register the MDIO bus if we have it */
1471     if (plat->has_mdio) {
1472         err = ixp4xx_mdio_register(port->regs);
1473         if (err) {
1474             dev_err(dev, "failed to register MDIO bus\n");
1475             return err;
1476         }
1477     }
1478     /* If the instance with the MDIO bus has not yet appeared,
1479      * defer probing until it gets probed.
1480      */
1481     if (!mdio_bus)
1482         return -EPROBE_DEFER;
1483 
1484     ndev->netdev_ops = &ixp4xx_netdev_ops;
1485     ndev->ethtool_ops = &ixp4xx_ethtool_ops;
1486     ndev->tx_queue_len = 100;
1487     /* Inherit the DMA masks from the platform device */
1488     ndev->dev.dma_mask = dev->dma_mask;
1489     ndev->dev.coherent_dma_mask = dev->coherent_dma_mask;
1490 
1491     netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT);
1492 
1493     if (!(port->npe = npe_request(NPE_ID(port->id))))
1494         return -EIO;
1495 
1496     port->plat = plat;
1497     npe_port_tab[NPE_ID(port->id)] = port;
1498     if (is_valid_ether_addr(plat->hwaddr))
1499         eth_hw_addr_set(ndev, plat->hwaddr);
1500     else
1501         eth_hw_addr_random(ndev);
1502 
1503     platform_set_drvdata(pdev, ndev);
1504 
1505     __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1506              &port->regs->core_control);
1507     udelay(50);
1508     __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1509     udelay(50);
1510 
1511     phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link);
1512     if (!phydev) {
1513         err = -ENODEV;
1514         dev_err(dev, "no phydev\n");
1515         goto err_free_mem;
1516     }
1517 
1518     phydev->irq = PHY_POLL;
1519 
1520     if ((err = register_netdev(ndev)))
1521         goto err_phy_dis;
1522 
1523     netdev_info(ndev, "%s: MII PHY %i on %s\n", ndev->name, plat->phy,
1524             npe_name(port->npe));
1525 
1526     return 0;
1527 
1528 err_phy_dis:
1529     phy_disconnect(phydev);
1530 err_free_mem:
1531     npe_port_tab[NPE_ID(port->id)] = NULL;
1532     npe_release(port->npe);
1533     return err;
1534 }
1535 
1536 static int ixp4xx_eth_remove(struct platform_device *pdev)
1537 {
1538     struct net_device *ndev = platform_get_drvdata(pdev);
1539     struct phy_device *phydev = ndev->phydev;
1540     struct port *port = netdev_priv(ndev);
1541 
1542     unregister_netdev(ndev);
1543     phy_disconnect(phydev);
1544     ixp4xx_mdio_remove();
1545     npe_port_tab[NPE_ID(port->id)] = NULL;
1546     npe_release(port->npe);
1547     return 0;
1548 }
1549 
1550 static const struct of_device_id ixp4xx_eth_of_match[] = {
1551     {
1552         .compatible = "intel,ixp4xx-ethernet",
1553     },
1554     { },
1555 };
1556 
1557 static struct platform_driver ixp4xx_eth_driver = {
1558     .driver = {
1559         .name = DRV_NAME,
1560         .of_match_table = of_match_ptr(ixp4xx_eth_of_match),
1561     },
1562     .probe      = ixp4xx_eth_probe,
1563     .remove     = ixp4xx_eth_remove,
1564 };
1565 module_platform_driver(ixp4xx_eth_driver);
1566 
1567 MODULE_AUTHOR("Krzysztof Halasa");
1568 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1569 MODULE_LICENSE("GPL v2");
1570 MODULE_ALIAS("platform:ixp4xx_eth");
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