ethernet/xscale/ixp46x_ts.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * PTP 1588 clock using the IXP46X
0004  *
0005  * Copyright (C) 2010 OMICRON electronics GmbH
0006  */
0007
0008 #ifndef _IXP46X_TS_H_
0009 #define _IXP46X_TS_H_
0010
0011 #define DEFAULT_ADDEND 0xF0000029
0012 #define TICKS_NS_SHIFT 4
0013
0014 struct ixp46x_channel_ctl {
0015     u32 ch_control;  /* 0x40 Time Synchronization Channel Control */
0016     u32 ch_event;    /* 0x44 Time Synchronization Channel Event */
0017     u32 tx_snap_lo;  /* 0x48 Transmit Snapshot Low Register */
0018     u32 tx_snap_hi;  /* 0x4C Transmit Snapshot High Register */
0019     u32 rx_snap_lo;  /* 0x50 Receive Snapshot Low Register */
0020     u32 rx_snap_hi;  /* 0x54 Receive Snapshot High Register */
0021     u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
0022     u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
0023 };
0024
0025 struct ixp46x_ts_regs {
0026     u32 control;     /* 0x00 Time Sync Control Register */
0027     u32 event;       /* 0x04 Time Sync Event Register */
0028     u32 addend;      /* 0x08 Time Sync Addend Register */
0029     u32 accum;       /* 0x0C Time Sync Accumulator Register */
0030     u32 test;        /* 0x10 Time Sync Test Register */
0031     u32 unused;      /* 0x14 */
0032     u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
0033     u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
0034     u32 systime_lo;  /* 0x20 SystemTime_Low Register */
0035     u32 systime_hi;  /* 0x24 SystemTime_High Register */
0036     u32 trgt_lo;     /* 0x28 TargetTime_Low Register */
0037     u32 trgt_hi;     /* 0x2C TargetTime_High Register */
0038     u32 asms_lo;     /* 0x30 Auxiliary Slave Mode Snapshot Low  */
0039     u32 asms_hi;     /* 0x34 Auxiliary Slave Mode Snapshot High */
0040     u32 amms_lo;     /* 0x38 Auxiliary Master Mode Snapshot Low */
0041     u32 amms_hi;     /* 0x3C Auxiliary Master Mode Snapshot High */
0042
0043     struct ixp46x_channel_ctl channel[3];
0044 };
0045
0046 /* 0x00 Time Sync Control Register Bits */
0047 #define TSCR_AMM (1<<3)
0048 #define TSCR_ASM (1<<2)
0049 #define TSCR_TTM (1<<1)
0050 #define TSCR_RST (1<<0)
0051
0052 /* 0x04 Time Sync Event Register Bits */
0053 #define TSER_SNM (1<<3)
0054 #define TSER_SNS (1<<2)
0055 #define TTIPEND  (1<<1)
0056
0057 /* 0x40 Time Synchronization Channel Control Register Bits */
0058 #define MASTER_MODE   (1<<0)
0059 #define TIMESTAMP_ALL (1<<1)
0060
0061 /* 0x44 Time Synchronization Channel Event Register Bits */
0062 #define TX_SNAPSHOT_LOCKED (1<<0)
0063 #define RX_SNAPSHOT_LOCKED (1<<1)
0064
0065 #if IS_ENABLED(CONFIG_PTP_1588_CLOCK_IXP46X)
0066 int ixp46x_ptp_find(struct ixp46x_ts_regs *__iomem *regs, int *phc_index);
0067 #else
0068 static inline int ixp46x_ptp_find(struct ixp46x_ts_regs *__iomem *regs, int *phc_index)
0069 {
0070     *regs = NULL;
0071     *phc_index = -1;
0072
0073     return -ENODEV;
0074 }
0075 #endif
0076
0077 #endif