ethernet/xilinx/ll_temac_mdio.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * MDIO bus driver for the Xilinx TEMAC device
0004  *
0005  * Copyright (c) 2009 Secret Lab Technologies, Ltd.
0006  */
0007
0008 #include <linux/io.h>
0009 #include <linux/netdevice.h>
0010 #include <linux/mutex.h>
0011 #include <linux/phy.h>
0012 #include <linux/of.h>
0013 #include <linux/of_device.h>
0014 #include <linux/of_address.h>
0015 #include <linux/slab.h>
0016 #include <linux/of_mdio.h>
0017 #include <linux/platform_data/xilinx-ll-temac.h>
0018
0019 #include "ll_temac.h"
0020
0021 /* ---------------------------------------------------------------------
0022  * MDIO Bus functions
0023  */
0024 static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
0025 {
0026     struct temac_local *lp = bus->priv;
0027     u32 rc;
0028     unsigned long flags;
0029
0030     /* Write the PHY address to the MIIM Access Initiator register.
0031      * When the transfer completes, the PHY register value will appear
0032      * in the LSW0 register */
0033     spin_lock_irqsave(lp->indirect_lock, flags);
0034     temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg);
0035     rc = temac_indirect_in32_locked(lp, XTE_MIIMAI_OFFSET);
0036     spin_unlock_irqrestore(lp->indirect_lock, flags);
0037
0038     dev_dbg(lp->dev, "temac_mdio_read(phy_id=%i, reg=%x) == %x\n",
0039         phy_id, reg, rc);
0040
0041     return rc;
0042 }
0043
0044 static int temac_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
0045 {
0046     struct temac_local *lp = bus->priv;
0047     unsigned long flags;
0048
0049     dev_dbg(lp->dev, "temac_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
0050         phy_id, reg, val);
0051
0052     /* First write the desired value into the write data register
0053      * and then write the address into the access initiator register
0054      */
0055     spin_lock_irqsave(lp->indirect_lock, flags);
0056     temac_indirect_out32_locked(lp, XTE_MGTDR_OFFSET, val);
0057     temac_indirect_out32_locked(lp, XTE_MIIMAI_OFFSET, (phy_id << 5) | reg);
0058     spin_unlock_irqrestore(lp->indirect_lock, flags);
0059
0060     return 0;
0061 }
0062
0063 int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev)
0064 {
0065     struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev);
0066     struct device_node *np = dev_of_node(&pdev->dev);
0067     struct mii_bus *bus;
0068     u32 bus_hz;
0069     int clk_div;
0070     int rc;
0071     struct resource res;
0072
0073     /* Get MDIO bus frequency (if specified) */
0074     bus_hz = 0;
0075     if (np)
0076         of_property_read_u32(np, "clock-frequency", &bus_hz);
0077     else if (pdata)
0078         bus_hz = pdata->mdio_clk_freq;
0079
0080     /* Calculate a reasonable divisor for the clock rate */
0081     clk_div = 0x3f; /* worst-case default setting */
0082     if (bus_hz != 0) {
0083         clk_div = bus_hz / (2500 * 1000 * 2) - 1;
0084         if (clk_div < 1)
0085             clk_div = 1;
0086         if (clk_div > 0x3f)
0087             clk_div = 0x3f;
0088     }
0089
0090     /* Enable the MDIO bus by asserting the enable bit and writing
0091      * in the clock config */
0092     temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div);
0093
0094     bus = devm_mdiobus_alloc(&pdev->dev);
0095     if (!bus)
0096         return -ENOMEM;
0097
0098     if (np) {
0099         of_address_to_resource(np, 0, &res);
0100         snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
0101              (unsigned long long)res.start);
0102     } else if (pdata) {
0103         snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
0104              pdata->mdio_bus_id);
0105     }
0106
0107     bus->priv = lp;
0108     bus->name = "Xilinx TEMAC MDIO";
0109     bus->read = temac_mdio_read;
0110     bus->write = temac_mdio_write;
0111     bus->parent = lp->dev;
0112
0113     lp->mii_bus = bus;
0114
0115     rc = of_mdiobus_register(bus, np);
0116     if (rc)
0117         return rc;
0118
0119     dev_dbg(lp->dev, "MDIO bus registered;  MC:%x\n",
0120         temac_indirect_in32(lp, XTE_MC_OFFSET));
0121     return 0;
0122 }
0123
0124 void temac_mdio_teardown(struct temac_local *lp)
0125 {
0126     mdiobus_unregister(lp->mii_bus);
0127 }