ethernet/xilinx/ll_temac.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 #ifndef XILINX_LL_TEMAC_H
0004 #define XILINX_LL_TEMAC_H
0005
0006 #include <linux/netdevice.h>
0007 #include <linux/of.h>
0008 #include <linux/spinlock.h>
0009
0010 #ifdef CONFIG_PPC_DCR
0011 #include <asm/dcr.h>
0012 #include <asm/dcr-regs.h>
0013 #endif
0014
0015 /* packet size info */
0016 #define XTE_HDR_SIZE            14      /* size of Ethernet header */
0017 #define XTE_TRL_SIZE            4       /* size of Ethernet trailer (FCS) */
0018 #define XTE_JUMBO_MTU           9000
0019 #define XTE_MAX_JUMBO_FRAME_SIZE    (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE)
0020
0021 /*  Configuration options */
0022
0023 /*  Accept all incoming packets.
0024  *  This option defaults to disabled (cleared) */
0025 #define XTE_OPTION_PROMISC                      (1 << 0)
0026 /*  Jumbo frame support for Tx & Rx.
0027  *  This option defaults to disabled (cleared) */
0028 #define XTE_OPTION_JUMBO                        (1 << 1)
0029 /*  VLAN Rx & Tx frame support.
0030  *  This option defaults to disabled (cleared) */
0031 #define XTE_OPTION_VLAN                         (1 << 2)
0032 /*  Enable recognition of flow control frames on Rx
0033  *  This option defaults to enabled (set) */
0034 #define XTE_OPTION_FLOW_CONTROL                 (1 << 4)
0035 /*  Strip FCS and PAD from incoming frames.
0036  *  Note: PAD from VLAN frames is not stripped.
0037  *  This option defaults to disabled (set) */
0038 #define XTE_OPTION_FCS_STRIP                    (1 << 5)
0039 /*  Generate FCS field and add PAD automatically for outgoing frames.
0040  *  This option defaults to enabled (set) */
0041 #define XTE_OPTION_FCS_INSERT                   (1 << 6)
0042 /*  Enable Length/Type error checking for incoming frames. When this option is
0043 set, the MAC will filter frames that have a mismatched type/length field
0044 and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
0045 types of frames are encountered. When this option is cleared, the MAC will
0046 allow these types of frames to be received.
0047 This option defaults to enabled (set) */
0048 #define XTE_OPTION_LENTYPE_ERR                  (1 << 7)
0049 /*  Enable the transmitter.
0050  *  This option defaults to enabled (set) */
0051 #define XTE_OPTION_TXEN                         (1 << 11)
0052 /*  Enable the receiver
0053 *   This option defaults to enabled (set) */
0054 #define XTE_OPTION_RXEN                         (1 << 12)
0055
0056 /*  Default options set when device is initialized or reset */
0057 #define XTE_OPTION_DEFAULTS                     \
0058     (XTE_OPTION_TXEN |                          \
0059      XTE_OPTION_FLOW_CONTROL |                  \
0060      XTE_OPTION_RXEN)
0061
0062 /* XPS_LL_TEMAC SDMA registers definition */
0063
0064 #define TX_NXTDESC_PTR      0x00            /* r */
0065 #define TX_CURBUF_ADDR      0x01            /* r */
0066 #define TX_CURBUF_LENGTH    0x02            /* r */
0067 #define TX_CURDESC_PTR      0x03            /* rw */
0068 #define TX_TAILDESC_PTR     0x04            /* rw */
0069 #define TX_CHNL_CTRL        0x05            /* rw */
0070 /*
0071  0:7      24:31       IRQTimeout
0072  8:15     16:23       IRQCount
0073  16:20    11:15       Reserved
0074  21       10          0
0075  22       9           UseIntOnEnd
0076  23       8           LdIRQCnt
0077  24       7           IRQEn
0078  25:28    3:6         Reserved
0079  29       2           IrqErrEn
0080  30       1           IrqDlyEn
0081  31       0           IrqCoalEn
0082 */
0083 #define CHNL_CTRL_IRQ_IOE       (1 << 9)
0084 #define CHNL_CTRL_IRQ_EN        (1 << 7)
0085 #define CHNL_CTRL_IRQ_ERR_EN    (1 << 2)
0086 #define CHNL_CTRL_IRQ_DLY_EN    (1 << 1)
0087 #define CHNL_CTRL_IRQ_COAL_EN   (1 << 0)
0088 #define TX_IRQ_REG          0x06            /* rw */
0089 /*
0090   0:7      24:31       DltTmrValue
0091  8:15     16:23       ClscCntrValue
0092  16:17    14:15       Reserved
0093  18:21    10:13       ClscCnt
0094  22:23    8:9         DlyCnt
0095  24:28    3::7        Reserved
0096  29       2           ErrIrq
0097  30       1           DlyIrq
0098  31       0           CoalIrq
0099  */
0100 #define TX_CHNL_STS         0x07            /* r */
0101 /*
0102    0:9      22:31   Reserved
0103  10       21      TailPErr
0104  11       20      CmpErr
0105  12       19      AddrErr
0106  13       18      NxtPErr
0107  14       17      CurPErr
0108  15       16      BsyWr
0109  16:23    8:15    Reserved
0110  24       7       Error
0111  25       6       IOE
0112  26       5       SOE
0113  27       4       Cmplt
0114  28       3       SOP
0115  29       2       EOP
0116  30       1       EngBusy
0117  31       0       Reserved
0118 */
0119
0120 #define RX_NXTDESC_PTR      0x08            /* r */
0121 #define RX_CURBUF_ADDR      0x09            /* r */
0122 #define RX_CURBUF_LENGTH    0x0a            /* r */
0123 #define RX_CURDESC_PTR      0x0b            /* rw */
0124 #define RX_TAILDESC_PTR     0x0c            /* rw */
0125 #define RX_CHNL_CTRL        0x0d            /* rw */
0126 /*
0127  0:7      24:31       IRQTimeout
0128  8:15     16:23       IRQCount
0129  16:20    11:15       Reserved
0130  21       10          0
0131  22       9           UseIntOnEnd
0132  23       8           LdIRQCnt
0133  24       7           IRQEn
0134  25:28    3:6         Reserved
0135  29       2           IrqErrEn
0136  30       1           IrqDlyEn
0137  31       0           IrqCoalEn
0138  */
0139 #define RX_IRQ_REG          0x0e            /* rw */
0140 #define IRQ_COAL        (1 << 0)
0141 #define IRQ_DLY         (1 << 1)
0142 #define IRQ_ERR         (1 << 2)
0143 #define IRQ_DMAERR      (1 << 7)            /* this is not documented ??? */
0144 /*
0145  0:7      24:31       DltTmrValue
0146  8:15     16:23       ClscCntrValue
0147  16:17    14:15       Reserved
0148  18:21    10:13       ClscCnt
0149  22:23    8:9         DlyCnt
0150  24:28    3::7        Reserved
0151 */
0152 #define RX_CHNL_STS         0x0f        /* r */
0153 #define CHNL_STS_ENGBUSY    (1 << 1)
0154 #define CHNL_STS_EOP        (1 << 2)
0155 #define CHNL_STS_SOP        (1 << 3)
0156 #define CHNL_STS_CMPLT      (1 << 4)
0157 #define CHNL_STS_SOE        (1 << 5)
0158 #define CHNL_STS_IOE        (1 << 6)
0159 #define CHNL_STS_ERR        (1 << 7)
0160
0161 #define CHNL_STS_BSYWR      (1 << 16)
0162 #define CHNL_STS_CURPERR    (1 << 17)
0163 #define CHNL_STS_NXTPERR    (1 << 18)
0164 #define CHNL_STS_ADDRERR    (1 << 19)
0165 #define CHNL_STS_CMPERR     (1 << 20)
0166 #define CHNL_STS_TAILERR    (1 << 21)
0167 /*
0168  0:9      22:31   Reserved
0169  10       21      TailPErr
0170  11       20      CmpErr
0171  12       19      AddrErr
0172  13       18      NxtPErr
0173  14       17      CurPErr
0174  15       16      BsyWr
0175  16:23    8:15    Reserved
0176  24       7       Error
0177  25       6       IOE
0178  26       5       SOE
0179  27       4       Cmplt
0180  28       3       SOP
0181  29       2       EOP
0182  30       1       EngBusy
0183  31       0       Reserved
0184 */
0185
0186 #define DMA_CONTROL_REG             0x10            /* rw */
0187 #define DMA_CONTROL_RST                 (1 << 0)
0188 #define DMA_TAIL_ENABLE                 (1 << 2)
0189
0190 /* XPS_LL_TEMAC direct registers definition */
0191
0192 #define XTE_RAF0_OFFSET              0x00
0193 #define RAF0_RST                        (1 << 0)
0194 #define RAF0_MCSTREJ                    (1 << 1)
0195 #define RAF0_BCSTREJ                    (1 << 2)
0196 #define XTE_TPF0_OFFSET              0x04
0197 #define XTE_IFGP0_OFFSET             0x08
0198 #define XTE_ISR0_OFFSET              0x0c
0199 #define ISR0_HARDACSCMPLT               (1 << 0)
0200 #define ISR0_AUTONEG                    (1 << 1)
0201 #define ISR0_RXCMPLT                    (1 << 2)
0202 #define ISR0_RXREJ                      (1 << 3)
0203 #define ISR0_RXFIFOOVR                  (1 << 4)
0204 #define ISR0_TXCMPLT                    (1 << 5)
0205 #define ISR0_RXDCMLCK                   (1 << 6)
0206
0207 #define XTE_IPR0_OFFSET              0x10
0208 #define XTE_IER0_OFFSET              0x14
0209
0210 #define XTE_MSW0_OFFSET              0x20
0211 #define XTE_LSW0_OFFSET              0x24
0212 #define XTE_CTL0_OFFSET              0x28
0213 #define XTE_RDY0_OFFSET              0x2c
0214
0215 #define XTE_RSE_MIIM_RR_MASK      0x0002
0216 #define XTE_RSE_MIIM_WR_MASK      0x0004
0217 #define XTE_RSE_CFG_RR_MASK       0x0020
0218 #define XTE_RSE_CFG_WR_MASK       0x0040
0219 #define XTE_RDY0_HARD_ACS_RDY_MASK  (0x10000)
0220
0221 /* XPS_LL_TEMAC indirect registers offset definition */
0222
0223 #define XTE_RXC0_OFFSET         0x00000200 /* Rx configuration word 0 */
0224 #define XTE_RXC1_OFFSET         0x00000240 /* Rx configuration word 1 */
0225 #define XTE_RXC1_RXRST_MASK     (1 << 31)  /* Receiver reset */
0226 #define XTE_RXC1_RXJMBO_MASK        (1 << 30)  /* Jumbo frame enable */
0227 #define XTE_RXC1_RXFCS_MASK     (1 << 29)  /* FCS not stripped */
0228 #define XTE_RXC1_RXEN_MASK      (1 << 28)  /* Receiver enable */
0229 #define XTE_RXC1_RXVLAN_MASK        (1 << 27)  /* VLAN enable */
0230 #define XTE_RXC1_RXHD_MASK      (1 << 26)  /* Half duplex */
0231 #define XTE_RXC1_RXLT_MASK      (1 << 25)  /* Length/type check disable */
0232
0233 #define XTE_TXC_OFFSET          0x00000280 /*  Tx configuration */
0234 #define XTE_TXC_TXRST_MASK      (1 << 31)  /* Transmitter reset */
0235 #define XTE_TXC_TXJMBO_MASK     (1 << 30)  /* Jumbo frame enable */
0236 #define XTE_TXC_TXFCS_MASK      (1 << 29)  /* Generate FCS */
0237 #define XTE_TXC_TXEN_MASK       (1 << 28)  /* Transmitter enable */
0238 #define XTE_TXC_TXVLAN_MASK     (1 << 27)  /* VLAN enable */
0239 #define XTE_TXC_TXHD_MASK       (1 << 26)  /* Half duplex */
0240
0241 #define XTE_FCC_OFFSET          0x000002C0 /* Flow control config */
0242 #define XTE_FCC_RXFLO_MASK      (1 << 29)  /* Rx flow control enable */
0243 #define XTE_FCC_TXFLO_MASK      (1 << 30)  /* Tx flow control enable */
0244
0245 #define XTE_EMCFG_OFFSET        0x00000300 /* EMAC configuration */
0246 #define XTE_EMCFG_LINKSPD_MASK      0xC0000000 /* Link speed */
0247 #define XTE_EMCFG_HOSTEN_MASK       (1 << 26)  /* Host interface enable */
0248 #define XTE_EMCFG_LINKSPD_10        0x00000000 /* 10 Mbit LINKSPD_MASK */
0249 #define XTE_EMCFG_LINKSPD_100       (1 << 30)  /* 100 Mbit LINKSPD_MASK */
0250 #define XTE_EMCFG_LINKSPD_1000      (1 << 31)  /* 1000 Mbit LINKSPD_MASK */
0251
0252 #define XTE_GMIC_OFFSET         0x00000320 /* RGMII/SGMII config */
0253 #define XTE_MC_OFFSET           0x00000340 /* MDIO configuration */
0254 #define XTE_UAW0_OFFSET         0x00000380 /* Unicast address word 0 */
0255 #define XTE_UAW1_OFFSET         0x00000384 /* Unicast address word 1 */
0256
0257 #define XTE_MAW0_OFFSET         0x00000388 /* Multicast addr word 0 */
0258 #define XTE_MAW1_OFFSET         0x0000038C /* Multicast addr word 1 */
0259 #define XTE_AFM_OFFSET          0x00000390 /* Promiscuous mode */
0260 #define XTE_AFM_EPPRM_MASK      (1 << 31)  /* Promiscuous mode enable */
0261
0262 /* Interrupt Request status */
0263 #define XTE_TIS_OFFSET          0x000003A0
0264 #define TIS_FRIS            (1 << 0)
0265 #define TIS_MRIS            (1 << 1)
0266 #define TIS_MWIS            (1 << 2)
0267 #define TIS_ARIS            (1 << 3)
0268 #define TIS_AWIS            (1 << 4)
0269 #define TIS_CRIS            (1 << 5)
0270 #define TIS_CWIS            (1 << 6)
0271
0272 #define XTE_TIE_OFFSET          0x000003A4 /* Interrupt enable */
0273
0274 /* MII Management Control register (MGTCR) */
0275 #define XTE_MGTDR_OFFSET        0x000003B0 /* MII data */
0276 #define XTE_MIIMAI_OFFSET       0x000003B4 /* MII control */
0277
0278 #define CNTLREG_WRITE_ENABLE_MASK   0x8000
0279 #define CNTLREG_EMAC1SEL_MASK       0x0400
0280 #define CNTLREG_ADDRESSCODE_MASK    0x03ff
0281
0282 /* CDMAC descriptor status bit definitions */
0283
0284 #define STS_CTRL_APP0_ERR         (1 << 31)
0285 #define STS_CTRL_APP0_IRQONEND    (1 << 30)
0286 /* undocumented */
0287 #define STS_CTRL_APP0_STOPONEND   (1 << 29)
0288 #define STS_CTRL_APP0_CMPLT       (1 << 28)
0289 #define STS_CTRL_APP0_SOP         (1 << 27)
0290 #define STS_CTRL_APP0_EOP         (1 << 26)
0291 #define STS_CTRL_APP0_ENGBUSY     (1 << 25)
0292 /* undocumented */
0293 #define STS_CTRL_APP0_ENGRST      (1 << 24)
0294
0295 #define TX_CONTROL_CALC_CSUM_MASK   1
0296
0297 #define MULTICAST_CAM_TABLE_NUM 4
0298
0299 /* TEMAC Synthesis features */
0300 #define TEMAC_FEATURE_RX_CSUM  (1 << 0)
0301 #define TEMAC_FEATURE_TX_CSUM  (1 << 1)
0302
0303 /* TX/RX CURDESC_PTR points to first descriptor */
0304 /* TX/RX TAILDESC_PTR points to last descriptor in linked list */
0305
0306 /**
0307  * struct cdmac_bd - LocalLink buffer descriptor format
0308  *
0309  * app0 bits:
0310  *  0    Error
0311  *  1    IrqOnEnd    generate an interrupt at completion of DMA  op
0312  *  2    reserved
0313  *  3    completed   Current descriptor completed
0314  *  4    SOP         TX - marks first desc/ RX marks first desct
0315  *  5    EOP         TX marks last desc/RX marks last desc
0316  *  6    EngBusy     DMA is processing
0317  *  7    reserved
0318  *  8:31 application specific
0319  */
0320 struct cdmac_bd {
0321     u32 next;   /* Physical address of next buffer descriptor */
0322     u32 phys;
0323     u32 len;
0324     u32 app0;
0325     u32 app1;   /* TX start << 16 | insert */
0326     u32 app2;   /* TX csum */
0327     u32 app3;
0328     u32 app4;   /* skb for TX length for RX */
0329 };
0330
0331 struct temac_local {
0332     struct net_device *ndev;
0333     struct device *dev;
0334
0335     /* Connection to PHY device */
0336     struct device_node *phy_node;
0337     /* For non-device-tree devices */
0338     char phy_name[MII_BUS_ID_SIZE + 3];
0339     phy_interface_t phy_interface;
0340
0341     /* MDIO bus data */
0342     struct mii_bus *mii_bus;    /* MII bus reference */
0343
0344     /* IO registers, dma functions and IRQs */
0345     void __iomem *regs;
0346     void __iomem *sdma_regs;
0347 #ifdef CONFIG_PPC_DCR
0348     dcr_host_t sdma_dcrs;
0349 #endif
0350     u32 (*temac_ior)(struct temac_local *lp, int offset);
0351     void (*temac_iow)(struct temac_local *lp, int offset, u32 value);
0352     u32 (*dma_in)(struct temac_local *lp, int reg);
0353     void (*dma_out)(struct temac_local *lp, int reg, u32 value);
0354
0355     int tx_irq;
0356     int rx_irq;
0357     int emac_num;
0358
0359     struct sk_buff **rx_skb;
0360     spinlock_t rx_lock;
0361     /* For synchronization of indirect register access.  Must be
0362      * shared mutex between interfaces in same TEMAC block.
0363      */
0364     spinlock_t *indirect_lock;
0365     u32 options;            /* Current options word */
0366     int last_link;
0367     unsigned int temac_features;
0368
0369     /* Buffer descriptors */
0370     struct cdmac_bd *tx_bd_v;
0371     dma_addr_t tx_bd_p;
0372     u32 tx_bd_num;
0373     struct cdmac_bd *rx_bd_v;
0374     dma_addr_t rx_bd_p;
0375     u32 rx_bd_num;
0376     int tx_bd_ci;
0377     int tx_bd_tail;
0378     int rx_bd_ci;
0379     int rx_bd_tail;
0380
0381     /* DMA channel control setup */
0382     u8 coalesce_count_tx;
0383     u8 coalesce_delay_tx;
0384     u8 coalesce_count_rx;
0385     u8 coalesce_delay_rx;
0386
0387     struct delayed_work restart_work;
0388 };
0389
0390 /* Wrappers for temac_ior()/temac_iow() function pointers above */
0391 #define temac_ior(lp, o) ((lp)->temac_ior(lp, o))
0392 #define temac_iow(lp, o, v) ((lp)->temac_iow(lp, o, v))
0393
0394 /* xilinx_temac.c */
0395 int temac_indirect_busywait(struct temac_local *lp);
0396 u32 temac_indirect_in32(struct temac_local *lp, int reg);
0397 u32 temac_indirect_in32_locked(struct temac_local *lp, int reg);
0398 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);
0399 void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value);
0400
0401 /* xilinx_temac_mdio.c */
0402 int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev);
0403 void temac_mdio_teardown(struct temac_local *lp);
0404
0405 #endif /* XILINX_LL_TEMAC_H */