ethernet/wiznet/w5100-spi.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Ethernet driver for the WIZnet W5100/W5200/W5500 chip.
0004  *
0005  * Copyright (C) 2016 Akinobu Mita <akinobu.mita@gmail.com>
0006  *
0007  * Datasheet:
0008  * http://www.wiznet.co.kr/wp-content/uploads/wiznethome/Chip/W5100/Document/W5100_Datasheet_v1.2.6.pdf
0009  * http://wiznethome.cafe24.com/wp-content/uploads/wiznethome/Chip/W5200/Documents/W5200_DS_V140E.pdf
0010  * http://wizwiki.net/wiki/lib/exe/fetch.php?media=products:w5500:w5500_ds_v106e_141230.pdf
0011  */
0012
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/delay.h>
0016 #include <linux/netdevice.h>
0017 #include <linux/of_net.h>
0018 #include <linux/of_device.h>
0019 #include <linux/spi/spi.h>
0020
0021 #include "w5100.h"
0022
0023 #define W5100_SPI_WRITE_OPCODE 0xf0
0024 #define W5100_SPI_READ_OPCODE 0x0f
0025
0026 static int w5100_spi_read(struct net_device *ndev, u32 addr)
0027 {
0028     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0029     u8 cmd[3] = { W5100_SPI_READ_OPCODE, addr >> 8, addr & 0xff };
0030     u8 data;
0031     int ret;
0032
0033     ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, 1);
0034
0035     return ret ? ret : data;
0036 }
0037
0038 static int w5100_spi_write(struct net_device *ndev, u32 addr, u8 data)
0039 {
0040     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0041     u8 cmd[4] = { W5100_SPI_WRITE_OPCODE, addr >> 8, addr & 0xff, data};
0042
0043     return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
0044 }
0045
0046 static int w5100_spi_read16(struct net_device *ndev, u32 addr)
0047 {
0048     u16 data;
0049     int ret;
0050
0051     ret = w5100_spi_read(ndev, addr);
0052     if (ret < 0)
0053         return ret;
0054     data = ret << 8;
0055     ret = w5100_spi_read(ndev, addr + 1);
0056
0057     return ret < 0 ? ret : data | ret;
0058 }
0059
0060 static int w5100_spi_write16(struct net_device *ndev, u32 addr, u16 data)
0061 {
0062     int ret;
0063
0064     ret = w5100_spi_write(ndev, addr, data >> 8);
0065     if (ret)
0066         return ret;
0067
0068     return w5100_spi_write(ndev, addr + 1, data & 0xff);
0069 }
0070
0071 static int w5100_spi_readbulk(struct net_device *ndev, u32 addr, u8 *buf,
0072                   int len)
0073 {
0074     int i;
0075
0076     for (i = 0; i < len; i++) {
0077         int ret = w5100_spi_read(ndev, addr + i);
0078
0079         if (ret < 0)
0080             return ret;
0081         buf[i] = ret;
0082     }
0083
0084     return 0;
0085 }
0086
0087 static int w5100_spi_writebulk(struct net_device *ndev, u32 addr, const u8 *buf,
0088                    int len)
0089 {
0090     int i;
0091
0092     for (i = 0; i < len; i++) {
0093         int ret = w5100_spi_write(ndev, addr + i, buf[i]);
0094
0095         if (ret)
0096             return ret;
0097     }
0098
0099     return 0;
0100 }
0101
0102 static const struct w5100_ops w5100_spi_ops = {
0103     .may_sleep = true,
0104     .chip_id = W5100,
0105     .read = w5100_spi_read,
0106     .write = w5100_spi_write,
0107     .read16 = w5100_spi_read16,
0108     .write16 = w5100_spi_write16,
0109     .readbulk = w5100_spi_readbulk,
0110     .writebulk = w5100_spi_writebulk,
0111 };
0112
0113 #define W5200_SPI_WRITE_OPCODE 0x80
0114
0115 struct w5200_spi_priv {
0116     /* Serialize access to cmd_buf */
0117     struct mutex cmd_lock;
0118
0119     /* DMA (thus cache coherency maintenance) requires the
0120      * transfer buffers to live in their own cache lines.
0121      */
0122     u8 cmd_buf[4] ____cacheline_aligned;
0123 };
0124
0125 static struct w5200_spi_priv *w5200_spi_priv(struct net_device *ndev)
0126 {
0127     return w5100_ops_priv(ndev);
0128 }
0129
0130 static int w5200_spi_init(struct net_device *ndev)
0131 {
0132     struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);
0133
0134     mutex_init(&spi_priv->cmd_lock);
0135
0136     return 0;
0137 }
0138
0139 static int w5200_spi_read(struct net_device *ndev, u32 addr)
0140 {
0141     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0142     u8 cmd[4] = { addr >> 8, addr & 0xff, 0, 1 };
0143     u8 data;
0144     int ret;
0145
0146     ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, 1);
0147
0148     return ret ? ret : data;
0149 }
0150
0151 static int w5200_spi_write(struct net_device *ndev, u32 addr, u8 data)
0152 {
0153     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0154     u8 cmd[5] = { addr >> 8, addr & 0xff, W5200_SPI_WRITE_OPCODE, 1, data };
0155
0156     return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
0157 }
0158
0159 static int w5200_spi_read16(struct net_device *ndev, u32 addr)
0160 {
0161     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0162     u8 cmd[4] = { addr >> 8, addr & 0xff, 0, 2 };
0163     __be16 data;
0164     int ret;
0165
0166     ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, sizeof(data));
0167
0168     return ret ? ret : be16_to_cpu(data);
0169 }
0170
0171 static int w5200_spi_write16(struct net_device *ndev, u32 addr, u16 data)
0172 {
0173     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0174     u8 cmd[6] = {
0175         addr >> 8, addr & 0xff,
0176         W5200_SPI_WRITE_OPCODE, 2,
0177         data >> 8, data & 0xff
0178     };
0179
0180     return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
0181 }
0182
0183 static int w5200_spi_readbulk(struct net_device *ndev, u32 addr, u8 *buf,
0184                   int len)
0185 {
0186     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0187     struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);
0188     struct spi_transfer xfer[] = {
0189         {
0190             .tx_buf = spi_priv->cmd_buf,
0191             .len = sizeof(spi_priv->cmd_buf),
0192         },
0193         {
0194             .rx_buf = buf,
0195             .len = len,
0196         },
0197     };
0198     int ret;
0199
0200     mutex_lock(&spi_priv->cmd_lock);
0201
0202     spi_priv->cmd_buf[0] = addr >> 8;
0203     spi_priv->cmd_buf[1] = addr;
0204     spi_priv->cmd_buf[2] = len >> 8;
0205     spi_priv->cmd_buf[3] = len;
0206     ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
0207
0208     mutex_unlock(&spi_priv->cmd_lock);
0209
0210     return ret;
0211 }
0212
0213 static int w5200_spi_writebulk(struct net_device *ndev, u32 addr, const u8 *buf,
0214                    int len)
0215 {
0216     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0217     struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);
0218     struct spi_transfer xfer[] = {
0219         {
0220             .tx_buf = spi_priv->cmd_buf,
0221             .len = sizeof(spi_priv->cmd_buf),
0222         },
0223         {
0224             .tx_buf = buf,
0225             .len = len,
0226         },
0227     };
0228     int ret;
0229
0230     mutex_lock(&spi_priv->cmd_lock);
0231
0232     spi_priv->cmd_buf[0] = addr >> 8;
0233     spi_priv->cmd_buf[1] = addr;
0234     spi_priv->cmd_buf[2] = W5200_SPI_WRITE_OPCODE | (len >> 8);
0235     spi_priv->cmd_buf[3] = len;
0236     ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
0237
0238     mutex_unlock(&spi_priv->cmd_lock);
0239
0240     return ret;
0241 }
0242
0243 static const struct w5100_ops w5200_ops = {
0244     .may_sleep = true,
0245     .chip_id = W5200,
0246     .read = w5200_spi_read,
0247     .write = w5200_spi_write,
0248     .read16 = w5200_spi_read16,
0249     .write16 = w5200_spi_write16,
0250     .readbulk = w5200_spi_readbulk,
0251     .writebulk = w5200_spi_writebulk,
0252     .init = w5200_spi_init,
0253 };
0254
0255 #define W5500_SPI_BLOCK_SELECT(addr) (((addr) >> 16) & 0x1f)
0256 #define W5500_SPI_READ_CONTROL(addr) (W5500_SPI_BLOCK_SELECT(addr) << 3)
0257 #define W5500_SPI_WRITE_CONTROL(addr)   \
0258     ((W5500_SPI_BLOCK_SELECT(addr) << 3) | BIT(2))
0259
0260 struct w5500_spi_priv {
0261     /* Serialize access to cmd_buf */
0262     struct mutex cmd_lock;
0263
0264     /* DMA (thus cache coherency maintenance) requires the
0265      * transfer buffers to live in their own cache lines.
0266      */
0267     u8 cmd_buf[3] ____cacheline_aligned;
0268 };
0269
0270 static struct w5500_spi_priv *w5500_spi_priv(struct net_device *ndev)
0271 {
0272     return w5100_ops_priv(ndev);
0273 }
0274
0275 static int w5500_spi_init(struct net_device *ndev)
0276 {
0277     struct w5500_spi_priv *spi_priv = w5500_spi_priv(ndev);
0278
0279     mutex_init(&spi_priv->cmd_lock);
0280
0281     return 0;
0282 }
0283
0284 static int w5500_spi_read(struct net_device *ndev, u32 addr)
0285 {
0286     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0287     u8 cmd[3] = {
0288         addr >> 8,
0289         addr,
0290         W5500_SPI_READ_CONTROL(addr)
0291     };
0292     u8 data;
0293     int ret;
0294
0295     ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, 1);
0296
0297     return ret ? ret : data;
0298 }
0299
0300 static int w5500_spi_write(struct net_device *ndev, u32 addr, u8 data)
0301 {
0302     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0303     u8 cmd[4] = {
0304         addr >> 8,
0305         addr,
0306         W5500_SPI_WRITE_CONTROL(addr),
0307         data
0308     };
0309
0310     return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
0311 }
0312
0313 static int w5500_spi_read16(struct net_device *ndev, u32 addr)
0314 {
0315     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0316     u8 cmd[3] = {
0317         addr >> 8,
0318         addr,
0319         W5500_SPI_READ_CONTROL(addr)
0320     };
0321     __be16 data;
0322     int ret;
0323
0324     ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, sizeof(data));
0325
0326     return ret ? ret : be16_to_cpu(data);
0327 }
0328
0329 static int w5500_spi_write16(struct net_device *ndev, u32 addr, u16 data)
0330 {
0331     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0332     u8 cmd[5] = {
0333         addr >> 8,
0334         addr,
0335         W5500_SPI_WRITE_CONTROL(addr),
0336         data >> 8,
0337         data
0338     };
0339
0340     return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);
0341 }
0342
0343 static int w5500_spi_readbulk(struct net_device *ndev, u32 addr, u8 *buf,
0344                   int len)
0345 {
0346     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0347     struct w5500_spi_priv *spi_priv = w5500_spi_priv(ndev);
0348     struct spi_transfer xfer[] = {
0349         {
0350             .tx_buf = spi_priv->cmd_buf,
0351             .len = sizeof(spi_priv->cmd_buf),
0352         },
0353         {
0354             .rx_buf = buf,
0355             .len = len,
0356         },
0357     };
0358     int ret;
0359
0360     mutex_lock(&spi_priv->cmd_lock);
0361
0362     spi_priv->cmd_buf[0] = addr >> 8;
0363     spi_priv->cmd_buf[1] = addr;
0364     spi_priv->cmd_buf[2] = W5500_SPI_READ_CONTROL(addr);
0365     ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
0366
0367     mutex_unlock(&spi_priv->cmd_lock);
0368
0369     return ret;
0370 }
0371
0372 static int w5500_spi_writebulk(struct net_device *ndev, u32 addr, const u8 *buf,
0373                    int len)
0374 {
0375     struct spi_device *spi = to_spi_device(ndev->dev.parent);
0376     struct w5500_spi_priv *spi_priv = w5500_spi_priv(ndev);
0377     struct spi_transfer xfer[] = {
0378         {
0379             .tx_buf = spi_priv->cmd_buf,
0380             .len = sizeof(spi_priv->cmd_buf),
0381         },
0382         {
0383             .tx_buf = buf,
0384             .len = len,
0385         },
0386     };
0387     int ret;
0388
0389     mutex_lock(&spi_priv->cmd_lock);
0390
0391     spi_priv->cmd_buf[0] = addr >> 8;
0392     spi_priv->cmd_buf[1] = addr;
0393     spi_priv->cmd_buf[2] = W5500_SPI_WRITE_CONTROL(addr);
0394     ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
0395
0396     mutex_unlock(&spi_priv->cmd_lock);
0397
0398     return ret;
0399 }
0400
0401 static const struct w5100_ops w5500_ops = {
0402     .may_sleep = true,
0403     .chip_id = W5500,
0404     .read = w5500_spi_read,
0405     .write = w5500_spi_write,
0406     .read16 = w5500_spi_read16,
0407     .write16 = w5500_spi_write16,
0408     .readbulk = w5500_spi_readbulk,
0409     .writebulk = w5500_spi_writebulk,
0410     .init = w5500_spi_init,
0411 };
0412
0413 static const struct of_device_id w5100_of_match[] = {
0414     { .compatible = "wiznet,w5100", .data = (const void*)W5100, },
0415     { .compatible = "wiznet,w5200", .data = (const void*)W5200, },
0416     { .compatible = "wiznet,w5500", .data = (const void*)W5500, },
0417     { },
0418 };
0419 MODULE_DEVICE_TABLE(of, w5100_of_match);
0420
0421 static int w5100_spi_probe(struct spi_device *spi)
0422 {
0423     const struct of_device_id *of_id;
0424     const struct w5100_ops *ops;
0425     kernel_ulong_t driver_data;
0426     const void *mac = NULL;
0427     u8 tmpmac[ETH_ALEN];
0428     int priv_size;
0429     int ret;
0430
0431     ret = of_get_mac_address(spi->dev.of_node, tmpmac);
0432     if (!ret)
0433         mac = tmpmac;
0434
0435     if (spi->dev.of_node) {
0436         of_id = of_match_device(w5100_of_match, &spi->dev);
0437         if (!of_id)
0438             return -ENODEV;
0439         driver_data = (kernel_ulong_t)of_id->data;
0440     } else {
0441         driver_data = spi_get_device_id(spi)->driver_data;
0442     }
0443
0444     switch (driver_data) {
0445     case W5100:
0446         ops = &w5100_spi_ops;
0447         priv_size = 0;
0448         break;
0449     case W5200:
0450         ops = &w5200_ops;
0451         priv_size = sizeof(struct w5200_spi_priv);
0452         break;
0453     case W5500:
0454         ops = &w5500_ops;
0455         priv_size = sizeof(struct w5500_spi_priv);
0456         break;
0457     default:
0458         return -EINVAL;
0459     }
0460
0461     return w5100_probe(&spi->dev, ops, priv_size, mac, spi->irq, -EINVAL);
0462 }
0463
0464 static void w5100_spi_remove(struct spi_device *spi)
0465 {
0466     w5100_remove(&spi->dev);
0467 }
0468
0469 static const struct spi_device_id w5100_spi_ids[] = {
0470     { "w5100", W5100 },
0471     { "w5200", W5200 },
0472     { "w5500", W5500 },
0473     {}
0474 };
0475 MODULE_DEVICE_TABLE(spi, w5100_spi_ids);
0476
0477 static struct spi_driver w5100_spi_driver = {
0478     .driver     = {
0479         .name   = "w5100",
0480         .pm = &w5100_pm_ops,
0481         .of_match_table = w5100_of_match,
0482     },
0483     .probe      = w5100_spi_probe,
0484     .remove     = w5100_spi_remove,
0485     .id_table   = w5100_spi_ids,
0486 };
0487 module_spi_driver(w5100_spi_driver);
0488
0489 MODULE_DESCRIPTION("WIZnet W5100/W5200/W5500 Ethernet driver for SPI mode");
0490 MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
0491 MODULE_LICENSE("GPL");