ethernet/toshiba/ps3_gelic_net.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  PS3 Platfom gelic network driver.
0004  *
0005  * Copyright (C) 2007 Sony Computer Entertainment Inc.
0006  * Copyright 2006, 2007 Sony Corporation.
0007  *
0008  * This file is based on: spider_net.h
0009  *
0010  * (C) Copyright IBM Corp. 2005
0011  *
0012  * Authors : Utz Bacher <utz.bacher@de.ibm.com>
0013  *           Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
0014  */
0015 #ifndef _GELIC_NET_H
0016 #define _GELIC_NET_H
0017
0018 /* descriptors */
0019 #define GELIC_NET_RX_DESCRIPTORS        128 /* num of descriptors */
0020 #define GELIC_NET_TX_DESCRIPTORS        128 /* num of descriptors */
0021
0022 #define GELIC_NET_MAX_MTU               VLAN_ETH_FRAME_LEN
0023 #define GELIC_NET_MIN_MTU               VLAN_ETH_ZLEN
0024 #define GELIC_NET_RXBUF_ALIGN           128
0025 #define GELIC_CARD_RX_CSUM_DEFAULT      1 /* hw chksum */
0026 #define GELIC_NET_WATCHDOG_TIMEOUT      5*HZ
0027 #define GELIC_NET_BROADCAST_ADDR        0xffffffffffffL
0028
0029 #define GELIC_NET_MC_COUNT_MAX          32 /* multicast address list */
0030
0031 /* virtual interrupt status register bits */
0032     /* INT1 */
0033 #define GELIC_CARD_TX_RAM_FULL_ERR           0x0000000000000001L
0034 #define GELIC_CARD_RX_RAM_FULL_ERR           0x0000000000000002L
0035 #define GELIC_CARD_TX_SHORT_FRAME_ERR        0x0000000000000004L
0036 #define GELIC_CARD_TX_INVALID_DESCR_ERR      0x0000000000000008L
0037 #define GELIC_CARD_RX_FIFO_FULL_ERR          0x0000000000002000L
0038 #define GELIC_CARD_RX_DESCR_CHAIN_END        0x0000000000004000L
0039 #define GELIC_CARD_RX_INVALID_DESCR_ERR      0x0000000000008000L
0040 #define GELIC_CARD_TX_RESPONCE_ERR           0x0000000000010000L
0041 #define GELIC_CARD_RX_RESPONCE_ERR           0x0000000000100000L
0042 #define GELIC_CARD_TX_PROTECTION_ERR         0x0000000000400000L
0043 #define GELIC_CARD_RX_PROTECTION_ERR         0x0000000004000000L
0044 #define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR   0x0000000008000000L
0045 #define GELIC_CARD_PORT_STATUS_CHANGED       0x0000000020000000L
0046 #define GELIC_CARD_WLAN_EVENT_RECEIVED       0x0000000040000000L
0047 #define GELIC_CARD_WLAN_COMMAND_COMPLETED    0x0000000080000000L
0048     /* INT 0 */
0049 #define GELIC_CARD_TX_FLAGGED_DESCR          0x0004000000000000L
0050 #define GELIC_CARD_RX_FLAGGED_DESCR          0x0040000000000000L
0051 #define GELIC_CARD_TX_TRANSFER_END           0x0080000000000000L
0052 #define GELIC_CARD_TX_DESCR_CHAIN_END        0x0100000000000000L
0053 #define GELIC_CARD_NUMBER_OF_RX_FRAME        0x1000000000000000L
0054 #define GELIC_CARD_ONE_TIME_COUNT_TIMER      0x4000000000000000L
0055 #define GELIC_CARD_FREE_RUN_COUNT_TIMER      0x8000000000000000L
0056
0057 /* initial interrupt mask */
0058 #define GELIC_CARD_TXINT    GELIC_CARD_TX_DESCR_CHAIN_END
0059
0060 #define GELIC_CARD_RXINT    (GELIC_CARD_RX_DESCR_CHAIN_END | \
0061                  GELIC_CARD_NUMBER_OF_RX_FRAME)
0062
0063  /* RX descriptor data_status bits */
0064 enum gelic_descr_rx_status {
0065     GELIC_DESCR_RXDMADU = 0x80000000, /* destination MAC addr unknown */
0066     GELIC_DESCR_RXLSTFBF    = 0x40000000, /* last frame buffer            */
0067     GELIC_DESCR_RXIPCHK = 0x20000000, /* IP checksum performed        */
0068     GELIC_DESCR_RXTCPCHK    = 0x10000000, /* TCP/UDP checksup performed   */
0069     GELIC_DESCR_RXWTPKT = 0x00C00000, /*
0070                            * wakeup trigger packet
0071                            * 01: Magic Packet (TM)
0072                            * 10: ARP packet
0073                            * 11: Multicast MAC addr
0074                            */
0075     GELIC_DESCR_RXVLNPKT    = 0x00200000, /* VLAN packet */
0076     /* bit 20..16 reserved */
0077     GELIC_DESCR_RXRRECNUM   = 0x0000ff00, /* reception receipt number */
0078     /* bit 7..0 reserved */
0079 };
0080
0081 #define GELIC_DESCR_DATA_STATUS_CHK_MASK    \
0082     (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
0083
0084  /* TX descriptor data_status bits */
0085 enum gelic_descr_tx_status {
0086     GELIC_DESCR_TX_TAIL = 0x00000001, /* gelic treated this
0087                            * descriptor was end of
0088                            * a tx frame
0089                            */
0090 };
0091
0092 /* RX descriptor data error bits */
0093 enum gelic_descr_rx_error {
0094     /* bit 31 reserved */
0095     GELIC_DESCR_RXALNERR    = 0x40000000, /* alignement error 10/100M */
0096     GELIC_DESCR_RXOVERERR   = 0x20000000, /* oversize error */
0097     GELIC_DESCR_RXRNTERR    = 0x10000000, /* Runt error */
0098     GELIC_DESCR_RXIPCHKERR  = 0x08000000, /* IP checksum  error */
0099     GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum  error */
0100     GELIC_DESCR_RXDRPPKT    = 0x00100000, /* drop packet */
0101     GELIC_DESCR_RXIPFMTERR  = 0x00080000, /* IP packet format error */
0102     /* bit 18 reserved */
0103     GELIC_DESCR_RXDATAERR   = 0x00020000, /* IP packet format error */
0104     GELIC_DESCR_RXCALERR    = 0x00010000, /* cariier extension length
0105                           * error */
0106     GELIC_DESCR_RXCREXERR   = 0x00008000, /* carrier extension error */
0107     GELIC_DESCR_RXMLTCST    = 0x00004000, /* multicast address frame */
0108     /* bit 13..0 reserved */
0109 };
0110 #define GELIC_DESCR_DATA_ERROR_CHK_MASK     \
0111     (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
0112
0113 /* DMA command and status (RX and TX)*/
0114 enum gelic_descr_dma_status {
0115     GELIC_DESCR_DMA_COMPLETE            = 0x00000000, /* used in tx */
0116     GELIC_DESCR_DMA_BUFFER_FULL         = 0x00000000, /* used in rx */
0117     GELIC_DESCR_DMA_RESPONSE_ERROR      = 0x10000000, /* used in rx, tx */
0118     GELIC_DESCR_DMA_PROTECTION_ERROR    = 0x20000000, /* used in rx, tx */
0119     GELIC_DESCR_DMA_FRAME_END           = 0x40000000, /* used in rx */
0120     GELIC_DESCR_DMA_FORCE_END           = 0x50000000, /* used in rx, tx */
0121     GELIC_DESCR_DMA_CARDOWNED           = 0xa0000000, /* used in rx, tx */
0122     GELIC_DESCR_DMA_NOT_IN_USE          = 0xb0000000, /* any other value */
0123 };
0124
0125 #define GELIC_DESCR_DMA_STAT_MASK   (0xf0000000)
0126
0127 /* tx descriptor command and status */
0128 enum gelic_descr_tx_dma_status {
0129     /* [19] */
0130     GELIC_DESCR_TX_DMA_IKE      = 0x00080000, /* IPSEC off */
0131     /* [18] */
0132     GELIC_DESCR_TX_DMA_FRAME_TAIL   = 0x00040000, /* last descriptor of
0133                                * the packet
0134                                */
0135     /* [17..16] */
0136     GELIC_DESCR_TX_DMA_TCP_CHKSUM   = 0x00020000, /* TCP packet */
0137     GELIC_DESCR_TX_DMA_UDP_CHKSUM   = 0x00030000, /* UDP packet */
0138     GELIC_DESCR_TX_DMA_NO_CHKSUM    = 0x00000000, /* no checksum */
0139
0140     /* [1] */
0141     GELIC_DESCR_TX_DMA_CHAIN_END    = 0x00000002, /* DMA terminated
0142                                * due to chain end
0143                                */
0144 };
0145
0146 #define GELIC_DESCR_DMA_CMD_NO_CHKSUM   \
0147     (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
0148     GELIC_DESCR_TX_DMA_NO_CHKSUM)
0149
0150 #define GELIC_DESCR_DMA_CMD_TCP_CHKSUM  \
0151     (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
0152     GELIC_DESCR_TX_DMA_TCP_CHKSUM)
0153
0154 #define GELIC_DESCR_DMA_CMD_UDP_CHKSUM  \
0155     (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
0156     GELIC_DESCR_TX_DMA_UDP_CHKSUM)
0157
0158 enum gelic_descr_rx_dma_status {
0159     /* [ 1 ] */
0160     GELIC_DESCR_RX_DMA_CHAIN_END    = 0x00000002, /* DMA terminated
0161                                * due to chain end
0162                                */
0163 };
0164
0165 /* for lv1_net_control */
0166 enum gelic_lv1_net_control_code {
0167     GELIC_LV1_GET_MAC_ADDRESS   = 1,
0168     GELIC_LV1_GET_ETH_PORT_STATUS   = 2,
0169     GELIC_LV1_SET_NEGOTIATION_MODE  = 3,
0170     GELIC_LV1_GET_VLAN_ID       = 4,
0171     GELIC_LV1_SET_WOL       = 5,
0172     GELIC_LV1_GET_CHANNEL           = 6,
0173     GELIC_LV1_POST_WLAN_CMD     = 9,
0174     GELIC_LV1_GET_WLAN_CMD_RESULT   = 10,
0175     GELIC_LV1_GET_WLAN_EVENT    = 11,
0176 };
0177
0178 /* for GELIC_LV1_SET_WOL */
0179 enum gelic_lv1_wol_command {
0180     GELIC_LV1_WOL_MAGIC_PACKET  = 1,
0181     GELIC_LV1_WOL_ADD_MATCH_ADDR    = 6,
0182     GELIC_LV1_WOL_DELETE_MATCH_ADDR = 7,
0183 };
0184
0185 /* for GELIC_LV1_WOL_MAGIC_PACKET */
0186 enum gelic_lv1_wol_mp_arg {
0187     GELIC_LV1_WOL_MP_DISABLE    = 0,
0188     GELIC_LV1_WOL_MP_ENABLE     = 1,
0189 };
0190
0191 /* for GELIC_LV1_WOL_{ADD,DELETE}_MATCH_ADDR */
0192 enum gelic_lv1_wol_match_arg {
0193     GELIC_LV1_WOL_MATCH_INDIVIDUAL  = 0,
0194     GELIC_LV1_WOL_MATCH_ALL     = 1,
0195 };
0196
0197 /* status returened from GET_ETH_PORT_STATUS */
0198 enum gelic_lv1_ether_port_status {
0199     GELIC_LV1_ETHER_LINK_UP     = 0x0000000000000001L,
0200     GELIC_LV1_ETHER_FULL_DUPLEX = 0x0000000000000002L,
0201     GELIC_LV1_ETHER_AUTO_NEG    = 0x0000000000000004L,
0202
0203     GELIC_LV1_ETHER_SPEED_10    = 0x0000000000000010L,
0204     GELIC_LV1_ETHER_SPEED_100   = 0x0000000000000020L,
0205     GELIC_LV1_ETHER_SPEED_1000  = 0x0000000000000040L,
0206     GELIC_LV1_ETHER_SPEED_MASK  = 0x0000000000000070L,
0207 };
0208
0209 enum gelic_lv1_vlan_index {
0210     /* for outgoing packets */
0211     GELIC_LV1_VLAN_TX_ETHERNET_0    = 0x0000000000000002L,
0212     GELIC_LV1_VLAN_TX_WIRELESS  = 0x0000000000000003L,
0213
0214     /* for incoming packets */
0215     GELIC_LV1_VLAN_RX_ETHERNET_0    = 0x0000000000000012L,
0216     GELIC_LV1_VLAN_RX_WIRELESS  = 0x0000000000000013L,
0217 };
0218
0219 enum gelic_lv1_phy {
0220     GELIC_LV1_PHY_ETHERNET_0    = 0x0000000000000002L,
0221 };
0222
0223 /* size of hardware part of gelic descriptor */
0224 #define GELIC_DESCR_SIZE    (32)
0225
0226 enum gelic_port_type {
0227     GELIC_PORT_ETHERNET_0   = 0,
0228     GELIC_PORT_WIRELESS = 1,
0229     GELIC_PORT_MAX
0230 };
0231
0232 struct gelic_descr {
0233     /* as defined by the hardware */
0234     __be32 buf_addr;
0235     __be32 buf_size;
0236     __be32 next_descr_addr;
0237     __be32 dmac_cmd_status;
0238     __be32 result_size;
0239     __be32 valid_size;  /* all zeroes for tx */
0240     __be32 data_status;
0241     __be32 data_error;  /* all zeroes for tx */
0242
0243     /* used in the driver */
0244     struct sk_buff *skb;
0245     dma_addr_t bus_addr;
0246     struct gelic_descr *next;
0247     struct gelic_descr *prev;
0248 } __attribute__((aligned(32)));
0249
0250 struct gelic_descr_chain {
0251     /* we walk from tail to head */
0252     struct gelic_descr *head;
0253     struct gelic_descr *tail;
0254 };
0255
0256 struct gelic_vlan_id {
0257     u16 tx;
0258     u16 rx;
0259 };
0260
0261 struct gelic_card {
0262     struct napi_struct napi;
0263     struct net_device *netdev[GELIC_PORT_MAX];
0264     /*
0265      * hypervisor requires irq_status should be
0266      * 8 bytes aligned, but u64 member is
0267      * always disposed in that manner
0268      */
0269     u64 irq_status;
0270     u64 irq_mask;
0271
0272     struct ps3_system_bus_device *dev;
0273     struct gelic_vlan_id vlan[GELIC_PORT_MAX];
0274     int vlan_required;
0275
0276     struct gelic_descr_chain tx_chain;
0277     struct gelic_descr_chain rx_chain;
0278     /*
0279      * tx_lock guards tx descriptor list and
0280      * tx_dma_progress.
0281      */
0282     spinlock_t tx_lock;
0283     int tx_dma_progress;
0284
0285     struct work_struct tx_timeout_task;
0286     atomic_t tx_timeout_task_counter;
0287     wait_queue_head_t waitq;
0288
0289     /* only first user should up the card */
0290     struct mutex updown_lock;
0291     atomic_t users;
0292
0293     u64 ether_port_status;
0294     int link_mode;
0295
0296     /* original address returned by kzalloc */
0297     void *unalign;
0298
0299     /*
0300      * each netdevice has copy of irq
0301      */
0302     unsigned int irq;
0303     struct gelic_descr *tx_top, *rx_top;
0304     struct gelic_descr descr[]; /* must be the last */
0305 };
0306
0307 struct gelic_port {
0308     struct gelic_card *card;
0309     struct net_device *netdev;
0310     enum gelic_port_type type;
0311     long priv[]; /* long for alignment */
0312 };
0313
0314 static inline struct gelic_card *port_to_card(struct gelic_port *p)
0315 {
0316     return p->card;
0317 }
0318 static inline struct net_device *port_to_netdev(struct gelic_port *p)
0319 {
0320     return p->netdev;
0321 }
0322 static inline struct gelic_card *netdev_card(struct net_device *d)
0323 {
0324     return ((struct gelic_port *)netdev_priv(d))->card;
0325 }
0326 static inline struct gelic_port *netdev_port(struct net_device *d)
0327 {
0328     return (struct gelic_port *)netdev_priv(d);
0329 }
0330 static inline struct device *ctodev(struct gelic_card *card)
0331 {
0332     return &card->dev->core;
0333 }
0334 static inline u64 bus_id(struct gelic_card *card)
0335 {
0336     return card->dev->bus_id;
0337 }
0338 static inline u64 dev_id(struct gelic_card *card)
0339 {
0340     return card->dev->dev_id;
0341 }
0342
0343 static inline void *port_priv(struct gelic_port *port)
0344 {
0345     return port->priv;
0346 }
0347
0348 #ifdef CONFIG_PPC_EARLY_DEBUG_PS3GELIC
0349 void udbg_shutdown_ps3gelic(void);
0350 #else
0351 static inline void udbg_shutdown_ps3gelic(void) {}
0352 #endif
0353
0354 int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);
0355 /* shared netdev ops */
0356 void gelic_card_up(struct gelic_card *card);
0357 void gelic_card_down(struct gelic_card *card);
0358 int gelic_net_open(struct net_device *netdev);
0359 int gelic_net_stop(struct net_device *netdev);
0360 netdev_tx_t gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
0361 void gelic_net_set_multi(struct net_device *netdev);
0362 void gelic_net_tx_timeout(struct net_device *netdev, unsigned int txqueue);
0363 int gelic_net_setup_netdev(struct net_device *netdev, struct gelic_card *card);
0364
0365 /* shared ethtool ops */
0366 void gelic_net_get_drvinfo(struct net_device *netdev,
0367                struct ethtool_drvinfo *info);
0368 void gelic_net_poll_controller(struct net_device *netdev);
0369
0370 #endif /* _GELIC_NET_H */