ethernet/ti/tlan.h

0001 #ifndef TLAN_H
0002 #define TLAN_H
0003 /********************************************************************
0004  *
0005  *  Linux ThunderLAN Driver
0006  *
0007  *  tlan.h
0008  *  by James Banks
0009  *
0010  *  (C) 1997-1998 Caldera, Inc.
0011  *  (C) 1999-2001 Torben Mathiasen
0012  *
0013  *  This software may be used and distributed according to the terms
0014  *  of the GNU General Public License, incorporated herein by reference.
0015  *
0016  *
0017  *  Dec 10, 1999    Torben Mathiasen <torben.mathiasen@compaq.com>
0018  *          New Maintainer
0019  *
0020  ********************************************************************/
0021
0022
0023 #include <linux/io.h>
0024 #include <linux/types.h>
0025 #include <linux/netdevice.h>
0026
0027
0028
0029     /*****************************************************************
0030      * TLan Definitions
0031      *
0032      ****************************************************************/
0033
0034 #define TLAN_MIN_FRAME_SIZE 64
0035 #define TLAN_MAX_FRAME_SIZE 1600
0036
0037 #define TLAN_NUM_RX_LISTS   32
0038 #define TLAN_NUM_TX_LISTS   64
0039
0040 #define TLAN_IGNORE     0
0041 #define TLAN_RECORD     1
0042
0043 #define TLAN_DBG(lvl, format, args...)                  \
0044     do {                                \
0045         if (debug&lvl)                      \
0046             printk(KERN_DEBUG "TLAN: " format, ##args); \
0047     } while (0)
0048
0049 #define TLAN_DEBUG_GNRL     0x0001
0050 #define TLAN_DEBUG_TX       0x0002
0051 #define TLAN_DEBUG_RX       0x0004
0052 #define TLAN_DEBUG_LIST     0x0008
0053 #define TLAN_DEBUG_PROBE    0x0010
0054
0055 #define TX_TIMEOUT      (10*HZ)  /* We need time for auto-neg */
0056 #define MAX_TLAN_BOARDS     8    /* Max number of boards installed
0057                         at a time */
0058
0059
0060     /*****************************************************************
0061      * Device Identification Definitions
0062      *
0063      ****************************************************************/
0064
0065 #define PCI_DEVICE_ID_NETELLIGENT_10_T2         0xB012
0066 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100    0xB030
0067 #ifndef PCI_DEVICE_ID_OLICOM_OC2183
0068 #define PCI_DEVICE_ID_OLICOM_OC2183         0x0013
0069 #endif
0070 #ifndef PCI_DEVICE_ID_OLICOM_OC2325
0071 #define PCI_DEVICE_ID_OLICOM_OC2325         0x0012
0072 #endif
0073 #ifndef PCI_DEVICE_ID_OLICOM_OC2326
0074 #define PCI_DEVICE_ID_OLICOM_OC2326         0x0014
0075 #endif
0076
0077 struct tlan_adapter_entry {
0078     u16 vendor_id;
0079     u16 device_id;
0080     char    *device_label;
0081     u32 flags;
0082     u16 addr_ofs;
0083 };
0084
0085 #define TLAN_ADAPTER_NONE       0x00000000
0086 #define TLAN_ADAPTER_UNMANAGED_PHY  0x00000001
0087 #define TLAN_ADAPTER_BIT_RATE_PHY   0x00000002
0088 #define TLAN_ADAPTER_USE_INTERN_10  0x00000004
0089 #define TLAN_ADAPTER_ACTIVITY_LED   0x00000008
0090
0091 #define TLAN_SPEED_DEFAULT  0
0092 #define TLAN_SPEED_10       10
0093 #define TLAN_SPEED_100      100
0094
0095 #define TLAN_DUPLEX_DEFAULT 0
0096 #define TLAN_DUPLEX_HALF    1
0097 #define TLAN_DUPLEX_FULL    2
0098
0099
0100
0101     /*****************************************************************
0102      * EISA Definitions
0103      *
0104      ****************************************************************/
0105
0106 #define EISA_ID      0xc80   /* EISA ID Registers */
0107 #define EISA_ID0     0xc80   /* EISA ID Register 0 */
0108 #define EISA_ID1     0xc81   /* EISA ID Register 1 */
0109 #define EISA_ID2     0xc82   /* EISA ID Register 2 */
0110 #define EISA_ID3     0xc83   /* EISA ID Register 3 */
0111 #define EISA_CR      0xc84   /* EISA Control Register */
0112 #define EISA_REG0    0xc88   /* EISA Configuration Register 0 */
0113 #define EISA_REG1    0xc89   /* EISA Configuration Register 1 */
0114 #define EISA_REG2    0xc8a   /* EISA Configuration Register 2 */
0115 #define EISA_REG3    0xc8f   /* EISA Configuration Register 3 */
0116 #define EISA_APROM   0xc90   /* Ethernet Address PROM */
0117
0118
0119
0120     /*****************************************************************
0121      * Rx/Tx List Definitions
0122      *
0123      ****************************************************************/
0124
0125 #define TLAN_BUFFERS_PER_LIST   10
0126 #define TLAN_LAST_BUFFER    0x80000000
0127 #define TLAN_CSTAT_UNUSED   0x8000
0128 #define TLAN_CSTAT_FRM_CMP  0x4000
0129 #define TLAN_CSTAT_READY    0x3000
0130 #define TLAN_CSTAT_EOC      0x0800
0131 #define TLAN_CSTAT_RX_ERROR 0x0400
0132 #define TLAN_CSTAT_PASS_CRC 0x0200
0133 #define TLAN_CSTAT_DP_PR    0x0100
0134
0135
0136 struct tlan_buffer {
0137     u32 count;
0138     u32 address;
0139 };
0140
0141
0142 struct tlan_list {
0143     u32     forward;
0144     u16     c_stat;
0145     u16     frame_size;
0146     struct tlan_buffer buffer[TLAN_BUFFERS_PER_LIST];
0147 };
0148
0149
0150 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
0151
0152
0153
0154
0155     /*****************************************************************
0156      * PHY definitions
0157      *
0158      ****************************************************************/
0159
0160 #define TLAN_PHY_MAX_ADDR   0x1F
0161 #define TLAN_PHY_NONE       0x20
0162
0163
0164
0165
0166     /*****************************************************************
0167      * TLAN Private Information Structure
0168      *
0169      ****************************************************************/
0170
0171 struct tlan_priv {
0172     struct net_device       *next_device;
0173     struct pci_dev      *pci_dev;
0174     struct net_device       *dev;
0175     void            *dma_storage;
0176     dma_addr_t      dma_storage_dma;
0177     unsigned int        dma_size;
0178     u8          *pad_buffer;
0179     struct tlan_list    *rx_list;
0180     dma_addr_t      rx_list_dma;
0181     u8          *rx_buffer;
0182     dma_addr_t      rx_buffer_dma;
0183     u32         rx_head;
0184     u32         rx_tail;
0185     u32         rx_eoc_count;
0186     struct tlan_list    *tx_list;
0187     dma_addr_t      tx_list_dma;
0188     u8          *tx_buffer;
0189     dma_addr_t      tx_buffer_dma;
0190     u32         tx_head;
0191     u32         tx_in_progress;
0192     u32         tx_tail;
0193     u32         tx_busy_count;
0194     u32         phy_online;
0195     u32         timer_set_at;
0196     u32         timer_type;
0197     struct timer_list   timer;
0198     struct timer_list   media_timer;
0199     struct board        *adapter;
0200     u32         adapter_rev;
0201     u32         aui;
0202     u32         debug;
0203     u32         duplex;
0204     u32         phy[2];
0205     u32         phy_num;
0206     u32         speed;
0207     u8          tlan_rev;
0208     u8          tlan_full_duplex;
0209     spinlock_t      lock;
0210     struct work_struct          tlan_tqueue;
0211 };
0212
0213
0214
0215
0216     /*****************************************************************
0217      * TLan Driver Timer Definitions
0218      *
0219      ****************************************************************/
0220
0221 #define TLAN_TIMER_ACTIVITY     2
0222 #define TLAN_TIMER_PHY_PDOWN        3
0223 #define TLAN_TIMER_PHY_PUP      4
0224 #define TLAN_TIMER_PHY_RESET        5
0225 #define TLAN_TIMER_PHY_START_LINK   6
0226 #define TLAN_TIMER_PHY_FINISH_AN    7
0227 #define TLAN_TIMER_FINISH_RESET     8
0228
0229 #define TLAN_TIMER_ACT_DELAY        (HZ/10)
0230
0231
0232
0233
0234     /*****************************************************************
0235      * TLan Driver Eeprom Definitions
0236      *
0237      ****************************************************************/
0238
0239 #define TLAN_EEPROM_ACK     0
0240 #define TLAN_EEPROM_STOP    1
0241
0242 #define TLAN_EEPROM_SIZE    256
0243
0244
0245
0246     /*****************************************************************
0247      * Host Register Offsets and Contents
0248      *
0249      ****************************************************************/
0250
0251 #define TLAN_HOST_CMD           0x00
0252 #define TLAN_HC_GO      0x80000000
0253 #define     TLAN_HC_STOP        0x40000000
0254 #define     TLAN_HC_ACK     0x20000000
0255 #define     TLAN_HC_CS_MASK     0x1FE00000
0256 #define     TLAN_HC_EOC     0x00100000
0257 #define     TLAN_HC_RT      0x00080000
0258 #define     TLAN_HC_NES     0x00040000
0259 #define     TLAN_HC_AD_RST      0x00008000
0260 #define     TLAN_HC_LD_TMR      0x00004000
0261 #define     TLAN_HC_LD_THR      0x00002000
0262 #define     TLAN_HC_REQ_INT     0x00001000
0263 #define     TLAN_HC_INT_OFF     0x00000800
0264 #define     TLAN_HC_INT_ON      0x00000400
0265 #define     TLAN_HC_AC_MASK     0x000000FF
0266 #define TLAN_CH_PARM            0x04
0267 #define TLAN_DIO_ADR            0x08
0268 #define     TLAN_DA_ADR_INC     0x8000
0269 #define     TLAN_DA_RAM_ADR     0x4000
0270 #define TLAN_HOST_INT           0x0A
0271 #define     TLAN_HI_IV_MASK     0x1FE0
0272 #define     TLAN_HI_IT_MASK     0x001C
0273 #define TLAN_DIO_DATA           0x0C
0274
0275
0276 /* ThunderLAN Internal Register DIO Offsets */
0277
0278 #define TLAN_NET_CMD            0x00
0279 #define     TLAN_NET_CMD_NRESET 0x80
0280 #define     TLAN_NET_CMD_NWRAP  0x40
0281 #define     TLAN_NET_CMD_CSF    0x20
0282 #define     TLAN_NET_CMD_CAF    0x10
0283 #define     TLAN_NET_CMD_NOBRX  0x08
0284 #define     TLAN_NET_CMD_DUPLEX 0x04
0285 #define     TLAN_NET_CMD_TRFRAM 0x02
0286 #define     TLAN_NET_CMD_TXPACE 0x01
0287 #define TLAN_NET_SIO            0x01
0288 #define TLAN_NET_SIO_MINTEN 0x80
0289 #define     TLAN_NET_SIO_ECLOK  0x40
0290 #define     TLAN_NET_SIO_ETXEN  0x20
0291 #define     TLAN_NET_SIO_EDATA  0x10
0292 #define     TLAN_NET_SIO_NMRST  0x08
0293 #define     TLAN_NET_SIO_MCLK   0x04
0294 #define     TLAN_NET_SIO_MTXEN  0x02
0295 #define     TLAN_NET_SIO_MDATA  0x01
0296 #define TLAN_NET_STS            0x02
0297 #define     TLAN_NET_STS_MIRQ   0x80
0298 #define     TLAN_NET_STS_HBEAT  0x40
0299 #define     TLAN_NET_STS_TXSTOP 0x20
0300 #define     TLAN_NET_STS_RXSTOP 0x10
0301 #define     TLAN_NET_STS_RSRVD  0x0F
0302 #define TLAN_NET_MASK           0x03
0303 #define     TLAN_NET_MASK_MASK7 0x80
0304 #define     TLAN_NET_MASK_MASK6 0x40
0305 #define     TLAN_NET_MASK_MASK5 0x20
0306 #define     TLAN_NET_MASK_MASK4 0x10
0307 #define     TLAN_NET_MASK_RSRVD 0x0F
0308 #define TLAN_NET_CONFIG         0x04
0309 #define TLAN_NET_CFG_RCLK   0x8000
0310 #define     TLAN_NET_CFG_TCLK   0x4000
0311 #define     TLAN_NET_CFG_BIT    0x2000
0312 #define     TLAN_NET_CFG_RXCRC  0x1000
0313 #define     TLAN_NET_CFG_PEF    0x0800
0314 #define     TLAN_NET_CFG_1FRAG  0x0400
0315 #define     TLAN_NET_CFG_1CHAN  0x0200
0316 #define     TLAN_NET_CFG_MTEST  0x0100
0317 #define     TLAN_NET_CFG_PHY_EN 0x0080
0318 #define     TLAN_NET_CFG_MSMASK 0x007F
0319 #define TLAN_MAN_TEST           0x06
0320 #define TLAN_DEF_VENDOR_ID      0x08
0321 #define TLAN_DEF_DEVICE_ID      0x0A
0322 #define TLAN_DEF_REVISION       0x0C
0323 #define TLAN_DEF_SUBCLASS       0x0D
0324 #define TLAN_DEF_MIN_LAT        0x0E
0325 #define TLAN_DEF_MAX_LAT        0x0F
0326 #define TLAN_AREG_0         0x10
0327 #define TLAN_AREG_1         0x16
0328 #define TLAN_AREG_2         0x1C
0329 #define TLAN_AREG_3         0x22
0330 #define TLAN_HASH_1         0x28
0331 #define TLAN_HASH_2         0x2C
0332 #define TLAN_GOOD_TX_FRMS       0x30
0333 #define TLAN_TX_UNDERUNS        0x33
0334 #define TLAN_GOOD_RX_FRMS       0x34
0335 #define TLAN_RX_OVERRUNS        0x37
0336 #define TLAN_DEFERRED_TX        0x38
0337 #define TLAN_CRC_ERRORS         0x3A
0338 #define TLAN_CODE_ERRORS        0x3B
0339 #define TLAN_MULTICOL_FRMS      0x3C
0340 #define TLAN_SINGLECOL_FRMS     0x3E
0341 #define TLAN_EXCESSCOL_FRMS     0x40
0342 #define TLAN_LATE_COLS          0x41
0343 #define TLAN_CARRIER_LOSS       0x42
0344 #define TLAN_ACOMMIT            0x43
0345 #define TLAN_LED_REG            0x44
0346 #define     TLAN_LED_ACT        0x10
0347 #define     TLAN_LED_LINK       0x01
0348 #define TLAN_BSIZE_REG          0x45
0349 #define TLAN_MAX_RX         0x46
0350 #define TLAN_INT_DIS            0x48
0351 #define     TLAN_ID_TX_EOC      0x04
0352 #define     TLAN_ID_RX_EOF      0x02
0353 #define     TLAN_ID_RX_EOC      0x01
0354
0355
0356
0357 /* ThunderLAN Interrupt Codes */
0358
0359 #define TLAN_INT_NUMBER_OF_INTS 8
0360
0361 #define TLAN_INT_NONE           0x0000
0362 #define TLAN_INT_TX_EOF         0x0001
0363 #define TLAN_INT_STAT_OVERFLOW      0x0002
0364 #define TLAN_INT_RX_EOF         0x0003
0365 #define TLAN_INT_DUMMY          0x0004
0366 #define TLAN_INT_TX_EOC         0x0005
0367 #define TLAN_INT_STATUS_CHECK       0x0006
0368 #define TLAN_INT_RX_EOC         0x0007
0369
0370
0371
0372 /* ThunderLAN MII Registers */
0373
0374 /* Generic MII/PHY Registers */
0375
0376 #define MII_GEN_CTL         0x00
0377 #define MII_GC_RESET        0x8000
0378 #define     MII_GC_LOOPBK       0x4000
0379 #define     MII_GC_SPEEDSEL     0x2000
0380 #define     MII_GC_AUTOENB      0x1000
0381 #define     MII_GC_PDOWN        0x0800
0382 #define     MII_GC_ISOLATE      0x0400
0383 #define     MII_GC_AUTORSRT     0x0200
0384 #define     MII_GC_DUPLEX       0x0100
0385 #define     MII_GC_COLTEST      0x0080
0386 #define     MII_GC_RESERVED     0x007F
0387 #define MII_GEN_STS         0x01
0388 #define     MII_GS_100BT4       0x8000
0389 #define     MII_GS_100BTXFD     0x4000
0390 #define     MII_GS_100BTXHD     0x2000
0391 #define     MII_GS_10BTFD       0x1000
0392 #define     MII_GS_10BTHD       0x0800
0393 #define     MII_GS_RESERVED     0x07C0
0394 #define     MII_GS_AUTOCMPLT    0x0020
0395 #define     MII_GS_RFLT     0x0010
0396 #define     MII_GS_AUTONEG      0x0008
0397 #define     MII_GS_LINK     0x0004
0398 #define     MII_GS_JABBER       0x0002
0399 #define     MII_GS_EXTCAP       0x0001
0400 #define MII_GEN_ID_HI           0x02
0401 #define MII_GEN_ID_LO           0x03
0402 #define MII_GIL_OUI     0xFC00
0403 #define MII_GIL_MODEL       0x03F0
0404 #define MII_GIL_REVISION    0x000F
0405 #define MII_AN_ADV          0x04
0406 #define MII_AN_LPA          0x05
0407 #define MII_AN_EXP          0x06
0408
0409 /* ThunderLAN Specific MII/PHY Registers */
0410
0411 #define TLAN_TLPHY_ID           0x10
0412 #define TLAN_TLPHY_CTL          0x11
0413 #define TLAN_TC_IGLINK      0x8000
0414 #define     TLAN_TC_SWAPOL      0x4000
0415 #define     TLAN_TC_AUISEL      0x2000
0416 #define     TLAN_TC_SQEEN       0x1000
0417 #define     TLAN_TC_MTEST       0x0800
0418 #define     TLAN_TC_RESERVED    0x07F8
0419 #define     TLAN_TC_NFEW        0x0004
0420 #define     TLAN_TC_INTEN       0x0002
0421 #define     TLAN_TC_TINT        0x0001
0422 #define TLAN_TLPHY_STS          0x12
0423 #define     TLAN_TS_MINT        0x8000
0424 #define     TLAN_TS_PHOK        0x4000
0425 #define     TLAN_TS_POLOK       0x2000
0426 #define     TLAN_TS_TPENERGY    0x1000
0427 #define     TLAN_TS_RESERVED    0x0FFF
0428 #define TLAN_TLPHY_PAR          0x19
0429 #define     TLAN_PHY_CIM_STAT   0x0020
0430 #define     TLAN_PHY_SPEED_100  0x0040
0431 #define     TLAN_PHY_DUPLEX_FULL    0x0080
0432 #define     TLAN_PHY_AN_EN_STAT     0x0400
0433
0434 /* National Sem. & Level1 PHY id's */
0435 #define NAT_SEM_ID1         0x2000
0436 #define NAT_SEM_ID2         0x5C01
0437 #define LEVEL1_ID1          0x7810
0438 #define LEVEL1_ID2          0x0000
0439
0440 #define CIRC_INC(a, b) if (++a >= b) a = 0
0441
0442 /* Routines to access internal registers. */
0443
0444 static inline u8 tlan_dio_read8(u16 base_addr, u16 internal_addr)
0445 {
0446     outw(internal_addr, base_addr + TLAN_DIO_ADR);
0447     return inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3));
0448
0449 }
0450
0451
0452
0453
0454 static inline u16 tlan_dio_read16(u16 base_addr, u16 internal_addr)
0455 {
0456     outw(internal_addr, base_addr + TLAN_DIO_ADR);
0457     return inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2));
0458
0459 }
0460
0461
0462
0463
0464 static inline u32 tlan_dio_read32(u16 base_addr, u16 internal_addr)
0465 {
0466     outw(internal_addr, base_addr + TLAN_DIO_ADR);
0467     return inl(base_addr + TLAN_DIO_DATA);
0468
0469 }
0470
0471
0472
0473
0474 static inline void tlan_dio_write8(u16 base_addr, u16 internal_addr, u8 data)
0475 {
0476     outw(internal_addr, base_addr + TLAN_DIO_ADR);
0477     outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
0478
0479 }
0480
0481
0482
0483
0484 static inline void tlan_dio_write16(u16 base_addr, u16 internal_addr, u16 data)
0485 {
0486     outw(internal_addr, base_addr + TLAN_DIO_ADR);
0487     outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
0488
0489 }
0490
0491
0492
0493
0494 static inline void tlan_dio_write32(u16 base_addr, u16 internal_addr, u32 data)
0495 {
0496     outw(internal_addr, base_addr + TLAN_DIO_ADR);
0497     outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
0498
0499 }
0500
0501 #define tlan_clear_bit(bit, port)   outb_p(inb_p(port) & ~bit, port)
0502 #define tlan_get_bit(bit, port) ((int) (inb_p(port) & bit))
0503 #define tlan_set_bit(bit, port) outb_p(inb_p(port) | bit, port)
0504
0505 /*
0506  * given 6 bytes, view them as 8 6-bit numbers and return the XOR of those
0507  * the code below is about seven times as fast as the original code
0508  *
0509  * The original code was:
0510  *
0511  * u32  xor(u32 a, u32 b) { return ((a && !b ) || (! a && b )); }
0512  *
0513  * #define XOR8(a, b, c, d, e, f, g, h) \
0514  *  xor(a, xor(b, xor(c, xor(d, xor(e, xor(f, xor(g, h)) ) ) ) ) )
0515  * #define DA(a, bit)       (( (u8) a[bit/8] ) & ( (u8) (1 << bit%8)) )
0516  *
0517  *  hash  = XOR8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24),
0518  *            DA(a,30), DA(a,36), DA(a,42));
0519  *  hash |= XOR8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25),
0520  *            DA(a,31), DA(a,37), DA(a,43)) << 1;
0521  *  hash |= XOR8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26),
0522  *            DA(a,32), DA(a,38), DA(a,44)) << 2;
0523  *  hash |= XOR8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27),
0524  *            DA(a,33), DA(a,39), DA(a,45)) << 3;
0525  *  hash |= XOR8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28),
0526  *            DA(a,34), DA(a,40), DA(a,46)) << 4;
0527  *  hash |= XOR8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29),
0528  *            DA(a,35), DA(a,41), DA(a,47)) << 5;
0529  *
0530  */
0531 static inline u32 tlan_hash_func(const u8 *a)
0532 {
0533     u8     hash;
0534
0535     hash = (a[0]^a[3]);     /* & 077 */
0536     hash ^= ((a[0]^a[3])>>6);   /* & 003 */
0537     hash ^= ((a[1]^a[4])<<2);   /* & 074 */
0538     hash ^= ((a[1]^a[4])>>4);   /* & 017 */
0539     hash ^= ((a[2]^a[5])<<4);   /* & 060 */
0540     hash ^= ((a[2]^a[5])>>2);   /* & 077 */
0541
0542     return hash & 077;
0543 }
0544 #endif