ethernet/ti/davinci_mdio.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * DaVinci MDIO Module driver
0004  *
0005  * Copyright (C) 2010 Texas Instruments.
0006  *
0007  * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
0008  *
0009  * Copyright (C) 2009 Texas Instruments.
0010  *
0011  */
0012 #include <linux/module.h>
0013 #include <linux/kernel.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/delay.h>
0016 #include <linux/sched.h>
0017 #include <linux/slab.h>
0018 #include <linux/phy.h>
0019 #include <linux/clk.h>
0020 #include <linux/err.h>
0021 #include <linux/io.h>
0022 #include <linux/iopoll.h>
0023 #include <linux/pm_runtime.h>
0024 #include <linux/davinci_emac.h>
0025 #include <linux/of.h>
0026 #include <linux/of_device.h>
0027 #include <linux/of_mdio.h>
0028 #include <linux/pinctrl/consumer.h>
0029
0030 /*
0031  * This timeout definition is a worst-case ultra defensive measure against
0032  * unexpected controller lock ups.  Ideally, we should never ever hit this
0033  * scenario in practice.
0034  */
0035 #define MDIO_TIMEOUT        100 /* msecs */
0036
0037 #define PHY_REG_MASK        0x1f
0038 #define PHY_ID_MASK     0x1f
0039
0040 #define DEF_OUT_FREQ        2200000     /* 2.2 MHz */
0041
0042 struct davinci_mdio_of_param {
0043     int autosuspend_delay_ms;
0044 };
0045
0046 struct davinci_mdio_regs {
0047     u32 version;
0048     u32 control;
0049 #define CONTROL_IDLE        BIT(31)
0050 #define CONTROL_ENABLE      BIT(30)
0051 #define CONTROL_MAX_DIV     (0xffff)
0052
0053     u32 alive;
0054     u32 link;
0055     u32 linkintraw;
0056     u32 linkintmasked;
0057     u32 __reserved_0[2];
0058     u32 userintraw;
0059     u32 userintmasked;
0060     u32 userintmaskset;
0061     u32 userintmaskclr;
0062     u32 __reserved_1[20];
0063
0064     struct {
0065         u32 access;
0066 #define USERACCESS_GO       BIT(31)
0067 #define USERACCESS_WRITE    BIT(30)
0068 #define USERACCESS_ACK      BIT(29)
0069 #define USERACCESS_READ     (0)
0070 #define USERACCESS_DATA     (0xffff)
0071
0072         u32 physel;
0073     }   user[];
0074 };
0075
0076 static const struct mdio_platform_data default_pdata = {
0077     .bus_freq = DEF_OUT_FREQ,
0078 };
0079
0080 struct davinci_mdio_data {
0081     struct mdio_platform_data pdata;
0082     struct davinci_mdio_regs __iomem *regs;
0083     struct clk  *clk;
0084     struct device   *dev;
0085     struct mii_bus  *bus;
0086     bool            active_in_suspend;
0087     unsigned long   access_time; /* jiffies */
0088     /* Indicates that driver shouldn't modify phy_mask in case
0089      * if MDIO bus is registered from DT.
0090      */
0091     bool        skip_scan;
0092     u32     clk_div;
0093 };
0094
0095 static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
0096 {
0097     u32 mdio_in, div, mdio_out_khz, access_time;
0098
0099     mdio_in = clk_get_rate(data->clk);
0100     div = (mdio_in / data->pdata.bus_freq) - 1;
0101     if (div > CONTROL_MAX_DIV)
0102         div = CONTROL_MAX_DIV;
0103
0104     data->clk_div = div;
0105     /*
0106      * One mdio transaction consists of:
0107      *  32 bits of preamble
0108      *  32 bits of transferred data
0109      *  24 bits of bus yield (not needed unless shared?)
0110      */
0111     mdio_out_khz = mdio_in / (1000 * (div + 1));
0112     access_time  = (88 * 1000) / mdio_out_khz;
0113
0114     /*
0115      * In the worst case, we could be kicking off a user-access immediately
0116      * after the mdio bus scan state-machine triggered its own read.  If
0117      * so, our request could get deferred by one access cycle.  We
0118      * defensively allow for 4 access cycles.
0119      */
0120     data->access_time = usecs_to_jiffies(access_time * 4);
0121     if (!data->access_time)
0122         data->access_time = 1;
0123 }
0124
0125 static void davinci_mdio_enable(struct davinci_mdio_data *data)
0126 {
0127     /* set enable and clock divider */
0128     writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
0129 }
0130
0131 static int davinci_mdio_reset(struct mii_bus *bus)
0132 {
0133     struct davinci_mdio_data *data = bus->priv;
0134     u32 phy_mask, ver;
0135     int ret;
0136
0137     ret = pm_runtime_resume_and_get(data->dev);
0138     if (ret < 0)
0139         return ret;
0140
0141     /* wait for scan logic to settle */
0142     msleep(PHY_MAX_ADDR * data->access_time);
0143
0144     /* dump hardware version info */
0145     ver = readl(&data->regs->version);
0146     dev_info(data->dev,
0147          "davinci mdio revision %d.%d, bus freq %ld\n",
0148          (ver >> 8) & 0xff, ver & 0xff,
0149          data->pdata.bus_freq);
0150
0151     if (data->skip_scan)
0152         goto done;
0153
0154     /* get phy mask from the alive register */
0155     phy_mask = readl(&data->regs->alive);
0156     if (phy_mask) {
0157         /* restrict mdio bus to live phys only */
0158         dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
0159         phy_mask = ~phy_mask;
0160     } else {
0161         /* desperately scan all phys */
0162         dev_warn(data->dev, "no live phy, scanning all\n");
0163         phy_mask = 0;
0164     }
0165     data->bus->phy_mask = phy_mask;
0166
0167 done:
0168     pm_runtime_mark_last_busy(data->dev);
0169     pm_runtime_put_autosuspend(data->dev);
0170
0171     return 0;
0172 }
0173
0174 /* wait until hardware is ready for another user access */
0175 static inline int wait_for_user_access(struct davinci_mdio_data *data)
0176 {
0177     struct davinci_mdio_regs __iomem *regs = data->regs;
0178     unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
0179     u32 reg;
0180
0181     while (time_after(timeout, jiffies)) {
0182         reg = readl(&regs->user[0].access);
0183         if ((reg & USERACCESS_GO) == 0)
0184             return 0;
0185
0186         reg = readl(&regs->control);
0187         if ((reg & CONTROL_IDLE) == 0) {
0188             usleep_range(100, 200);
0189             continue;
0190         }
0191
0192         /*
0193          * An emac soft_reset may have clobbered the mdio controller's
0194          * state machine.  We need to reset and retry the current
0195          * operation
0196          */
0197         dev_warn(data->dev, "resetting idled controller\n");
0198         davinci_mdio_enable(data);
0199         return -EAGAIN;
0200     }
0201
0202     reg = readl(&regs->user[0].access);
0203     if ((reg & USERACCESS_GO) == 0)
0204         return 0;
0205
0206     dev_err(data->dev, "timed out waiting for user access\n");
0207     return -ETIMEDOUT;
0208 }
0209
0210 /* wait until hardware state machine is idle */
0211 static inline int wait_for_idle(struct davinci_mdio_data *data)
0212 {
0213     struct davinci_mdio_regs __iomem *regs = data->regs;
0214     u32 val, ret;
0215
0216     ret = readl_poll_timeout(&regs->control, val, val & CONTROL_IDLE,
0217                  0, MDIO_TIMEOUT * 1000);
0218     if (ret)
0219         dev_err(data->dev, "timed out waiting for idle\n");
0220
0221     return ret;
0222 }
0223
0224 static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
0225 {
0226     struct davinci_mdio_data *data = bus->priv;
0227     u32 reg;
0228     int ret;
0229
0230     if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
0231         return -EINVAL;
0232
0233     ret = pm_runtime_resume_and_get(data->dev);
0234     if (ret < 0)
0235         return ret;
0236
0237     reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
0238            (phy_id << 16));
0239
0240     while (1) {
0241         ret = wait_for_user_access(data);
0242         if (ret == -EAGAIN)
0243             continue;
0244         if (ret < 0)
0245             break;
0246
0247         writel(reg, &data->regs->user[0].access);
0248
0249         ret = wait_for_user_access(data);
0250         if (ret == -EAGAIN)
0251             continue;
0252         if (ret < 0)
0253             break;
0254
0255         reg = readl(&data->regs->user[0].access);
0256         ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
0257         break;
0258     }
0259
0260     pm_runtime_mark_last_busy(data->dev);
0261     pm_runtime_put_autosuspend(data->dev);
0262     return ret;
0263 }
0264
0265 static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
0266                   int phy_reg, u16 phy_data)
0267 {
0268     struct davinci_mdio_data *data = bus->priv;
0269     u32 reg;
0270     int ret;
0271
0272     if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
0273         return -EINVAL;
0274
0275     ret = pm_runtime_resume_and_get(data->dev);
0276     if (ret < 0)
0277         return ret;
0278
0279     reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
0280            (phy_id << 16) | (phy_data & USERACCESS_DATA));
0281
0282     while (1) {
0283         ret = wait_for_user_access(data);
0284         if (ret == -EAGAIN)
0285             continue;
0286         if (ret < 0)
0287             break;
0288
0289         writel(reg, &data->regs->user[0].access);
0290
0291         ret = wait_for_user_access(data);
0292         if (ret == -EAGAIN)
0293             continue;
0294         break;
0295     }
0296
0297     pm_runtime_mark_last_busy(data->dev);
0298     pm_runtime_put_autosuspend(data->dev);
0299
0300     return ret;
0301 }
0302
0303 static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
0304              struct platform_device *pdev)
0305 {
0306     struct device_node *node = pdev->dev.of_node;
0307     u32 prop;
0308
0309     if (!node)
0310         return -EINVAL;
0311
0312     if (of_property_read_u32(node, "bus_freq", &prop)) {
0313         dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
0314         return -EINVAL;
0315     }
0316     data->bus_freq = prop;
0317
0318     return 0;
0319 }
0320
0321 #if IS_ENABLED(CONFIG_OF)
0322 static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
0323     .autosuspend_delay_ms = 100,
0324 };
0325
0326 static const struct of_device_id davinci_mdio_of_mtable[] = {
0327     { .compatible = "ti,davinci_mdio", },
0328     { .compatible = "ti,cpsw-mdio", .data = &of_cpsw_mdio_data},
0329     { /* sentinel */ },
0330 };
0331 MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
0332 #endif
0333
0334 static int davinci_mdio_probe(struct platform_device *pdev)
0335 {
0336     struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
0337     struct device *dev = &pdev->dev;
0338     struct davinci_mdio_data *data;
0339     struct resource *res;
0340     struct phy_device *phy;
0341     int ret, addr;
0342     int autosuspend_delay_ms = -1;
0343
0344     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0345     if (!data)
0346         return -ENOMEM;
0347
0348     data->bus = devm_mdiobus_alloc(dev);
0349     if (!data->bus) {
0350         dev_err(dev, "failed to alloc mii bus\n");
0351         return -ENOMEM;
0352     }
0353
0354     if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
0355         const struct davinci_mdio_of_param *of_mdio_data;
0356
0357         ret = davinci_mdio_probe_dt(&data->pdata, pdev);
0358         if (ret)
0359             return ret;
0360         snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
0361
0362         of_mdio_data = of_device_get_match_data(&pdev->dev);
0363         if (of_mdio_data) {
0364             autosuspend_delay_ms =
0365                     of_mdio_data->autosuspend_delay_ms;
0366         }
0367     } else {
0368         data->pdata = pdata ? (*pdata) : default_pdata;
0369         snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
0370              pdev->name, pdev->id);
0371     }
0372
0373     data->bus->name     = dev_name(dev);
0374     data->bus->read     = davinci_mdio_read;
0375     data->bus->write    = davinci_mdio_write;
0376     data->bus->reset    = davinci_mdio_reset;
0377     data->bus->parent   = dev;
0378     data->bus->priv     = data;
0379
0380     data->clk = devm_clk_get(dev, "fck");
0381     if (IS_ERR(data->clk)) {
0382         dev_err(dev, "failed to get device clock\n");
0383         return PTR_ERR(data->clk);
0384     }
0385
0386     dev_set_drvdata(dev, data);
0387     data->dev = dev;
0388
0389     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0390     if (!res)
0391         return -EINVAL;
0392     data->regs = devm_ioremap(dev, res->start, resource_size(res));
0393     if (!data->regs)
0394         return -ENOMEM;
0395
0396     davinci_mdio_init_clk(data);
0397
0398     pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay_ms);
0399     pm_runtime_use_autosuspend(&pdev->dev);
0400     pm_runtime_enable(&pdev->dev);
0401
0402     /* register the mii bus
0403      * Create PHYs from DT only in case if PHY child nodes are explicitly
0404      * defined to support backward compatibility with DTs which assume that
0405      * Davinci MDIO will always scan the bus for PHYs detection.
0406      */
0407     if (dev->of_node && of_get_child_count(dev->of_node))
0408         data->skip_scan = true;
0409
0410     ret = of_mdiobus_register(data->bus, dev->of_node);
0411     if (ret)
0412         goto bail_out;
0413
0414     /* scan and dump the bus */
0415     for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
0416         phy = mdiobus_get_phy(data->bus, addr);
0417         if (phy) {
0418             dev_info(dev, "phy[%d]: device %s, driver %s\n",
0419                  phy->mdio.addr, phydev_name(phy),
0420                  phy->drv ? phy->drv->name : "unknown");
0421         }
0422     }
0423
0424     return 0;
0425
0426 bail_out:
0427     pm_runtime_dont_use_autosuspend(&pdev->dev);
0428     pm_runtime_disable(&pdev->dev);
0429     return ret;
0430 }
0431
0432 static int davinci_mdio_remove(struct platform_device *pdev)
0433 {
0434     struct davinci_mdio_data *data = platform_get_drvdata(pdev);
0435
0436     if (data->bus)
0437         mdiobus_unregister(data->bus);
0438
0439     pm_runtime_dont_use_autosuspend(&pdev->dev);
0440     pm_runtime_disable(&pdev->dev);
0441
0442     return 0;
0443 }
0444
0445 #ifdef CONFIG_PM
0446 static int davinci_mdio_runtime_suspend(struct device *dev)
0447 {
0448     struct davinci_mdio_data *data = dev_get_drvdata(dev);
0449     u32 ctrl;
0450
0451     /* shutdown the scan state machine */
0452     ctrl = readl(&data->regs->control);
0453     ctrl &= ~CONTROL_ENABLE;
0454     writel(ctrl, &data->regs->control);
0455     wait_for_idle(data);
0456
0457     return 0;
0458 }
0459
0460 static int davinci_mdio_runtime_resume(struct device *dev)
0461 {
0462     struct davinci_mdio_data *data = dev_get_drvdata(dev);
0463
0464     davinci_mdio_enable(data);
0465     return 0;
0466 }
0467 #endif
0468
0469 #ifdef CONFIG_PM_SLEEP
0470 static int davinci_mdio_suspend(struct device *dev)
0471 {
0472     struct davinci_mdio_data *data = dev_get_drvdata(dev);
0473     int ret = 0;
0474
0475     data->active_in_suspend = !pm_runtime_status_suspended(dev);
0476     if (data->active_in_suspend)
0477         ret = pm_runtime_force_suspend(dev);
0478     if (ret < 0)
0479         return ret;
0480
0481     /* Select sleep pin state */
0482     pinctrl_pm_select_sleep_state(dev);
0483
0484     return 0;
0485 }
0486
0487 static int davinci_mdio_resume(struct device *dev)
0488 {
0489     struct davinci_mdio_data *data = dev_get_drvdata(dev);
0490
0491     /* Select default pin state */
0492     pinctrl_pm_select_default_state(dev);
0493
0494     if (data->active_in_suspend)
0495         pm_runtime_force_resume(dev);
0496
0497     return 0;
0498 }
0499 #endif
0500
0501 static const struct dev_pm_ops davinci_mdio_pm_ops = {
0502     SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend,
0503                davinci_mdio_runtime_resume, NULL)
0504     SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
0505 };
0506
0507 static struct platform_driver davinci_mdio_driver = {
0508     .driver = {
0509         .name    = "davinci_mdio",
0510         .pm  = &davinci_mdio_pm_ops,
0511         .of_match_table = of_match_ptr(davinci_mdio_of_mtable),
0512     },
0513     .probe = davinci_mdio_probe,
0514     .remove = davinci_mdio_remove,
0515 };
0516
0517 static int __init davinci_mdio_init(void)
0518 {
0519     return platform_driver_register(&davinci_mdio_driver);
0520 }
0521 device_initcall(davinci_mdio_init);
0522
0523 static void __exit davinci_mdio_exit(void)
0524 {
0525     platform_driver_unregister(&davinci_mdio_driver);
0526 }
0527 module_exit(davinci_mdio_exit);
0528
0529 MODULE_LICENSE("GPL");
0530 MODULE_DESCRIPTION("DaVinci MDIO driver");