ethernet/ti/cpts.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * TI Common Platform Time Sync
0004  *
0005  * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
0006  *
0007  */
0008 #ifndef _TI_CPTS_H_
0009 #define _TI_CPTS_H_
0010
0011 #if IS_ENABLED(CONFIG_TI_CPTS)
0012
0013 #include <linux/clk.h>
0014 #include <linux/clkdev.h>
0015 #include <linux/clocksource.h>
0016 #include <linux/device.h>
0017 #include <linux/list.h>
0018 #include <linux/of.h>
0019 #include <linux/ptp_clock_kernel.h>
0020 #include <linux/skbuff.h>
0021 #include <linux/ptp_classify.h>
0022 #include <linux/timecounter.h>
0023
0024 struct cpsw_cpts {
0025     u32 idver;                /* Identification and version */
0026     u32 control;              /* Time sync control */
0027     u32 rftclk_sel;       /* Reference Clock Select Register */
0028     u32 ts_push;              /* Time stamp event push */
0029     u32 ts_load_val;          /* Time stamp load value */
0030     u32 ts_load_en;           /* Time stamp load enable */
0031     u32 res2[2];
0032     u32 intstat_raw;          /* Time sync interrupt status raw */
0033     u32 intstat_masked;       /* Time sync interrupt status masked */
0034     u32 int_enable;           /* Time sync interrupt enable */
0035     u32 res3;
0036     u32 event_pop;            /* Event interrupt pop */
0037     u32 event_low;            /* 32 Bit Event Time Stamp */
0038     u32 event_high;           /* Event Type Fields */
0039 };
0040
0041 /* Bit definitions for the IDVER register */
0042 #define TX_IDENT_SHIFT       (16)    /* TX Identification Value */
0043 #define TX_IDENT_MASK        (0xffff)
0044 #define RTL_VER_SHIFT        (11)    /* RTL Version Value */
0045 #define RTL_VER_MASK         (0x1f)
0046 #define MAJOR_VER_SHIFT      (8)     /* Major Version Value */
0047 #define MAJOR_VER_MASK       (0x7)
0048 #define MINOR_VER_SHIFT      (0)     /* Minor Version Value */
0049 #define MINOR_VER_MASK       (0xff)
0050
0051 /* Bit definitions for the CONTROL register */
0052 #define HW4_TS_PUSH_EN       (1<<11) /* Hardware push 4 enable */
0053 #define HW3_TS_PUSH_EN       (1<<10) /* Hardware push 3 enable */
0054 #define HW2_TS_PUSH_EN       (1<<9)  /* Hardware push 2 enable */
0055 #define HW1_TS_PUSH_EN       (1<<8)  /* Hardware push 1 enable */
0056 #define INT_TEST             (1<<1)  /* Interrupt Test */
0057 #define CPTS_EN              (1<<0)  /* Time Sync Enable */
0058
0059 /*
0060  * Definitions for the single bit resisters:
0061  * TS_PUSH TS_LOAD_EN  INTSTAT_RAW INTSTAT_MASKED INT_ENABLE EVENT_POP
0062  */
0063 #define TS_PUSH             (1<<0)  /* Time stamp event push */
0064 #define TS_LOAD_EN          (1<<0)  /* Time Stamp Load */
0065 #define TS_PEND_RAW         (1<<0)  /* int read (before enable) */
0066 #define TS_PEND             (1<<0)  /* masked interrupt read (after enable) */
0067 #define TS_PEND_EN          (1<<0)  /* masked interrupt enable */
0068 #define EVENT_POP           (1<<0)  /* writing discards one event */
0069
0070 /* Bit definitions for the EVENT_HIGH register */
0071 #define PORT_NUMBER_SHIFT    (24)    /* Indicates Ethernet port or HW pin */
0072 #define PORT_NUMBER_MASK     (0x1f)
0073 #define EVENT_TYPE_SHIFT     (20)    /* Time sync event type */
0074 #define EVENT_TYPE_MASK      (0xf)
0075 #define MESSAGE_TYPE_SHIFT   (16)    /* PTP message type */
0076 #define MESSAGE_TYPE_MASK    (0xf)
0077 #define SEQUENCE_ID_SHIFT    (0)     /* PTP message sequence ID */
0078 #define SEQUENCE_ID_MASK     (0xffff)
0079
0080 enum {
0081     CPTS_EV_PUSH, /* Time Stamp Push Event */
0082     CPTS_EV_ROLL, /* Time Stamp Rollover Event */
0083     CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
0084     CPTS_EV_HW,   /* Hardware Time Stamp Push Event */
0085     CPTS_EV_RX,   /* Ethernet Receive Event */
0086     CPTS_EV_TX,   /* Ethernet Transmit Event */
0087 };
0088
0089 #define CPTS_FIFO_DEPTH 16
0090 #define CPTS_MAX_EVENTS 32
0091
0092 struct cpts_event {
0093     struct list_head list;
0094     unsigned long tmo;
0095     u32 high;
0096     u32 low;
0097     u64 timestamp;
0098 };
0099
0100 struct cpts {
0101     struct device *dev;
0102     struct cpsw_cpts __iomem *reg;
0103     int tx_enable;
0104     int rx_enable;
0105     struct ptp_clock_info info;
0106     struct ptp_clock *clock;
0107     spinlock_t lock; /* protects fifo/events */
0108     u32 cc_mult; /* for the nominal frequency */
0109     struct cyclecounter cc;
0110     struct timecounter tc;
0111     int phc_index;
0112     struct clk *refclk;
0113     struct list_head events;
0114     struct list_head pool;
0115     struct cpts_event pool_data[CPTS_MAX_EVENTS];
0116     unsigned long ov_check_period;
0117     struct sk_buff_head txq;
0118     u64 cur_timestamp;
0119     u32 mult_new;
0120     struct mutex ptp_clk_mutex; /* sync PTP interface and worker */
0121     bool irq_poll;
0122     struct completion   ts_push_complete;
0123     u32 hw_ts_enable;
0124 };
0125
0126 void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb);
0127 void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb);
0128 int cpts_register(struct cpts *cpts);
0129 void cpts_unregister(struct cpts *cpts);
0130 struct cpts *cpts_create(struct device *dev, void __iomem *regs,
0131              struct device_node *node, u32 n_ext_ts);
0132 void cpts_release(struct cpts *cpts);
0133 void cpts_misc_interrupt(struct cpts *cpts);
0134
0135 static inline bool cpts_can_timestamp(struct cpts *cpts, struct sk_buff *skb)
0136 {
0137     unsigned int class = ptp_classify_raw(skb);
0138
0139     if (class == PTP_CLASS_NONE)
0140         return false;
0141
0142     return true;
0143 }
0144
0145 static inline void cpts_set_irqpoll(struct cpts *cpts, bool en)
0146 {
0147     cpts->irq_poll = en;
0148 }
0149
0150 #else
0151 struct cpts;
0152
0153 static inline void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
0154 {
0155 }
0156 static inline void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
0157 {
0158 }
0159
0160 static inline
0161 struct cpts *cpts_create(struct device *dev, void __iomem *regs,
0162              struct device_node *node, u32 n_ext_ts)
0163 {
0164     return NULL;
0165 }
0166
0167 static inline void cpts_release(struct cpts *cpts)
0168 {
0169 }
0170
0171 static inline int
0172 cpts_register(struct cpts *cpts)
0173 {
0174     return 0;
0175 }
0176
0177 static inline void cpts_unregister(struct cpts *cpts)
0178 {
0179 }
0180
0181 static inline bool cpts_can_timestamp(struct cpts *cpts, struct sk_buff *skb)
0182 {
0183     return false;
0184 }
0185
0186 static inline void cpts_misc_interrupt(struct cpts *cpts)
0187 {
0188 }
0189
0190 static inline void cpts_set_irqpoll(struct cpts *cpts, bool en)
0191 {
0192 }
0193 #endif
0194
0195
0196 #endif