ethernet/ti/cpsw_sl.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/
0004  * Ethernet MAC Sliver (CPGMAC_SL) APIs
0005  *
0006  * Copyright (C) 2019 Texas Instruments
0007  *
0008  */
0009
0010 #ifndef __TI_CPSW_SL_H__
0011 #define __TI_CPSW_SL_H__
0012
0013 #include <linux/device.h>
0014
0015 enum cpsw_sl_regs {
0016     CPSW_SL_IDVER,
0017     CPSW_SL_MACCONTROL,
0018     CPSW_SL_MACSTATUS,
0019     CPSW_SL_SOFT_RESET,
0020     CPSW_SL_RX_MAXLEN,
0021     CPSW_SL_BOFFTEST,
0022     CPSW_SL_RX_PAUSE,
0023     CPSW_SL_TX_PAUSE,
0024     CPSW_SL_EMCONTROL,
0025     CPSW_SL_RX_PRI_MAP,
0026     CPSW_SL_TX_GAP,
0027 };
0028
0029 enum {
0030     CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */
0031     CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */
0032     CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */
0033     CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */
0034     CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */
0035     CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */
0036     CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */
0037     CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */
0038     CPSW_SL_CTL_XGIG = BIT(8), /* 10 Gigabit Mode */
0039     CPSW_SL_CTL_TX_SHORT_GAP_EN = BIT(10), /* Transmit Short Gap Enable */
0040     CPSW_SL_CTL_CMD_IDLE = BIT(11), /* Command Idle */
0041     CPSW_SL_CTL_CRC_TYPE = BIT(12), /* Port CRC Type */
0042     CPSW_SL_CTL_XGMII_EN = BIT(13), /* XGMII Enable */
0043     CPSW_SL_CTL_IFCTL_A = BIT(15), /* Interface Control A */
0044     CPSW_SL_CTL_IFCTL_B = BIT(16), /* Interface Control B */
0045     CPSW_SL_CTL_GIG_FORCE = BIT(17), /* Gigabit Mode Force */
0046     CPSW_SL_CTL_EXT_EN = BIT(18), /* External Control Enable */
0047     CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */
0048     CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */
0049     CPSW_SL_CTL_TX_SG_LIM_EN = BIT(21), /* TXt Short Gap Limit Enable */
0050     CPSW_SL_CTL_RX_CEF_EN = BIT(22), /* RX Copy Error Frames Enable */
0051     CPSW_SL_CTL_RX_CSF_EN = BIT(23), /* RX Copy Short Frames Enable */
0052     CPSW_SL_CTL_RX_CMF_EN = BIT(24), /* RX Copy MAC Control Frames Enable */
0053     CPSW_SL_CTL_EXT_EN_XGIG = BIT(25),  /* Ext XGIG Control En, k3 only */
0054
0055     CPSW_SL_CTL_FUNCS_COUNT
0056 };
0057
0058 struct cpsw_sl;
0059
0060 struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev,
0061                 void __iomem *sl_base);
0062
0063 void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo);
0064
0065 u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs);
0066 u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs);
0067 void cpsw_sl_ctl_reset(struct cpsw_sl *sl);
0068 int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo);
0069
0070 u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg);
0071 void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val);
0072
0073 #endif /* __TI_CPSW_SL_H__ */