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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Texas Instruments Ethernet Switch Driver
0004  */
0005 
0006 #ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
0007 #define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
0008 
0009 #include <uapi/linux/bpf.h>
0010 
0011 #include "davinci_cpdma.h"
0012 
0013 #define CPSW_DEBUG  (NETIF_MSG_HW       | NETIF_MSG_WOL     | \
0014              NETIF_MSG_DRV      | NETIF_MSG_LINK    | \
0015              NETIF_MSG_IFUP     | NETIF_MSG_INTR    | \
0016              NETIF_MSG_PROBE    | NETIF_MSG_TIMER   | \
0017              NETIF_MSG_IFDOWN   | NETIF_MSG_RX_ERR  | \
0018              NETIF_MSG_TX_ERR   | NETIF_MSG_TX_DONE | \
0019              NETIF_MSG_PKTDATA  | NETIF_MSG_TX_QUEUED   | \
0020              NETIF_MSG_RX_STATUS)
0021 
0022 #define cpsw_info(priv, type, format, ...)      \
0023 do {                                \
0024     if (netif_msg_##type(priv) && net_ratelimit())      \
0025         dev_info(priv->dev, format, ## __VA_ARGS__);    \
0026 } while (0)
0027 
0028 #define cpsw_err(priv, type, format, ...)       \
0029 do {                                \
0030     if (netif_msg_##type(priv) && net_ratelimit())      \
0031         dev_err(priv->dev, format, ## __VA_ARGS__); \
0032 } while (0)
0033 
0034 #define cpsw_dbg(priv, type, format, ...)       \
0035 do {                                \
0036     if (netif_msg_##type(priv) && net_ratelimit())      \
0037         dev_dbg(priv->dev, format, ## __VA_ARGS__); \
0038 } while (0)
0039 
0040 #define cpsw_notice(priv, type, format, ...)        \
0041 do {                                \
0042     if (netif_msg_##type(priv) && net_ratelimit())      \
0043         dev_notice(priv->dev, format, ## __VA_ARGS__);  \
0044 } while (0)
0045 
0046 #define ALE_ALL_PORTS       0x7
0047 
0048 #define CPSW_MAJOR_VERSION(reg)     (reg >> 8 & 0x7)
0049 #define CPSW_MINOR_VERSION(reg)     (reg & 0xff)
0050 #define CPSW_RTL_VERSION(reg)       ((reg >> 11) & 0x1f)
0051 
0052 #define CPSW_VERSION_1      0x19010a
0053 #define CPSW_VERSION_2      0x19010c
0054 #define CPSW_VERSION_3      0x19010f
0055 #define CPSW_VERSION_4      0x190112
0056 
0057 #define HOST_PORT_NUM       0
0058 #define CPSW_ALE_PORTS_NUM  3
0059 #define CPSW_SLAVE_PORTS_NUM    2
0060 #define SLIVER_SIZE     0x40
0061 
0062 #define CPSW1_HOST_PORT_OFFSET  0x028
0063 #define CPSW1_SLAVE_OFFSET  0x050
0064 #define CPSW1_SLAVE_SIZE    0x040
0065 #define CPSW1_CPDMA_OFFSET  0x100
0066 #define CPSW1_STATERAM_OFFSET   0x200
0067 #define CPSW1_HW_STATS      0x400
0068 #define CPSW1_CPTS_OFFSET   0x500
0069 #define CPSW1_ALE_OFFSET    0x600
0070 #define CPSW1_SLIVER_OFFSET 0x700
0071 #define CPSW1_WR_OFFSET     0x900
0072 
0073 #define CPSW2_HOST_PORT_OFFSET  0x108
0074 #define CPSW2_SLAVE_OFFSET  0x200
0075 #define CPSW2_SLAVE_SIZE    0x100
0076 #define CPSW2_CPDMA_OFFSET  0x800
0077 #define CPSW2_HW_STATS      0x900
0078 #define CPSW2_STATERAM_OFFSET   0xa00
0079 #define CPSW2_CPTS_OFFSET   0xc00
0080 #define CPSW2_ALE_OFFSET    0xd00
0081 #define CPSW2_SLIVER_OFFSET 0xd80
0082 #define CPSW2_BD_OFFSET     0x2000
0083 #define CPSW2_WR_OFFSET     0x1200
0084 
0085 #define CPDMA_RXTHRESH      0x0c0
0086 #define CPDMA_RXFREE        0x0e0
0087 #define CPDMA_TXHDP     0x00
0088 #define CPDMA_RXHDP     0x20
0089 #define CPDMA_TXCP      0x40
0090 #define CPDMA_RXCP      0x60
0091 
0092 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE     4
0093 #define CPSW_MIN_PACKET_SIZE_VLAN   (VLAN_ETH_ZLEN)
0094 #define CPSW_MIN_PACKET_SIZE    (ETH_ZLEN)
0095 #define CPSW_MAX_PACKET_SIZE    (VLAN_ETH_FRAME_LEN +\
0096                  ETH_FCS_LEN +\
0097                  CPSW_RX_VLAN_ENCAP_HDR_SIZE)
0098 
0099 #define RX_PRIORITY_MAPPING 0x76543210
0100 #define TX_PRIORITY_MAPPING 0x33221100
0101 #define CPDMA_TX_PRIORITY_MAP   0x76543210
0102 
0103 #define CPSW_VLAN_AWARE     BIT(1)
0104 #define CPSW_RX_VLAN_ENCAP  BIT(2)
0105 #define CPSW_ALE_VLAN_AWARE 1
0106 
0107 #define CPSW_FIFO_NORMAL_MODE       (0 << 16)
0108 #define CPSW_FIFO_DUAL_MAC_MODE     (1 << 16)
0109 #define CPSW_FIFO_RATE_LIMIT_MODE   (2 << 16)
0110 
0111 #define CPSW_INTPACEEN      (0x3f << 16)
0112 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
0113 #define CPSW_CMINTMAX_CNT   63
0114 #define CPSW_CMINTMIN_CNT   2
0115 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
0116 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
0117 
0118 #define IRQ_NUM         2
0119 #define CPSW_MAX_QUEUES     8
0120 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
0121 #define CPSW_ALE_AGEOUT_DEFAULT     10 /* sec */
0122 #define CPSW_FIFO_QUEUE_TYPE_SHIFT  16
0123 #define CPSW_FIFO_SHAPE_EN_SHIFT    16
0124 #define CPSW_FIFO_RATE_EN_SHIFT     20
0125 #define CPSW_TC_NUM         4
0126 #define CPSW_FIFO_SHAPERS_NUM       (CPSW_TC_NUM - 1)
0127 #define CPSW_PCT_MASK           0x7f
0128 #define CPSW_BD_RAM_SIZE        0x2000
0129 
0130 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT   29
0131 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK     GENMASK(2, 0)
0132 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT    16
0133 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT   8
0134 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0)
0135 enum {
0136     CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
0137     CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
0138     CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
0139     CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
0140 };
0141 
0142 struct cpsw_wr_regs {
0143     u32 id_ver;
0144     u32 soft_reset;
0145     u32 control;
0146     u32 int_control;
0147     u32 rx_thresh_en;
0148     u32 rx_en;
0149     u32 tx_en;
0150     u32 misc_en;
0151     u32 mem_allign1[8];
0152     u32 rx_thresh_stat;
0153     u32 rx_stat;
0154     u32 tx_stat;
0155     u32 misc_stat;
0156     u32 mem_allign2[8];
0157     u32 rx_imax;
0158     u32 tx_imax;
0159 
0160 };
0161 
0162 struct cpsw_ss_regs {
0163     u32 id_ver;
0164     u32 control;
0165     u32 soft_reset;
0166     u32 stat_port_en;
0167     u32 ptype;
0168     u32 soft_idle;
0169     u32 thru_rate;
0170     u32 gap_thresh;
0171     u32 tx_start_wds;
0172     u32 flow_control;
0173     u32 vlan_ltype;
0174     u32 ts_ltype;
0175     u32 dlr_ltype;
0176 };
0177 
0178 /* CPSW_PORT_V1 */
0179 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
0180 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
0181 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
0182 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
0183 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
0184 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
0185 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
0186 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
0187 
0188 /* CPSW_PORT_V2 */
0189 #define CPSW2_CONTROL       0x00 /* Control Register */
0190 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
0191 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
0192 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
0193 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
0194 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
0195 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
0196 
0197 /* CPSW_PORT_V1 and V2 */
0198 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
0199 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
0200 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
0201 
0202 /* CPSW_PORT_V2 only */
0203 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
0204 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
0205 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
0206 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
0207 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
0208 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
0209 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
0210 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
0211 
0212 /* Bit definitions for the CPSW2_CONTROL register */
0213 #define PASS_PRI_TAGGED     BIT(24) /* Pass Priority Tagged */
0214 #define VLAN_LTYPE2_EN      BIT(21) /* VLAN LTYPE 2 enable */
0215 #define VLAN_LTYPE1_EN      BIT(20) /* VLAN LTYPE 1 enable */
0216 #define DSCP_PRI_EN         BIT(16) /* DSCP Priority Enable */
0217 #define TS_107              BIT(15) /* Tyme Sync Dest IP Address 107 */
0218 #define TS_320              BIT(14) /* Time Sync Dest Port 320 enable */
0219 #define TS_319              BIT(13) /* Time Sync Dest Port 319 enable */
0220 #define TS_132              BIT(12) /* Time Sync Dest IP Addr 132 enable */
0221 #define TS_131              BIT(11) /* Time Sync Dest IP Addr 131 enable */
0222 #define TS_130              BIT(10) /* Time Sync Dest IP Addr 130 enable */
0223 #define TS_129              BIT(9)  /* Time Sync Dest IP Addr 129 enable */
0224 #define TS_TTL_NONZERO      BIT(8)  /* Time Sync Time To Live Non-zero enable */
0225 #define TS_ANNEX_F_EN       BIT(6)  /* Time Sync Annex F enable */
0226 #define TS_ANNEX_D_EN       BIT(4)  /* Time Sync Annex D enable */
0227 #define TS_LTYPE2_EN        BIT(3)  /* Time Sync LTYPE 2 enable */
0228 #define TS_LTYPE1_EN        BIT(2)  /* Time Sync LTYPE 1 enable */
0229 #define TS_TX_EN            BIT(1)  /* Time Sync Transmit Enable */
0230 #define TS_RX_EN            BIT(0)  /* Time Sync Receive Enable */
0231 
0232 #define CTRL_V2_TS_BITS \
0233     (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
0234      TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN)
0235 
0236 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
0237 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
0238 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
0239 
0240 
0241 #define CTRL_V3_TS_BITS \
0242     (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
0243      TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
0244      TS_LTYPE1_EN | VLAN_LTYPE1_EN)
0245 
0246 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
0247 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
0248 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
0249 
0250 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
0251 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
0252 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
0253 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
0254 #define TS_MSG_TYPE_EN_MASK      (0xffff)
0255 
0256 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
0257 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
0258 
0259 /* Bit definitions for the CPSW1_TS_CTL register */
0260 #define CPSW_V1_TS_RX_EN        BIT(0)
0261 #define CPSW_V1_TS_TX_EN        BIT(4)
0262 #define CPSW_V1_MSG_TYPE_OFS        16
0263 
0264 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
0265 #define CPSW_V1_SEQ_ID_OFS_SHIFT    16
0266 
0267 #define CPSW_MAX_BLKS_TX        15
0268 #define CPSW_MAX_BLKS_TX_SHIFT      4
0269 #define CPSW_MAX_BLKS_RX        5
0270 
0271 struct cpsw_host_regs {
0272     u32 max_blks;
0273     u32 blk_cnt;
0274     u32 tx_in_ctl;
0275     u32 port_vlan;
0276     u32 tx_pri_map;
0277     u32 cpdma_tx_pri_map;
0278     u32 cpdma_rx_chan_map;
0279 };
0280 
0281 struct cpsw_slave_data {
0282     struct device_node *slave_node;
0283     struct device_node *phy_node;
0284     char        phy_id[MII_BUS_ID_SIZE];
0285     phy_interface_t phy_if;
0286     u8      mac_addr[ETH_ALEN];
0287     u16     dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */
0288     struct phy  *ifphy;
0289     bool        disabled;
0290 };
0291 
0292 struct cpsw_platform_data {
0293     struct cpsw_slave_data  *slave_data;
0294     u32 ss_reg_ofs; /* Subsystem control register offset */
0295     u32 channels;   /* number of cpdma channels (symmetric) */
0296     u32 slaves;     /* number of slave cpgmac ports */
0297     u32 active_slave;/* time stamping, ethtool and SIOCGMIIPHY slave */
0298     u32 bd_ram_size;    /*buffer descriptor ram size */
0299     u32 mac_control;    /* Mac control register */
0300     u16 default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
0301     bool    dual_emac;  /* Enable Dual EMAC mode */
0302 };
0303 
0304 struct cpsw_slave {
0305     void __iomem            *regs;
0306     int             slave_num;
0307     u32             mac_control;
0308     struct cpsw_slave_data      *data;
0309     struct phy_device       *phy;
0310     struct net_device       *ndev;
0311     u32             port_vlan;
0312     struct cpsw_sl          *mac_sl;
0313 };
0314 
0315 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
0316 {
0317     return readl_relaxed(slave->regs + offset);
0318 }
0319 
0320 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
0321 {
0322     writel_relaxed(val, slave->regs + offset);
0323 }
0324 
0325 struct cpsw_vector {
0326     struct cpdma_chan *ch;
0327     int budget;
0328 };
0329 
0330 struct cpsw_common {
0331     struct device           *dev;
0332     struct cpsw_platform_data   data;
0333     struct napi_struct      napi_rx;
0334     struct napi_struct      napi_tx;
0335     struct cpsw_ss_regs __iomem *regs;
0336     struct cpsw_wr_regs __iomem *wr_regs;
0337     u8 __iomem          *hw_stats;
0338     struct cpsw_host_regs __iomem   *host_port_regs;
0339     u32             version;
0340     u32             coal_intvl;
0341     u32             bus_freq_mhz;
0342     int             rx_packet_max;
0343     int             descs_pool_size;
0344     struct cpsw_slave       *slaves;
0345     struct cpdma_ctlr       *dma;
0346     struct cpsw_vector      txv[CPSW_MAX_QUEUES];
0347     struct cpsw_vector      rxv[CPSW_MAX_QUEUES];
0348     struct cpsw_ale         *ale;
0349     bool                quirk_irq;
0350     bool                rx_irq_disabled;
0351     bool                tx_irq_disabled;
0352     u32 irqs_table[IRQ_NUM];
0353     int misc_irq;
0354     struct cpts         *cpts;
0355     struct devlink *devlink;
0356     int             rx_ch_num, tx_ch_num;
0357     int             speed;
0358     int             usage_count;
0359     struct page_pool        *page_pool[CPSW_MAX_QUEUES];
0360     u8 br_members;
0361     struct net_device *hw_bridge_dev;
0362     bool ale_bypass;
0363     u8 base_mac[ETH_ALEN];
0364 };
0365 
0366 struct cpsw_ale_ratelimit {
0367     unsigned long cookie;
0368     u64 rate_packet_ps;
0369 };
0370 
0371 struct cpsw_priv {
0372     struct net_device       *ndev;
0373     struct device           *dev;
0374     u32             msg_enable;
0375     u8              mac_addr[ETH_ALEN];
0376     bool                rx_pause;
0377     bool                tx_pause;
0378     bool                mqprio_hw;
0379     int             fifo_bw[CPSW_TC_NUM];
0380     int             shp_cfg_speed;
0381     int             tx_ts_enabled;
0382     int             rx_ts_enabled;
0383     struct bpf_prog         *xdp_prog;
0384     struct xdp_rxq_info     xdp_rxq[CPSW_MAX_QUEUES];
0385     struct xdp_attachment_info  xdpi;
0386 
0387     u32 emac_port;
0388     struct cpsw_common *cpsw;
0389     int offload_fwd_mark;
0390     u32 tx_packet_min;
0391     struct cpsw_ale_ratelimit ale_bc_ratelimit;
0392     struct cpsw_ale_ratelimit ale_mc_ratelimit;
0393 };
0394 
0395 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
0396 #define napi_to_cpsw(napi)  container_of(napi, struct cpsw_common, napi)
0397 
0398 extern int (*cpsw_slave_index)(struct cpsw_common *cpsw,
0399                    struct cpsw_priv *priv);
0400 
0401 struct addr_sync_ctx {
0402     struct net_device *ndev;
0403     const u8 *addr;     /* address to be synched */
0404     int consumed;       /* number of address instances */
0405     int flush;      /* flush flag */
0406 };
0407 
0408 #define CPSW_XMETA_OFFSET   ALIGN(sizeof(struct xdp_frame), sizeof(long))
0409 
0410 #define CPSW_XDP_CONSUMED       1
0411 #define CPSW_XDP_PASS           0
0412 
0413 struct __aligned(sizeof(long)) cpsw_meta_xdp {
0414     struct net_device *ndev;
0415     int ch;
0416 };
0417 
0418 /* The buf includes headroom compatible with both skb and xdpf */
0419 #define CPSW_HEADROOM_NA (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + NET_IP_ALIGN)
0420 
0421 static inline int cpsw_is_xdpf_handle(void *handle)
0422 {
0423     return (unsigned long)handle & BIT(0);
0424 }
0425 
0426 static inline void *cpsw_xdpf_to_handle(struct xdp_frame *xdpf)
0427 {
0428     return (void *)((unsigned long)xdpf | BIT(0));
0429 }
0430 
0431 static inline struct xdp_frame *cpsw_handle_to_xdpf(void *handle)
0432 {
0433     return (struct xdp_frame *)((unsigned long)handle & ~BIT(0));
0434 }
0435 
0436 int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs,
0437              int ale_ageout, phys_addr_t desc_mem_phys,
0438              int descs_pool_size);
0439 void cpsw_split_res(struct cpsw_common *cpsw);
0440 int cpsw_fill_rx_channels(struct cpsw_priv *priv);
0441 void cpsw_intr_enable(struct cpsw_common *cpsw);
0442 void cpsw_intr_disable(struct cpsw_common *cpsw);
0443 void cpsw_tx_handler(void *token, int len, int status);
0444 int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw);
0445 void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw);
0446 int cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf);
0447 int cpsw_xdp_tx_frame(struct cpsw_priv *priv, struct xdp_frame *xdpf,
0448               struct page *page, int port);
0449 int cpsw_run_xdp(struct cpsw_priv *priv, int ch, struct xdp_buff *xdp,
0450          struct page *page, int port, int *len);
0451 irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id);
0452 irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id);
0453 irqreturn_t cpsw_misc_interrupt(int irq, void *dev_id);
0454 int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget);
0455 int cpsw_tx_poll(struct napi_struct *napi_tx, int budget);
0456 int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget);
0457 int cpsw_rx_poll(struct napi_struct *napi_rx, int budget);
0458 void cpsw_rx_vlan_encap(struct sk_buff *skb);
0459 void soft_reset(const char *module, void __iomem *reg);
0460 void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv);
0461 void cpsw_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue);
0462 int cpsw_need_resplit(struct cpsw_common *cpsw);
0463 int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd);
0464 int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate);
0465 int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
0466               void *type_data);
0467 bool cpsw_shp_is_off(struct cpsw_priv *priv);
0468 void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv);
0469 void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv);
0470 void cpsw_qos_clsflower_resume(struct cpsw_priv *priv);
0471 
0472 /* ethtool */
0473 u32 cpsw_get_msglevel(struct net_device *ndev);
0474 void cpsw_set_msglevel(struct net_device *ndev, u32 value);
0475 int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal,
0476               struct kernel_ethtool_coalesce *kernel_coal,
0477               struct netlink_ext_ack *extack);
0478 int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal,
0479               struct kernel_ethtool_coalesce *kernel_coal,
0480               struct netlink_ext_ack *extack);
0481 int cpsw_get_sset_count(struct net_device *ndev, int sset);
0482 void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data);
0483 void cpsw_get_ethtool_stats(struct net_device *ndev,
0484                 struct ethtool_stats *stats, u64 *data);
0485 void cpsw_get_pauseparam(struct net_device *ndev,
0486              struct ethtool_pauseparam *pause);
0487 void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
0488 int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
0489 int cpsw_get_regs_len(struct net_device *ndev);
0490 void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p);
0491 int cpsw_ethtool_op_begin(struct net_device *ndev);
0492 void cpsw_ethtool_op_complete(struct net_device *ndev);
0493 void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch);
0494 int cpsw_get_link_ksettings(struct net_device *ndev,
0495                 struct ethtool_link_ksettings *ecmd);
0496 int cpsw_set_link_ksettings(struct net_device *ndev,
0497                 const struct ethtool_link_ksettings *ecmd);
0498 int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata);
0499 int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata);
0500 int cpsw_nway_reset(struct net_device *ndev);
0501 void cpsw_get_ringparam(struct net_device *ndev,
0502             struct ethtool_ringparam *ering,
0503             struct kernel_ethtool_ringparam *kernel_ering,
0504             struct netlink_ext_ack *extack);
0505 int cpsw_set_ringparam(struct net_device *ndev,
0506                struct ethtool_ringparam *ering,
0507                struct kernel_ethtool_ringparam *kernel_ering,
0508                struct netlink_ext_ack *extack);
0509 int cpsw_set_channels_common(struct net_device *ndev,
0510                  struct ethtool_channels *chs,
0511                  cpdma_handler_fn rx_handler);
0512 int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info);
0513 
0514 #endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */
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