Back to home page

OSCL-LXR
 
 

     

0001 /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver
0002  *
0003  * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)
0004  *
0005  * This program is dual-licensed; you may select either version 2 of
0006  * the GNU General Public License ("GPL") or BSD license ("BSD").
0007  *
0008  * This Synopsys DWC XLGMAC software driver and associated documentation
0009  * (hereinafter the "Software") is an unsupported proprietary work of
0010  * Synopsys, Inc. unless otherwise expressly agreed to in writing between
0011  * Synopsys and you. The Software IS NOT an item of Licensed Software or a
0012  * Licensed Product under any End User Software License Agreement or
0013  * Agreement for Licensed Products with Synopsys or any supplement thereto.
0014  * Synopsys is a registered trademark of Synopsys, Inc. Other names included
0015  * in the SOFTWARE may be the trademarks of their respective owners.
0016  */
0017 
0018 #ifndef __DWC_XLGMAC_H__
0019 #define __DWC_XLGMAC_H__
0020 
0021 #include <linux/dma-mapping.h>
0022 #include <linux/netdevice.h>
0023 #include <linux/workqueue.h>
0024 #include <linux/phy.h>
0025 #include <linux/if_vlan.h>
0026 #include <linux/bitops.h>
0027 #include <linux/timecounter.h>
0028 
0029 #define XLGMAC_DRV_NAME         "dwc-xlgmac"
0030 #define XLGMAC_DRV_VERSION      "1.0.0"
0031 #define XLGMAC_DRV_DESC         "Synopsys DWC XLGMAC Driver"
0032 
0033 /* Descriptor related parameters */
0034 #define XLGMAC_TX_DESC_CNT      1024
0035 #define XLGMAC_TX_DESC_MIN_FREE     (XLGMAC_TX_DESC_CNT >> 3)
0036 #define XLGMAC_TX_DESC_MAX_PROC     (XLGMAC_TX_DESC_CNT >> 1)
0037 #define XLGMAC_RX_DESC_CNT      1024
0038 #define XLGMAC_RX_DESC_MAX_DIRTY    (XLGMAC_RX_DESC_CNT >> 3)
0039 
0040 /* Descriptors required for maximum contiguous TSO/GSO packet */
0041 #define XLGMAC_TX_MAX_SPLIT \
0042     ((GSO_LEGACY_MAX_SIZE / XLGMAC_TX_MAX_BUF_SIZE) + 1)
0043 
0044 /* Maximum possible descriptors needed for a SKB */
0045 #define XLGMAC_TX_MAX_DESC_NR   (MAX_SKB_FRAGS + XLGMAC_TX_MAX_SPLIT + 2)
0046 
0047 #define XLGMAC_TX_MAX_BUF_SIZE  (0x3fff & ~(64 - 1))
0048 #define XLGMAC_RX_MIN_BUF_SIZE  (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
0049 #define XLGMAC_RX_BUF_ALIGN 64
0050 
0051 /* Maximum Size for Splitting the Header Data
0052  * Keep in sync with SKB_ALLOC_SIZE
0053  * 3'b000: 64 bytes, 3'b001: 128 bytes
0054  * 3'b010: 256 bytes, 3'b011: 512 bytes
0055  * 3'b100: 1023 bytes ,   3'b101'3'b111: Reserved
0056  */
0057 #define XLGMAC_SPH_HDSMS_SIZE       3
0058 #define XLGMAC_SKB_ALLOC_SIZE       512
0059 
0060 #define XLGMAC_MAX_FIFO         81920
0061 
0062 #define XLGMAC_MAX_DMA_CHANNELS     16
0063 #define XLGMAC_DMA_STOP_TIMEOUT     5
0064 #define XLGMAC_DMA_INTERRUPT_MASK   0x31c7
0065 
0066 /* Default coalescing parameters */
0067 #define XLGMAC_INIT_DMA_TX_USECS    1000
0068 #define XLGMAC_INIT_DMA_TX_FRAMES   25
0069 #define XLGMAC_INIT_DMA_RX_USECS    30
0070 #define XLGMAC_INIT_DMA_RX_FRAMES   25
0071 #define XLGMAC_MAX_DMA_RIWT     0xff
0072 #define XLGMAC_MIN_DMA_RIWT     0x01
0073 
0074 /* Flow control queue count */
0075 #define XLGMAC_MAX_FLOW_CONTROL_QUEUES  8
0076 
0077 /* System clock is 125 MHz */
0078 #define XLGMAC_SYSCLOCK         125000000
0079 
0080 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
0081 #define XLGMAC_MAC_HASH_TABLE_SIZE  8
0082 
0083 /* Receive Side Scaling */
0084 #define XLGMAC_RSS_HASH_KEY_SIZE    40
0085 #define XLGMAC_RSS_MAX_TABLE_SIZE   256
0086 #define XLGMAC_RSS_LOOKUP_TABLE_TYPE    0
0087 #define XLGMAC_RSS_HASH_KEY_TYPE    1
0088 
0089 #define XLGMAC_STD_PACKET_MTU       1500
0090 #define XLGMAC_JUMBO_PACKET_MTU     9000
0091 
0092 /* Helper macro for descriptor handling
0093  *  Always use XLGMAC_GET_DESC_DATA to access the descriptor data
0094  */
0095 #define XLGMAC_GET_DESC_DATA(ring, idx) ({              \
0096     typeof(ring) _ring = (ring);                    \
0097     ((_ring)->desc_data_head +                  \
0098      ((idx) & ((_ring)->dma_desc_count - 1)));          \
0099 })
0100 
0101 #define XLGMAC_GET_REG_BITS(var, pos, len) ({               \
0102     typeof(pos) _pos = (pos);                   \
0103     typeof(len) _len = (len);                   \
0104     ((var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos);     \
0105 })
0106 
0107 #define XLGMAC_GET_REG_BITS_LE(var, pos, len) ({            \
0108     typeof(pos) _pos = (pos);                   \
0109     typeof(len) _len = (len);                   \
0110     typeof(var) _var = le32_to_cpu((var));              \
0111     ((_var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos);        \
0112 })
0113 
0114 #define XLGMAC_SET_REG_BITS(var, pos, len, val) ({          \
0115     typeof(var) _var = (var);                   \
0116     typeof(pos) _pos = (pos);                   \
0117     typeof(len) _len = (len);                   \
0118     typeof(val) _val = (val);                   \
0119     _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos);     \
0120     _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val;     \
0121 })
0122 
0123 #define XLGMAC_SET_REG_BITS_LE(var, pos, len, val) ({           \
0124     typeof(var) _var = (var);                   \
0125     typeof(pos) _pos = (pos);                   \
0126     typeof(len) _len = (len);                   \
0127     typeof(val) _val = (val);                   \
0128     _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos);     \
0129     _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val;     \
0130     cpu_to_le32(_var);                      \
0131 })
0132 
0133 struct xlgmac_pdata;
0134 
0135 enum xlgmac_int {
0136     XLGMAC_INT_DMA_CH_SR_TI,
0137     XLGMAC_INT_DMA_CH_SR_TPS,
0138     XLGMAC_INT_DMA_CH_SR_TBU,
0139     XLGMAC_INT_DMA_CH_SR_RI,
0140     XLGMAC_INT_DMA_CH_SR_RBU,
0141     XLGMAC_INT_DMA_CH_SR_RPS,
0142     XLGMAC_INT_DMA_CH_SR_TI_RI,
0143     XLGMAC_INT_DMA_CH_SR_FBE,
0144     XLGMAC_INT_DMA_ALL,
0145 };
0146 
0147 struct xlgmac_stats {
0148     /* MMC TX counters */
0149     u64 txoctetcount_gb;
0150     u64 txframecount_gb;
0151     u64 txbroadcastframes_g;
0152     u64 txmulticastframes_g;
0153     u64 tx64octets_gb;
0154     u64 tx65to127octets_gb;
0155     u64 tx128to255octets_gb;
0156     u64 tx256to511octets_gb;
0157     u64 tx512to1023octets_gb;
0158     u64 tx1024tomaxoctets_gb;
0159     u64 txunicastframes_gb;
0160     u64 txmulticastframes_gb;
0161     u64 txbroadcastframes_gb;
0162     u64 txunderflowerror;
0163     u64 txoctetcount_g;
0164     u64 txframecount_g;
0165     u64 txpauseframes;
0166     u64 txvlanframes_g;
0167 
0168     /* MMC RX counters */
0169     u64 rxframecount_gb;
0170     u64 rxoctetcount_gb;
0171     u64 rxoctetcount_g;
0172     u64 rxbroadcastframes_g;
0173     u64 rxmulticastframes_g;
0174     u64 rxcrcerror;
0175     u64 rxrunterror;
0176     u64 rxjabbererror;
0177     u64 rxundersize_g;
0178     u64 rxoversize_g;
0179     u64 rx64octets_gb;
0180     u64 rx65to127octets_gb;
0181     u64 rx128to255octets_gb;
0182     u64 rx256to511octets_gb;
0183     u64 rx512to1023octets_gb;
0184     u64 rx1024tomaxoctets_gb;
0185     u64 rxunicastframes_g;
0186     u64 rxlengtherror;
0187     u64 rxoutofrangetype;
0188     u64 rxpauseframes;
0189     u64 rxfifooverflow;
0190     u64 rxvlanframes_gb;
0191     u64 rxwatchdogerror;
0192 
0193     /* Extra counters */
0194     u64 tx_tso_packets;
0195     u64 rx_split_header_packets;
0196     u64 tx_process_stopped;
0197     u64 rx_process_stopped;
0198     u64 tx_buffer_unavailable;
0199     u64 rx_buffer_unavailable;
0200     u64 fatal_bus_error;
0201     u64 tx_vlan_packets;
0202     u64 rx_vlan_packets;
0203     u64 napi_poll_isr;
0204     u64 napi_poll_txtimer;
0205 };
0206 
0207 struct xlgmac_ring_buf {
0208     struct sk_buff *skb;
0209     dma_addr_t skb_dma;
0210     unsigned int skb_len;
0211 };
0212 
0213 /* Common Tx and Rx DMA hardware descriptor */
0214 struct xlgmac_dma_desc {
0215     __le32 desc0;
0216     __le32 desc1;
0217     __le32 desc2;
0218     __le32 desc3;
0219 };
0220 
0221 /* Page allocation related values */
0222 struct xlgmac_page_alloc {
0223     struct page *pages;
0224     unsigned int pages_len;
0225     unsigned int pages_offset;
0226 
0227     dma_addr_t pages_dma;
0228 };
0229 
0230 /* Ring entry buffer data */
0231 struct xlgmac_buffer_data {
0232     struct xlgmac_page_alloc pa;
0233     struct xlgmac_page_alloc pa_unmap;
0234 
0235     dma_addr_t dma_base;
0236     unsigned long dma_off;
0237     unsigned int dma_len;
0238 };
0239 
0240 /* Tx-related desc data */
0241 struct xlgmac_tx_desc_data {
0242     unsigned int packets;       /* BQL packet count */
0243     unsigned int bytes;     /* BQL byte count */
0244 };
0245 
0246 /* Rx-related desc data */
0247 struct xlgmac_rx_desc_data {
0248     struct xlgmac_buffer_data hdr;  /* Header locations */
0249     struct xlgmac_buffer_data buf;  /* Payload locations */
0250 
0251     unsigned short hdr_len;     /* Length of received header */
0252     unsigned short len;     /* Length of received packet */
0253 };
0254 
0255 struct xlgmac_pkt_info {
0256     struct sk_buff *skb;
0257 
0258     unsigned int attributes;
0259 
0260     unsigned int errors;
0261 
0262     /* descriptors needed for this packet */
0263     unsigned int desc_count;
0264     unsigned int length;
0265 
0266     unsigned int tx_packets;
0267     unsigned int tx_bytes;
0268 
0269     unsigned int header_len;
0270     unsigned int tcp_header_len;
0271     unsigned int tcp_payload_len;
0272     unsigned short mss;
0273 
0274     unsigned short vlan_ctag;
0275 
0276     u64 rx_tstamp;
0277 
0278     u32 rss_hash;
0279     enum pkt_hash_types rss_hash_type;
0280 };
0281 
0282 struct xlgmac_desc_data {
0283     /* dma_desc: Virtual address of descriptor
0284      *  dma_desc_addr: DMA address of descriptor
0285      */
0286     struct xlgmac_dma_desc *dma_desc;
0287     dma_addr_t dma_desc_addr;
0288 
0289     /* skb: Virtual address of SKB
0290      *  skb_dma: DMA address of SKB data
0291      *  skb_dma_len: Length of SKB DMA area
0292      */
0293     struct sk_buff *skb;
0294     dma_addr_t skb_dma;
0295     unsigned int skb_dma_len;
0296 
0297     /* Tx/Rx -related data */
0298     struct xlgmac_tx_desc_data tx;
0299     struct xlgmac_rx_desc_data rx;
0300 
0301     unsigned int mapped_as_page;
0302 
0303     /* Incomplete receive save location.  If the budget is exhausted
0304      * or the last descriptor (last normal descriptor or a following
0305      * context descriptor) has not been DMA'd yet the current state
0306      * of the receive processing needs to be saved.
0307      */
0308     unsigned int state_saved;
0309     struct {
0310         struct sk_buff *skb;
0311         unsigned int len;
0312         unsigned int error;
0313     } state;
0314 };
0315 
0316 struct xlgmac_ring {
0317     /* Per packet related information */
0318     struct xlgmac_pkt_info pkt_info;
0319 
0320     /* Virtual/DMA addresses of DMA descriptor list and the total count */
0321     struct xlgmac_dma_desc *dma_desc_head;
0322     dma_addr_t dma_desc_head_addr;
0323     unsigned int dma_desc_count;
0324 
0325     /* Array of descriptor data corresponding the DMA descriptor
0326      * (always use the XLGMAC_GET_DESC_DATA macro to access this data)
0327      */
0328     struct xlgmac_desc_data *desc_data_head;
0329 
0330     /* Page allocation for RX buffers */
0331     struct xlgmac_page_alloc rx_hdr_pa;
0332     struct xlgmac_page_alloc rx_buf_pa;
0333 
0334     /* Ring index values
0335      *  cur   - Tx: index of descriptor to be used for current transfer
0336      *          Rx: index of descriptor to check for packet availability
0337      *  dirty - Tx: index of descriptor to check for transfer complete
0338      *          Rx: index of descriptor to check for buffer reallocation
0339      */
0340     unsigned int cur;
0341     unsigned int dirty;
0342 
0343     /* Coalesce frame count used for interrupt bit setting */
0344     unsigned int coalesce_count;
0345 
0346     union {
0347         struct {
0348             unsigned int xmit_more;
0349             unsigned int queue_stopped;
0350             unsigned short cur_mss;
0351             unsigned short cur_vlan_ctag;
0352         } tx;
0353     };
0354 } ____cacheline_aligned;
0355 
0356 struct xlgmac_channel {
0357     char name[16];
0358 
0359     /* Address of private data area for device */
0360     struct xlgmac_pdata *pdata;
0361 
0362     /* Queue index and base address of queue's DMA registers */
0363     unsigned int queue_index;
0364     void __iomem *dma_regs;
0365 
0366     /* Per channel interrupt irq number */
0367     int dma_irq;
0368     char dma_irq_name[IFNAMSIZ + 32];
0369 
0370     /* Netdev related settings */
0371     struct napi_struct napi;
0372 
0373     unsigned int saved_ier;
0374 
0375     unsigned int tx_timer_active;
0376     struct timer_list tx_timer;
0377 
0378     struct xlgmac_ring *tx_ring;
0379     struct xlgmac_ring *rx_ring;
0380 } ____cacheline_aligned;
0381 
0382 struct xlgmac_desc_ops {
0383     int (*alloc_channels_and_rings)(struct xlgmac_pdata *pdata);
0384     void (*free_channels_and_rings)(struct xlgmac_pdata *pdata);
0385     int (*map_tx_skb)(struct xlgmac_channel *channel,
0386               struct sk_buff *skb);
0387     int (*map_rx_buffer)(struct xlgmac_pdata *pdata,
0388                  struct xlgmac_ring *ring,
0389             struct xlgmac_desc_data *desc_data);
0390     void (*unmap_desc_data)(struct xlgmac_pdata *pdata,
0391                 struct xlgmac_desc_data *desc_data);
0392     void (*tx_desc_init)(struct xlgmac_pdata *pdata);
0393     void (*rx_desc_init)(struct xlgmac_pdata *pdata);
0394 };
0395 
0396 struct xlgmac_hw_ops {
0397     int (*init)(struct xlgmac_pdata *pdata);
0398     int (*exit)(struct xlgmac_pdata *pdata);
0399 
0400     int (*tx_complete)(struct xlgmac_dma_desc *dma_desc);
0401 
0402     void (*enable_tx)(struct xlgmac_pdata *pdata);
0403     void (*disable_tx)(struct xlgmac_pdata *pdata);
0404     void (*enable_rx)(struct xlgmac_pdata *pdata);
0405     void (*disable_rx)(struct xlgmac_pdata *pdata);
0406 
0407     int (*enable_int)(struct xlgmac_channel *channel,
0408               enum xlgmac_int int_id);
0409     int (*disable_int)(struct xlgmac_channel *channel,
0410                enum xlgmac_int int_id);
0411     void (*dev_xmit)(struct xlgmac_channel *channel);
0412     int (*dev_read)(struct xlgmac_channel *channel);
0413 
0414     int (*set_mac_address)(struct xlgmac_pdata *pdata, const u8 *addr);
0415     int (*config_rx_mode)(struct xlgmac_pdata *pdata);
0416     int (*enable_rx_csum)(struct xlgmac_pdata *pdata);
0417     int (*disable_rx_csum)(struct xlgmac_pdata *pdata);
0418 
0419     /* For MII speed configuration */
0420     int (*set_xlgmii_25000_speed)(struct xlgmac_pdata *pdata);
0421     int (*set_xlgmii_40000_speed)(struct xlgmac_pdata *pdata);
0422     int (*set_xlgmii_50000_speed)(struct xlgmac_pdata *pdata);
0423     int (*set_xlgmii_100000_speed)(struct xlgmac_pdata *pdata);
0424 
0425     /* For descriptor related operation */
0426     void (*tx_desc_init)(struct xlgmac_channel *channel);
0427     void (*rx_desc_init)(struct xlgmac_channel *channel);
0428     void (*tx_desc_reset)(struct xlgmac_desc_data *desc_data);
0429     void (*rx_desc_reset)(struct xlgmac_pdata *pdata,
0430                   struct xlgmac_desc_data *desc_data,
0431             unsigned int index);
0432     int (*is_last_desc)(struct xlgmac_dma_desc *dma_desc);
0433     int (*is_context_desc)(struct xlgmac_dma_desc *dma_desc);
0434     void (*tx_start_xmit)(struct xlgmac_channel *channel,
0435                   struct xlgmac_ring *ring);
0436 
0437     /* For Flow Control */
0438     int (*config_tx_flow_control)(struct xlgmac_pdata *pdata);
0439     int (*config_rx_flow_control)(struct xlgmac_pdata *pdata);
0440 
0441     /* For Vlan related config */
0442     int (*enable_rx_vlan_stripping)(struct xlgmac_pdata *pdata);
0443     int (*disable_rx_vlan_stripping)(struct xlgmac_pdata *pdata);
0444     int (*enable_rx_vlan_filtering)(struct xlgmac_pdata *pdata);
0445     int (*disable_rx_vlan_filtering)(struct xlgmac_pdata *pdata);
0446     int (*update_vlan_hash_table)(struct xlgmac_pdata *pdata);
0447 
0448     /* For RX coalescing */
0449     int (*config_rx_coalesce)(struct xlgmac_pdata *pdata);
0450     int (*config_tx_coalesce)(struct xlgmac_pdata *pdata);
0451     unsigned int (*usec_to_riwt)(struct xlgmac_pdata *pdata,
0452                      unsigned int usec);
0453     unsigned int (*riwt_to_usec)(struct xlgmac_pdata *pdata,
0454                      unsigned int riwt);
0455 
0456     /* For RX and TX threshold config */
0457     int (*config_rx_threshold)(struct xlgmac_pdata *pdata,
0458                    unsigned int val);
0459     int (*config_tx_threshold)(struct xlgmac_pdata *pdata,
0460                    unsigned int val);
0461 
0462     /* For RX and TX Store and Forward Mode config */
0463     int (*config_rsf_mode)(struct xlgmac_pdata *pdata,
0464                    unsigned int val);
0465     int (*config_tsf_mode)(struct xlgmac_pdata *pdata,
0466                    unsigned int val);
0467 
0468     /* For TX DMA Operate on Second Frame config */
0469     int (*config_osp_mode)(struct xlgmac_pdata *pdata);
0470 
0471     /* For RX and TX PBL config */
0472     int (*config_rx_pbl_val)(struct xlgmac_pdata *pdata);
0473     int (*get_rx_pbl_val)(struct xlgmac_pdata *pdata);
0474     int (*config_tx_pbl_val)(struct xlgmac_pdata *pdata);
0475     int (*get_tx_pbl_val)(struct xlgmac_pdata *pdata);
0476     int (*config_pblx8)(struct xlgmac_pdata *pdata);
0477 
0478     /* For MMC statistics */
0479     void (*rx_mmc_int)(struct xlgmac_pdata *pdata);
0480     void (*tx_mmc_int)(struct xlgmac_pdata *pdata);
0481     void (*read_mmc_stats)(struct xlgmac_pdata *pdata);
0482 
0483     /* For Receive Side Scaling */
0484     int (*enable_rss)(struct xlgmac_pdata *pdata);
0485     int (*disable_rss)(struct xlgmac_pdata *pdata);
0486     int (*set_rss_hash_key)(struct xlgmac_pdata *pdata,
0487                 const u8 *key);
0488     int (*set_rss_lookup_table)(struct xlgmac_pdata *pdata,
0489                     const u32 *table);
0490 };
0491 
0492 /* This structure contains flags that indicate what hardware features
0493  * or configurations are present in the device.
0494  */
0495 struct xlgmac_hw_features {
0496     /* HW Version */
0497     unsigned int version;
0498 
0499     /* HW Feature Register0 */
0500     unsigned int phyifsel;      /* PHY interface support */
0501     unsigned int vlhash;        /* VLAN Hash Filter */
0502     unsigned int sma;       /* SMA(MDIO) Interface */
0503     unsigned int rwk;       /* PMT remote wake-up packet */
0504     unsigned int mgk;       /* PMT magic packet */
0505     unsigned int mmc;       /* RMON module */
0506     unsigned int aoe;       /* ARP Offload */
0507     unsigned int ts;        /* IEEE 1588-2008 Advanced Timestamp */
0508     unsigned int eee;       /* Energy Efficient Ethernet */
0509     unsigned int tx_coe;        /* Tx Checksum Offload */
0510     unsigned int rx_coe;        /* Rx Checksum Offload */
0511     unsigned int addn_mac;      /* Additional MAC Addresses */
0512     unsigned int ts_src;        /* Timestamp Source */
0513     unsigned int sa_vlan_ins;   /* Source Address or VLAN Insertion */
0514 
0515     /* HW Feature Register1 */
0516     unsigned int rx_fifo_size;  /* MTL Receive FIFO Size */
0517     unsigned int tx_fifo_size;  /* MTL Transmit FIFO Size */
0518     unsigned int adv_ts_hi;     /* Advance Timestamping High Word */
0519     unsigned int dma_width;     /* DMA width */
0520     unsigned int dcb;       /* DCB Feature */
0521     unsigned int sph;       /* Split Header Feature */
0522     unsigned int tso;       /* TCP Segmentation Offload */
0523     unsigned int dma_debug;     /* DMA Debug Registers */
0524     unsigned int rss;       /* Receive Side Scaling */
0525     unsigned int tc_cnt;        /* Number of Traffic Classes */
0526     unsigned int hash_table_size;   /* Hash Table Size */
0527     unsigned int l3l4_filter_num;   /* Number of L3-L4 Filters */
0528 
0529     /* HW Feature Register2 */
0530     unsigned int rx_q_cnt;      /* Number of MTL Receive Queues */
0531     unsigned int tx_q_cnt;      /* Number of MTL Transmit Queues */
0532     unsigned int rx_ch_cnt;     /* Number of DMA Receive Channels */
0533     unsigned int tx_ch_cnt;     /* Number of DMA Transmit Channels */
0534     unsigned int pps_out_num;   /* Number of PPS outputs */
0535     unsigned int aux_snap_num;  /* Number of Aux snapshot inputs */
0536 };
0537 
0538 struct xlgmac_resources {
0539     void __iomem *addr;
0540     int irq;
0541 };
0542 
0543 struct xlgmac_pdata {
0544     struct net_device *netdev;
0545     struct device *dev;
0546 
0547     struct xlgmac_hw_ops hw_ops;
0548     struct xlgmac_desc_ops desc_ops;
0549 
0550     /* Device statistics */
0551     struct xlgmac_stats stats;
0552 
0553     u32 msg_enable;
0554 
0555     /* MAC registers base */
0556     void __iomem *mac_regs;
0557 
0558     /* Hardware features of the device */
0559     struct xlgmac_hw_features hw_feat;
0560 
0561     struct work_struct restart_work;
0562 
0563     /* Rings for Tx/Rx on a DMA channel */
0564     struct xlgmac_channel *channel_head;
0565     unsigned int channel_count;
0566     unsigned int tx_ring_count;
0567     unsigned int rx_ring_count;
0568     unsigned int tx_desc_count;
0569     unsigned int rx_desc_count;
0570     unsigned int tx_q_count;
0571     unsigned int rx_q_count;
0572 
0573     /* Tx/Rx common settings */
0574     unsigned int pblx8;
0575 
0576     /* Tx settings */
0577     unsigned int tx_sf_mode;
0578     unsigned int tx_threshold;
0579     unsigned int tx_pbl;
0580     unsigned int tx_osp_mode;
0581 
0582     /* Rx settings */
0583     unsigned int rx_sf_mode;
0584     unsigned int rx_threshold;
0585     unsigned int rx_pbl;
0586 
0587     /* Tx coalescing settings */
0588     unsigned int tx_usecs;
0589     unsigned int tx_frames;
0590 
0591     /* Rx coalescing settings */
0592     unsigned int rx_riwt;
0593     unsigned int rx_usecs;
0594     unsigned int rx_frames;
0595 
0596     /* Current Rx buffer size */
0597     unsigned int rx_buf_size;
0598 
0599     /* Flow control settings */
0600     unsigned int tx_pause;
0601     unsigned int rx_pause;
0602 
0603     /* Device interrupt number */
0604     int dev_irq;
0605     unsigned int per_channel_irq;
0606     int channel_irq[XLGMAC_MAX_DMA_CHANNELS];
0607 
0608     /* Netdev related settings */
0609     unsigned char mac_addr[ETH_ALEN];
0610     netdev_features_t netdev_features;
0611     struct napi_struct napi;
0612 
0613     /* Filtering support */
0614     unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
0615 
0616     /* Device clocks */
0617     unsigned long sysclk_rate;
0618 
0619     /* RSS addressing mutex */
0620     struct mutex rss_mutex;
0621 
0622     /* Receive Side Scaling settings */
0623     u8 rss_key[XLGMAC_RSS_HASH_KEY_SIZE];
0624     u32 rss_table[XLGMAC_RSS_MAX_TABLE_SIZE];
0625     u32 rss_options;
0626 
0627     int phy_speed;
0628 
0629     char drv_name[32];
0630     char drv_ver[32];
0631 };
0632 
0633 void xlgmac_init_desc_ops(struct xlgmac_desc_ops *desc_ops);
0634 void xlgmac_init_hw_ops(struct xlgmac_hw_ops *hw_ops);
0635 const struct net_device_ops *xlgmac_get_netdev_ops(void);
0636 const struct ethtool_ops *xlgmac_get_ethtool_ops(void);
0637 void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata,
0638              struct xlgmac_ring *ring,
0639              unsigned int idx,
0640              unsigned int count,
0641              unsigned int flag);
0642 void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata,
0643              struct xlgmac_ring *ring,
0644              unsigned int idx);
0645 void xlgmac_print_pkt(struct net_device *netdev,
0646               struct sk_buff *skb, bool tx_rx);
0647 void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata);
0648 void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata);
0649 int xlgmac_drv_probe(struct device *dev,
0650              struct xlgmac_resources *res);
0651 int xlgmac_drv_remove(struct device *dev);
0652 
0653 /* For debug prints */
0654 #ifdef XLGMAC_DEBUG
0655 #define XLGMAC_PR(fmt, args...) \
0656     pr_alert("[%s,%d]:" fmt, __func__, __LINE__, ## args)
0657 #else
0658 #define XLGMAC_PR(x...)     do { } while (0)
0659 #endif
0660 
0661 #endif /* __DWC_XLGMAC_H__ */
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!