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0001 /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver
0002  *
0003  * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)
0004  *
0005  * This program is dual-licensed; you may select either version 2 of
0006  * the GNU General Public License ("GPL") or BSD license ("BSD").
0007  *
0008  * This Synopsys DWC XLGMAC software driver and associated documentation
0009  * (hereinafter the "Software") is an unsupported proprietary work of
0010  * Synopsys, Inc. unless otherwise expressly agreed to in writing between
0011  * Synopsys and you. The Software IS NOT an item of Licensed Software or a
0012  * Licensed Product under any End User Software License Agreement or
0013  * Agreement for Licensed Products with Synopsys or any supplement thereto.
0014  * Synopsys is a registered trademark of Synopsys, Inc. Other names included
0015  * in the SOFTWARE may be the trademarks of their respective owners.
0016  */
0017 
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 
0021 #include "dwc-xlgmac.h"
0022 #include "dwc-xlgmac-reg.h"
0023 
0024 MODULE_LICENSE("Dual BSD/GPL");
0025 
0026 static int debug = -1;
0027 module_param(debug, int, 0644);
0028 MODULE_PARM_DESC(debug, "DWC ethernet debug level (0=none,...,16=all)");
0029 static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
0030                       NETIF_MSG_IFUP);
0031 
0032 static unsigned char dev_addr[6] = {0, 0x55, 0x7b, 0xb5, 0x7d, 0xf7};
0033 
0034 static void xlgmac_read_mac_addr(struct xlgmac_pdata *pdata)
0035 {
0036     struct net_device *netdev = pdata->netdev;
0037 
0038     /* Currently it uses a static mac address for test */
0039     memcpy(pdata->mac_addr, dev_addr, netdev->addr_len);
0040 }
0041 
0042 static void xlgmac_default_config(struct xlgmac_pdata *pdata)
0043 {
0044     pdata->tx_osp_mode = DMA_OSP_ENABLE;
0045     pdata->tx_sf_mode = MTL_TSF_ENABLE;
0046     pdata->rx_sf_mode = MTL_RSF_DISABLE;
0047     pdata->pblx8 = DMA_PBL_X8_ENABLE;
0048     pdata->tx_pbl = DMA_PBL_32;
0049     pdata->rx_pbl = DMA_PBL_32;
0050     pdata->tx_threshold = MTL_TX_THRESHOLD_128;
0051     pdata->rx_threshold = MTL_RX_THRESHOLD_128;
0052     pdata->tx_pause = 1;
0053     pdata->rx_pause = 1;
0054     pdata->phy_speed = SPEED_25000;
0055     pdata->sysclk_rate = XLGMAC_SYSCLOCK;
0056 
0057     strlcpy(pdata->drv_name, XLGMAC_DRV_NAME, sizeof(pdata->drv_name));
0058     strlcpy(pdata->drv_ver, XLGMAC_DRV_VERSION, sizeof(pdata->drv_ver));
0059 }
0060 
0061 static void xlgmac_init_all_ops(struct xlgmac_pdata *pdata)
0062 {
0063     xlgmac_init_desc_ops(&pdata->desc_ops);
0064     xlgmac_init_hw_ops(&pdata->hw_ops);
0065 }
0066 
0067 static int xlgmac_init(struct xlgmac_pdata *pdata)
0068 {
0069     struct xlgmac_hw_ops *hw_ops = &pdata->hw_ops;
0070     struct net_device *netdev = pdata->netdev;
0071     unsigned int i;
0072     int ret;
0073 
0074     /* Set default configuration data */
0075     xlgmac_default_config(pdata);
0076 
0077     /* Set irq, base_addr, MAC address, */
0078     netdev->irq = pdata->dev_irq;
0079     netdev->base_addr = (unsigned long)pdata->mac_regs;
0080     xlgmac_read_mac_addr(pdata);
0081     eth_hw_addr_set(netdev, pdata->mac_addr);
0082 
0083     /* Set all the function pointers */
0084     xlgmac_init_all_ops(pdata);
0085 
0086     /* Issue software reset to device */
0087     hw_ops->exit(pdata);
0088 
0089     /* Populate the hardware features */
0090     xlgmac_get_all_hw_features(pdata);
0091     xlgmac_print_all_hw_features(pdata);
0092 
0093     /* TODO: Set the PHY mode to XLGMII */
0094 
0095     /* Set the DMA mask */
0096     ret = dma_set_mask_and_coherent(pdata->dev,
0097                     DMA_BIT_MASK(pdata->hw_feat.dma_width));
0098     if (ret) {
0099         dev_err(pdata->dev, "dma_set_mask_and_coherent failed\n");
0100         return ret;
0101     }
0102 
0103     /* Channel and ring params initializtion
0104      *  pdata->channel_count;
0105      *  pdata->tx_ring_count;
0106      *  pdata->rx_ring_count;
0107      *  pdata->tx_desc_count;
0108      *  pdata->rx_desc_count;
0109      */
0110     BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_TX_DESC_CNT);
0111     pdata->tx_desc_count = XLGMAC_TX_DESC_CNT;
0112     if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) {
0113         dev_err(pdata->dev, "tx descriptor count (%d) is not valid\n",
0114             pdata->tx_desc_count);
0115         ret = -EINVAL;
0116         return ret;
0117     }
0118     BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_RX_DESC_CNT);
0119     pdata->rx_desc_count = XLGMAC_RX_DESC_CNT;
0120     if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) {
0121         dev_err(pdata->dev, "rx descriptor count (%d) is not valid\n",
0122             pdata->rx_desc_count);
0123         ret = -EINVAL;
0124         return ret;
0125     }
0126 
0127     pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
0128                      pdata->hw_feat.tx_ch_cnt);
0129     pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
0130                      pdata->hw_feat.tx_q_cnt);
0131     pdata->tx_q_count = pdata->tx_ring_count;
0132     ret = netif_set_real_num_tx_queues(netdev, pdata->tx_q_count);
0133     if (ret) {
0134         dev_err(pdata->dev, "error setting real tx queue count\n");
0135         return ret;
0136     }
0137 
0138     pdata->rx_ring_count = min_t(unsigned int,
0139                      netif_get_num_default_rss_queues(),
0140                      pdata->hw_feat.rx_ch_cnt);
0141     pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
0142                      pdata->hw_feat.rx_q_cnt);
0143     pdata->rx_q_count = pdata->rx_ring_count;
0144     ret = netif_set_real_num_rx_queues(netdev, pdata->rx_q_count);
0145     if (ret) {
0146         dev_err(pdata->dev, "error setting real rx queue count\n");
0147         return ret;
0148     }
0149 
0150     pdata->channel_count =
0151         max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
0152 
0153     /* Initialize RSS hash key and lookup table */
0154     netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));
0155 
0156     for (i = 0; i < XLGMAC_RSS_MAX_TABLE_SIZE; i++)
0157         pdata->rss_table[i] = XLGMAC_SET_REG_BITS(
0158                     pdata->rss_table[i],
0159                     MAC_RSSDR_DMCH_POS,
0160                     MAC_RSSDR_DMCH_LEN,
0161                     i % pdata->rx_ring_count);
0162 
0163     pdata->rss_options = XLGMAC_SET_REG_BITS(
0164                 pdata->rss_options,
0165                 MAC_RSSCR_IP2TE_POS,
0166                 MAC_RSSCR_IP2TE_LEN, 1);
0167     pdata->rss_options = XLGMAC_SET_REG_BITS(
0168                 pdata->rss_options,
0169                 MAC_RSSCR_TCP4TE_POS,
0170                 MAC_RSSCR_TCP4TE_LEN, 1);
0171     pdata->rss_options = XLGMAC_SET_REG_BITS(
0172                 pdata->rss_options,
0173                 MAC_RSSCR_UDP4TE_POS,
0174                 MAC_RSSCR_UDP4TE_LEN, 1);
0175 
0176     /* Set device operations */
0177     netdev->netdev_ops = xlgmac_get_netdev_ops();
0178     netdev->ethtool_ops = xlgmac_get_ethtool_ops();
0179 
0180     /* Set device features */
0181     if (pdata->hw_feat.tso) {
0182         netdev->hw_features = NETIF_F_TSO;
0183         netdev->hw_features |= NETIF_F_TSO6;
0184         netdev->hw_features |= NETIF_F_SG;
0185         netdev->hw_features |= NETIF_F_IP_CSUM;
0186         netdev->hw_features |= NETIF_F_IPV6_CSUM;
0187     } else if (pdata->hw_feat.tx_coe) {
0188         netdev->hw_features = NETIF_F_IP_CSUM;
0189         netdev->hw_features |= NETIF_F_IPV6_CSUM;
0190     }
0191 
0192     if (pdata->hw_feat.rx_coe) {
0193         netdev->hw_features |= NETIF_F_RXCSUM;
0194         netdev->hw_features |= NETIF_F_GRO;
0195     }
0196 
0197     if (pdata->hw_feat.rss)
0198         netdev->hw_features |= NETIF_F_RXHASH;
0199 
0200     netdev->vlan_features |= netdev->hw_features;
0201 
0202     netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
0203     if (pdata->hw_feat.sa_vlan_ins)
0204         netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
0205     if (pdata->hw_feat.vlhash)
0206         netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
0207 
0208     netdev->features |= netdev->hw_features;
0209     pdata->netdev_features = netdev->features;
0210 
0211     netdev->priv_flags |= IFF_UNICAST_FLT;
0212 
0213     /* Use default watchdog timeout */
0214     netdev->watchdog_timeo = 0;
0215 
0216     /* Tx coalesce parameters initialization */
0217     pdata->tx_usecs = XLGMAC_INIT_DMA_TX_USECS;
0218     pdata->tx_frames = XLGMAC_INIT_DMA_TX_FRAMES;
0219 
0220     /* Rx coalesce parameters initialization */
0221     pdata->rx_riwt = hw_ops->usec_to_riwt(pdata, XLGMAC_INIT_DMA_RX_USECS);
0222     pdata->rx_usecs = XLGMAC_INIT_DMA_RX_USECS;
0223     pdata->rx_frames = XLGMAC_INIT_DMA_RX_FRAMES;
0224 
0225     return 0;
0226 }
0227 
0228 int xlgmac_drv_probe(struct device *dev, struct xlgmac_resources *res)
0229 {
0230     struct xlgmac_pdata *pdata;
0231     struct net_device *netdev;
0232     int ret;
0233 
0234     netdev = alloc_etherdev_mq(sizeof(struct xlgmac_pdata),
0235                    XLGMAC_MAX_DMA_CHANNELS);
0236 
0237     if (!netdev) {
0238         dev_err(dev, "alloc_etherdev failed\n");
0239         return -ENOMEM;
0240     }
0241 
0242     SET_NETDEV_DEV(netdev, dev);
0243     dev_set_drvdata(dev, netdev);
0244     pdata = netdev_priv(netdev);
0245     pdata->dev = dev;
0246     pdata->netdev = netdev;
0247 
0248     pdata->dev_irq = res->irq;
0249     pdata->mac_regs = res->addr;
0250 
0251     mutex_init(&pdata->rss_mutex);
0252     pdata->msg_enable = netif_msg_init(debug, default_msg_level);
0253 
0254     ret = xlgmac_init(pdata);
0255     if (ret) {
0256         dev_err(dev, "xlgmac init failed\n");
0257         goto err_free_netdev;
0258     }
0259 
0260     ret = register_netdev(netdev);
0261     if (ret) {
0262         dev_err(dev, "net device registration failed\n");
0263         goto err_free_netdev;
0264     }
0265 
0266     return 0;
0267 
0268 err_free_netdev:
0269     free_netdev(netdev);
0270 
0271     return ret;
0272 }
0273 
0274 int xlgmac_drv_remove(struct device *dev)
0275 {
0276     struct net_device *netdev = dev_get_drvdata(dev);
0277 
0278     unregister_netdev(netdev);
0279     free_netdev(netdev);
0280 
0281     return 0;
0282 }
0283 
0284 void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata,
0285              struct xlgmac_ring *ring,
0286              unsigned int idx,
0287              unsigned int count,
0288              unsigned int flag)
0289 {
0290     struct xlgmac_desc_data *desc_data;
0291     struct xlgmac_dma_desc *dma_desc;
0292 
0293     while (count--) {
0294         desc_data = XLGMAC_GET_DESC_DATA(ring, idx);
0295         dma_desc = desc_data->dma_desc;
0296 
0297         netdev_dbg(pdata->netdev, "TX: dma_desc=%p, dma_desc_addr=%pad\n",
0298                desc_data->dma_desc, &desc_data->dma_desc_addr);
0299         netdev_dbg(pdata->netdev,
0300                "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
0301                (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
0302                le32_to_cpu(dma_desc->desc0),
0303                le32_to_cpu(dma_desc->desc1),
0304                le32_to_cpu(dma_desc->desc2),
0305                le32_to_cpu(dma_desc->desc3));
0306 
0307         idx++;
0308     }
0309 }
0310 
0311 void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata,
0312              struct xlgmac_ring *ring,
0313              unsigned int idx)
0314 {
0315     struct xlgmac_desc_data *desc_data;
0316     struct xlgmac_dma_desc *dma_desc;
0317 
0318     desc_data = XLGMAC_GET_DESC_DATA(ring, idx);
0319     dma_desc = desc_data->dma_desc;
0320 
0321     netdev_dbg(pdata->netdev, "RX: dma_desc=%p, dma_desc_addr=%pad\n",
0322            desc_data->dma_desc, &desc_data->dma_desc_addr);
0323     netdev_dbg(pdata->netdev,
0324            "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
0325            idx,
0326            le32_to_cpu(dma_desc->desc0),
0327            le32_to_cpu(dma_desc->desc1),
0328            le32_to_cpu(dma_desc->desc2),
0329            le32_to_cpu(dma_desc->desc3));
0330 }
0331 
0332 void xlgmac_print_pkt(struct net_device *netdev,
0333               struct sk_buff *skb, bool tx_rx)
0334 {
0335     struct ethhdr *eth = (struct ethhdr *)skb->data;
0336     unsigned char buffer[128];
0337     unsigned int i;
0338 
0339     netdev_dbg(netdev, "\n************** SKB dump ****************\n");
0340 
0341     netdev_dbg(netdev, "%s packet of %d bytes\n",
0342            (tx_rx ? "TX" : "RX"), skb->len);
0343 
0344     netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
0345     netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
0346     netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
0347 
0348     for (i = 0; i < skb->len; i += 32) {
0349         unsigned int len = min(skb->len - i, 32U);
0350 
0351         hex_dump_to_buffer(&skb->data[i], len, 32, 1,
0352                    buffer, sizeof(buffer), false);
0353         netdev_dbg(netdev, "  %#06x: %s\n", i, buffer);
0354     }
0355 
0356     netdev_dbg(netdev, "\n************** SKB dump ****************\n");
0357 }
0358 
0359 void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata)
0360 {
0361     struct xlgmac_hw_features *hw_feat = &pdata->hw_feat;
0362     unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
0363 
0364     mac_hfr0 = readl(pdata->mac_regs + MAC_HWF0R);
0365     mac_hfr1 = readl(pdata->mac_regs + MAC_HWF1R);
0366     mac_hfr2 = readl(pdata->mac_regs + MAC_HWF2R);
0367 
0368     memset(hw_feat, 0, sizeof(*hw_feat));
0369 
0370     hw_feat->version = readl(pdata->mac_regs + MAC_VR);
0371 
0372     /* Hardware feature register 0 */
0373     hw_feat->phyifsel    = XLGMAC_GET_REG_BITS(mac_hfr0,
0374                         MAC_HWF0R_PHYIFSEL_POS,
0375                         MAC_HWF0R_PHYIFSEL_LEN);
0376     hw_feat->vlhash      = XLGMAC_GET_REG_BITS(mac_hfr0,
0377                         MAC_HWF0R_VLHASH_POS,
0378                         MAC_HWF0R_VLHASH_LEN);
0379     hw_feat->sma         = XLGMAC_GET_REG_BITS(mac_hfr0,
0380                         MAC_HWF0R_SMASEL_POS,
0381                         MAC_HWF0R_SMASEL_LEN);
0382     hw_feat->rwk         = XLGMAC_GET_REG_BITS(mac_hfr0,
0383                         MAC_HWF0R_RWKSEL_POS,
0384                         MAC_HWF0R_RWKSEL_LEN);
0385     hw_feat->mgk         = XLGMAC_GET_REG_BITS(mac_hfr0,
0386                         MAC_HWF0R_MGKSEL_POS,
0387                         MAC_HWF0R_MGKSEL_LEN);
0388     hw_feat->mmc         = XLGMAC_GET_REG_BITS(mac_hfr0,
0389                         MAC_HWF0R_MMCSEL_POS,
0390                         MAC_HWF0R_MMCSEL_LEN);
0391     hw_feat->aoe         = XLGMAC_GET_REG_BITS(mac_hfr0,
0392                         MAC_HWF0R_ARPOFFSEL_POS,
0393                         MAC_HWF0R_ARPOFFSEL_LEN);
0394     hw_feat->ts          = XLGMAC_GET_REG_BITS(mac_hfr0,
0395                         MAC_HWF0R_TSSEL_POS,
0396                         MAC_HWF0R_TSSEL_LEN);
0397     hw_feat->eee         = XLGMAC_GET_REG_BITS(mac_hfr0,
0398                         MAC_HWF0R_EEESEL_POS,
0399                         MAC_HWF0R_EEESEL_LEN);
0400     hw_feat->tx_coe      = XLGMAC_GET_REG_BITS(mac_hfr0,
0401                         MAC_HWF0R_TXCOESEL_POS,
0402                         MAC_HWF0R_TXCOESEL_LEN);
0403     hw_feat->rx_coe      = XLGMAC_GET_REG_BITS(mac_hfr0,
0404                         MAC_HWF0R_RXCOESEL_POS,
0405                         MAC_HWF0R_RXCOESEL_LEN);
0406     hw_feat->addn_mac    = XLGMAC_GET_REG_BITS(mac_hfr0,
0407                         MAC_HWF0R_ADDMACADRSEL_POS,
0408                         MAC_HWF0R_ADDMACADRSEL_LEN);
0409     hw_feat->ts_src      = XLGMAC_GET_REG_BITS(mac_hfr0,
0410                         MAC_HWF0R_TSSTSSEL_POS,
0411                         MAC_HWF0R_TSSTSSEL_LEN);
0412     hw_feat->sa_vlan_ins = XLGMAC_GET_REG_BITS(mac_hfr0,
0413                         MAC_HWF0R_SAVLANINS_POS,
0414                         MAC_HWF0R_SAVLANINS_LEN);
0415 
0416     /* Hardware feature register 1 */
0417     hw_feat->rx_fifo_size  = XLGMAC_GET_REG_BITS(mac_hfr1,
0418                         MAC_HWF1R_RXFIFOSIZE_POS,
0419                         MAC_HWF1R_RXFIFOSIZE_LEN);
0420     hw_feat->tx_fifo_size  = XLGMAC_GET_REG_BITS(mac_hfr1,
0421                         MAC_HWF1R_TXFIFOSIZE_POS,
0422                         MAC_HWF1R_TXFIFOSIZE_LEN);
0423     hw_feat->adv_ts_hi     = XLGMAC_GET_REG_BITS(mac_hfr1,
0424                         MAC_HWF1R_ADVTHWORD_POS,
0425                         MAC_HWF1R_ADVTHWORD_LEN);
0426     hw_feat->dma_width     = XLGMAC_GET_REG_BITS(mac_hfr1,
0427                         MAC_HWF1R_ADDR64_POS,
0428                         MAC_HWF1R_ADDR64_LEN);
0429     hw_feat->dcb           = XLGMAC_GET_REG_BITS(mac_hfr1,
0430                         MAC_HWF1R_DCBEN_POS,
0431                         MAC_HWF1R_DCBEN_LEN);
0432     hw_feat->sph           = XLGMAC_GET_REG_BITS(mac_hfr1,
0433                         MAC_HWF1R_SPHEN_POS,
0434                         MAC_HWF1R_SPHEN_LEN);
0435     hw_feat->tso           = XLGMAC_GET_REG_BITS(mac_hfr1,
0436                         MAC_HWF1R_TSOEN_POS,
0437                         MAC_HWF1R_TSOEN_LEN);
0438     hw_feat->dma_debug     = XLGMAC_GET_REG_BITS(mac_hfr1,
0439                         MAC_HWF1R_DBGMEMA_POS,
0440                         MAC_HWF1R_DBGMEMA_LEN);
0441     hw_feat->rss           = XLGMAC_GET_REG_BITS(mac_hfr1,
0442                         MAC_HWF1R_RSSEN_POS,
0443                         MAC_HWF1R_RSSEN_LEN);
0444     hw_feat->tc_cnt        = XLGMAC_GET_REG_BITS(mac_hfr1,
0445                         MAC_HWF1R_NUMTC_POS,
0446                         MAC_HWF1R_NUMTC_LEN);
0447     hw_feat->hash_table_size = XLGMAC_GET_REG_BITS(mac_hfr1,
0448                         MAC_HWF1R_HASHTBLSZ_POS,
0449                         MAC_HWF1R_HASHTBLSZ_LEN);
0450     hw_feat->l3l4_filter_num = XLGMAC_GET_REG_BITS(mac_hfr1,
0451                         MAC_HWF1R_L3L4FNUM_POS,
0452                         MAC_HWF1R_L3L4FNUM_LEN);
0453 
0454     /* Hardware feature register 2 */
0455     hw_feat->rx_q_cnt     = XLGMAC_GET_REG_BITS(mac_hfr2,
0456                         MAC_HWF2R_RXQCNT_POS,
0457                         MAC_HWF2R_RXQCNT_LEN);
0458     hw_feat->tx_q_cnt     = XLGMAC_GET_REG_BITS(mac_hfr2,
0459                         MAC_HWF2R_TXQCNT_POS,
0460                         MAC_HWF2R_TXQCNT_LEN);
0461     hw_feat->rx_ch_cnt    = XLGMAC_GET_REG_BITS(mac_hfr2,
0462                         MAC_HWF2R_RXCHCNT_POS,
0463                         MAC_HWF2R_RXCHCNT_LEN);
0464     hw_feat->tx_ch_cnt    = XLGMAC_GET_REG_BITS(mac_hfr2,
0465                         MAC_HWF2R_TXCHCNT_POS,
0466                         MAC_HWF2R_TXCHCNT_LEN);
0467     hw_feat->pps_out_num  = XLGMAC_GET_REG_BITS(mac_hfr2,
0468                         MAC_HWF2R_PPSOUTNUM_POS,
0469                         MAC_HWF2R_PPSOUTNUM_LEN);
0470     hw_feat->aux_snap_num = XLGMAC_GET_REG_BITS(mac_hfr2,
0471                         MAC_HWF2R_AUXSNAPNUM_POS,
0472                         MAC_HWF2R_AUXSNAPNUM_LEN);
0473 
0474     /* Translate the Hash Table size into actual number */
0475     switch (hw_feat->hash_table_size) {
0476     case 0:
0477         break;
0478     case 1:
0479         hw_feat->hash_table_size = 64;
0480         break;
0481     case 2:
0482         hw_feat->hash_table_size = 128;
0483         break;
0484     case 3:
0485         hw_feat->hash_table_size = 256;
0486         break;
0487     }
0488 
0489     /* Translate the address width setting into actual number */
0490     switch (hw_feat->dma_width) {
0491     case 0:
0492         hw_feat->dma_width = 32;
0493         break;
0494     case 1:
0495         hw_feat->dma_width = 40;
0496         break;
0497     case 2:
0498         hw_feat->dma_width = 48;
0499         break;
0500     default:
0501         hw_feat->dma_width = 32;
0502     }
0503 
0504     /* The Queue, Channel and TC counts are zero based so increment them
0505      * to get the actual number
0506      */
0507     hw_feat->rx_q_cnt++;
0508     hw_feat->tx_q_cnt++;
0509     hw_feat->rx_ch_cnt++;
0510     hw_feat->tx_ch_cnt++;
0511     hw_feat->tc_cnt++;
0512 }
0513 
0514 void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata)
0515 {
0516     char __maybe_unused *str = NULL;
0517 
0518     XLGMAC_PR("\n");
0519     XLGMAC_PR("=====================================================\n");
0520     XLGMAC_PR("\n");
0521     XLGMAC_PR("HW support following features\n");
0522     XLGMAC_PR("\n");
0523     /* HW Feature Register0 */
0524     XLGMAC_PR("VLAN Hash Filter Selected                   : %s\n",
0525           pdata->hw_feat.vlhash ? "YES" : "NO");
0526     XLGMAC_PR("SMA (MDIO) Interface                        : %s\n",
0527           pdata->hw_feat.sma ? "YES" : "NO");
0528     XLGMAC_PR("PMT Remote Wake-up Packet Enable            : %s\n",
0529           pdata->hw_feat.rwk ? "YES" : "NO");
0530     XLGMAC_PR("PMT Magic Packet Enable                     : %s\n",
0531           pdata->hw_feat.mgk ? "YES" : "NO");
0532     XLGMAC_PR("RMON/MMC Module Enable                      : %s\n",
0533           pdata->hw_feat.mmc ? "YES" : "NO");
0534     XLGMAC_PR("ARP Offload Enabled                         : %s\n",
0535           pdata->hw_feat.aoe ? "YES" : "NO");
0536     XLGMAC_PR("IEEE 1588-2008 Timestamp Enabled            : %s\n",
0537           pdata->hw_feat.ts ? "YES" : "NO");
0538     XLGMAC_PR("Energy Efficient Ethernet Enabled           : %s\n",
0539           pdata->hw_feat.eee ? "YES" : "NO");
0540     XLGMAC_PR("Transmit Checksum Offload Enabled           : %s\n",
0541           pdata->hw_feat.tx_coe ? "YES" : "NO");
0542     XLGMAC_PR("Receive Checksum Offload Enabled            : %s\n",
0543           pdata->hw_feat.rx_coe ? "YES" : "NO");
0544     XLGMAC_PR("Additional MAC Addresses 1-31 Selected      : %s\n",
0545           pdata->hw_feat.addn_mac ? "YES" : "NO");
0546 
0547     switch (pdata->hw_feat.ts_src) {
0548     case 0:
0549         str = "RESERVED";
0550         break;
0551     case 1:
0552         str = "INTERNAL";
0553         break;
0554     case 2:
0555         str = "EXTERNAL";
0556         break;
0557     case 3:
0558         str = "BOTH";
0559         break;
0560     }
0561     XLGMAC_PR("Timestamp System Time Source                : %s\n", str);
0562 
0563     XLGMAC_PR("Source Address or VLAN Insertion Enable     : %s\n",
0564           pdata->hw_feat.sa_vlan_ins ? "YES" : "NO");
0565 
0566     /* HW Feature Register1 */
0567     switch (pdata->hw_feat.rx_fifo_size) {
0568     case 0:
0569         str = "128 bytes";
0570         break;
0571     case 1:
0572         str = "256 bytes";
0573         break;
0574     case 2:
0575         str = "512 bytes";
0576         break;
0577     case 3:
0578         str = "1 KBytes";
0579         break;
0580     case 4:
0581         str = "2 KBytes";
0582         break;
0583     case 5:
0584         str = "4 KBytes";
0585         break;
0586     case 6:
0587         str = "8 KBytes";
0588         break;
0589     case 7:
0590         str = "16 KBytes";
0591         break;
0592     case 8:
0593         str = "32 kBytes";
0594         break;
0595     case 9:
0596         str = "64 KBytes";
0597         break;
0598     case 10:
0599         str = "128 KBytes";
0600         break;
0601     case 11:
0602         str = "256 KBytes";
0603         break;
0604     default:
0605         str = "RESERVED";
0606     }
0607     XLGMAC_PR("MTL Receive FIFO Size                       : %s\n", str);
0608 
0609     switch (pdata->hw_feat.tx_fifo_size) {
0610     case 0:
0611         str = "128 bytes";
0612         break;
0613     case 1:
0614         str = "256 bytes";
0615         break;
0616     case 2:
0617         str = "512 bytes";
0618         break;
0619     case 3:
0620         str = "1 KBytes";
0621         break;
0622     case 4:
0623         str = "2 KBytes";
0624         break;
0625     case 5:
0626         str = "4 KBytes";
0627         break;
0628     case 6:
0629         str = "8 KBytes";
0630         break;
0631     case 7:
0632         str = "16 KBytes";
0633         break;
0634     case 8:
0635         str = "32 kBytes";
0636         break;
0637     case 9:
0638         str = "64 KBytes";
0639         break;
0640     case 10:
0641         str = "128 KBytes";
0642         break;
0643     case 11:
0644         str = "256 KBytes";
0645         break;
0646     default:
0647         str = "RESERVED";
0648     }
0649     XLGMAC_PR("MTL Transmit FIFO Size                      : %s\n", str);
0650 
0651     XLGMAC_PR("IEEE 1588 High Word Register Enable         : %s\n",
0652           pdata->hw_feat.adv_ts_hi ? "YES" : "NO");
0653     XLGMAC_PR("Address width                               : %u\n",
0654           pdata->hw_feat.dma_width);
0655     XLGMAC_PR("DCB Feature Enable                          : %s\n",
0656           pdata->hw_feat.dcb ? "YES" : "NO");
0657     XLGMAC_PR("Split Header Feature Enable                 : %s\n",
0658           pdata->hw_feat.sph ? "YES" : "NO");
0659     XLGMAC_PR("TCP Segmentation Offload Enable             : %s\n",
0660           pdata->hw_feat.tso ? "YES" : "NO");
0661     XLGMAC_PR("DMA Debug Registers Enabled                 : %s\n",
0662           pdata->hw_feat.dma_debug ? "YES" : "NO");
0663     XLGMAC_PR("RSS Feature Enabled                         : %s\n",
0664           pdata->hw_feat.rss ? "YES" : "NO");
0665     XLGMAC_PR("Number of Traffic classes                   : %u\n",
0666           (pdata->hw_feat.tc_cnt));
0667     XLGMAC_PR("Hash Table Size                             : %u\n",
0668           pdata->hw_feat.hash_table_size);
0669     XLGMAC_PR("Total number of L3 or L4 Filters            : %u\n",
0670           pdata->hw_feat.l3l4_filter_num);
0671 
0672     /* HW Feature Register2 */
0673     XLGMAC_PR("Number of MTL Receive Queues                : %u\n",
0674           pdata->hw_feat.rx_q_cnt);
0675     XLGMAC_PR("Number of MTL Transmit Queues               : %u\n",
0676           pdata->hw_feat.tx_q_cnt);
0677     XLGMAC_PR("Number of DMA Receive Channels              : %u\n",
0678           pdata->hw_feat.rx_ch_cnt);
0679     XLGMAC_PR("Number of DMA Transmit Channels             : %u\n",
0680           pdata->hw_feat.tx_ch_cnt);
0681 
0682     switch (pdata->hw_feat.pps_out_num) {
0683     case 0:
0684         str = "No PPS output";
0685         break;
0686     case 1:
0687         str = "1 PPS output";
0688         break;
0689     case 2:
0690         str = "2 PPS output";
0691         break;
0692     case 3:
0693         str = "3 PPS output";
0694         break;
0695     case 4:
0696         str = "4 PPS output";
0697         break;
0698     default:
0699         str = "RESERVED";
0700     }
0701     XLGMAC_PR("Number of PPS Outputs                       : %s\n", str);
0702 
0703     switch (pdata->hw_feat.aux_snap_num) {
0704     case 0:
0705         str = "No auxiliary input";
0706         break;
0707     case 1:
0708         str = "1 auxiliary input";
0709         break;
0710     case 2:
0711         str = "2 auxiliary input";
0712         break;
0713     case 3:
0714         str = "3 auxiliary input";
0715         break;
0716     case 4:
0717         str = "4 auxiliary input";
0718         break;
0719     default:
0720         str = "RESERVED";
0721     }
0722     XLGMAC_PR("Number of Auxiliary Snapshot Inputs         : %s", str);
0723 
0724     XLGMAC_PR("\n");
0725     XLGMAC_PR("=====================================================\n");
0726     XLGMAC_PR("\n");
0727 }
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