ethernet/sunplus/spl2sw_define.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright Sunplus Technology Co., Ltd.
0003  *       All rights reserved.
0004  */
0005
0006 #ifndef __SPL2SW_DEFINE_H__
0007 #define __SPL2SW_DEFINE_H__
0008
0009 #define MAX_NETDEV_NUM          2   /* Maximum # of net-device */
0010
0011 /* Interrupt status */
0012 #define MAC_INT_DAISY_MODE_CHG      BIT(31) /* Daisy Mode Change             */
0013 #define MAC_INT_IP_CHKSUM_ERR       BIT(23) /* IP Checksum Append Error      */
0014 #define MAC_INT_WDOG_TIMER1_EXP     BIT(22) /* Watchdog Timer1 Expired       */
0015 #define MAC_INT_WDOG_TIMER0_EXP     BIT(21) /* Watchdog Timer0 Expired       */
0016 #define MAC_INT_INTRUDER_ALERT      BIT(20) /* Atruder Alert                 */
0017 #define MAC_INT_PORT_ST_CHG     BIT(19) /* Port Status Change            */
0018 #define MAC_INT_BC_STORM        BIT(18) /* Broad Cast Storm              */
0019 #define MAC_INT_MUST_DROP_LAN       BIT(17) /* Global Queue Exhausted        */
0020 #define MAC_INT_GLOBAL_QUE_FULL     BIT(16) /* Global Queue Full             */
0021 #define MAC_INT_TX_SOC_PAUSE_ON     BIT(15) /* Soc Port TX Pause On          */
0022 #define MAC_INT_RX_SOC_QUE_FULL     BIT(14) /* Soc Port Out Queue Full       */
0023 #define MAC_INT_TX_LAN1_QUE_FULL    BIT(9)  /* Port 1 Out Queue Full         */
0024 #define MAC_INT_TX_LAN0_QUE_FULL    BIT(8)  /* Port 0 Out Queue Full         */
0025 #define MAC_INT_RX_L_DESCF      BIT(7)  /* Low Priority Descriptor Full  */
0026 #define MAC_INT_RX_H_DESCF      BIT(6)  /* High Priority Descriptor Full */
0027 #define MAC_INT_RX_DONE_L       BIT(5)  /* RX Low Priority Done          */
0028 #define MAC_INT_RX_DONE_H       BIT(4)  /* RX High Priority Done         */
0029 #define MAC_INT_TX_DONE_L       BIT(3)  /* TX Low Priority Done          */
0030 #define MAC_INT_TX_DONE_H       BIT(2)  /* TX High Priority Done         */
0031 #define MAC_INT_TX_DES_ERR      BIT(1)  /* TX Descriptor Error           */
0032 #define MAC_INT_RX_DES_ERR      BIT(0)  /* Rx Descriptor Error           */
0033
0034 #define MAC_INT_RX          (MAC_INT_RX_DONE_H | MAC_INT_RX_DONE_L | \
0035                     MAC_INT_RX_DES_ERR)
0036 #define MAC_INT_TX          (MAC_INT_TX_DONE_L | MAC_INT_TX_DONE_H | \
0037                     MAC_INT_TX_DES_ERR)
0038 #define MAC_INT_MASK_DEF        (MAC_INT_DAISY_MODE_CHG | MAC_INT_IP_CHKSUM_ERR | \
0039                     MAC_INT_WDOG_TIMER1_EXP | MAC_INT_WDOG_TIMER0_EXP | \
0040                     MAC_INT_INTRUDER_ALERT | MAC_INT_PORT_ST_CHG | \
0041                     MAC_INT_BC_STORM | MAC_INT_MUST_DROP_LAN | \
0042                     MAC_INT_GLOBAL_QUE_FULL | MAC_INT_TX_SOC_PAUSE_ON | \
0043                     MAC_INT_RX_SOC_QUE_FULL | MAC_INT_TX_LAN1_QUE_FULL | \
0044                     MAC_INT_TX_LAN0_QUE_FULL | MAC_INT_RX_L_DESCF | \
0045                     MAC_INT_RX_H_DESCF)
0046
0047 /* Address table search */
0048 #define MAC_ADDR_LOOKUP_IDLE        BIT(2)
0049 #define MAC_SEARCH_NEXT_ADDR        BIT(1)
0050 #define MAC_BEGIN_SEARCH_ADDR       BIT(0)
0051
0052 /* Address table status */
0053 #define MAC_HASH_LOOKUP_ADDR        GENMASK(31, 22)
0054 #define MAC_R_PORT_MAP          GENMASK(13, 12)
0055 #define MAC_R_CPU_PORT          GENMASK(11, 10)
0056 #define MAC_R_VID           GENMASK(9, 7)
0057 #define MAC_R_AGE           GENMASK(6, 4)
0058 #define MAC_R_PROXY         BIT(3)
0059 #define MAC_R_MC_INGRESS        BIT(2)
0060 #define MAC_AT_TABLE_END        BIT(1)
0061 #define MAC_AT_DATA_READY       BIT(0)
0062
0063 /* Wt mac ad0 */
0064 #define MAC_W_PORT_MAP          GENMASK(13, 12)
0065 #define MAC_W_LAN_PORT_1        BIT(13)
0066 #define MAC_W_LAN_PORT_0        BIT(12)
0067 #define MAC_W_CPU_PORT          GENMASK(11, 10)
0068 #define MAC_W_CPU_PORT_1        BIT(11)
0069 #define MAC_W_CPU_PORT_0        BIT(10)
0070 #define MAC_W_VID           GENMASK(9, 7)
0071 #define MAC_W_AGE           GENMASK(6, 4)
0072 #define MAC_W_PROXY         BIT(3)
0073 #define MAC_W_MC_INGRESS        BIT(2)
0074 #define MAC_W_MAC_DONE          BIT(1)
0075 #define MAC_W_MAC_CMD           BIT(0)
0076
0077 /* W mac 15_0 bus */
0078 #define MAC_W_MAC_15_0          GENMASK(15, 0)
0079
0080 /* W mac 47_16 bus */
0081 #define MAC_W_MAC_47_16         GENMASK(31, 0)
0082
0083 /* PVID config 0 */
0084 #define MAC_P1_PVID         GENMASK(6, 4)
0085 #define MAC_P0_PVID         GENMASK(2, 0)
0086
0087 /* VLAN member config 0 */
0088 #define MAC_VLAN_MEMSET_3       GENMASK(27, 24)
0089 #define MAC_VLAN_MEMSET_2       GENMASK(19, 16)
0090 #define MAC_VLAN_MEMSET_1       GENMASK(11, 8)
0091 #define MAC_VLAN_MEMSET_0       GENMASK(3, 0)
0092
0093 /* VLAN member config 1 */
0094 #define MAC_VLAN_MEMSET_5       GENMASK(11, 8)
0095 #define MAC_VLAN_MEMSET_4       GENMASK(3, 0)
0096
0097 /* Port ability */
0098 #define MAC_PORT_ABILITY_LINK_ST    GENMASK(25, 24)
0099
0100 /* CPU control */
0101 #define MAC_EN_SOC1_AGING       BIT(15)
0102 #define MAC_EN_SOC0_AGING       BIT(14)
0103 #define MAC_DIS_LRN_SOC1        BIT(13)
0104 #define MAC_DIS_LRN_SOC0        BIT(12)
0105 #define MAC_EN_CRC_SOC1         BIT(9)
0106 #define MAC_EN_CRC_SOC0         BIT(8)
0107 #define MAC_DIS_SOC1_CPU        BIT(7)
0108 #define MAC_DIS_SOC0_CPU        BIT(6)
0109 #define MAC_DIS_BC2CPU_P1       BIT(5)
0110 #define MAC_DIS_BC2CPU_P0       BIT(4)
0111 #define MAC_DIS_MC2CPU          GENMASK(3, 2)
0112 #define MAC_DIS_MC2CPU_P1       BIT(3)
0113 #define MAC_DIS_MC2CPU_P0       BIT(2)
0114 #define MAC_DIS_UN2CPU          GENMASK(1, 0)
0115
0116 /* Port control 0 */
0117 #define MAC_DIS_PORT            GENMASK(25, 24)
0118 #define MAC_DIS_PORT1           BIT(25)
0119 #define MAC_DIS_PORT0           BIT(24)
0120 #define MAC_DIS_RMC2CPU_P1      BIT(17)
0121 #define MAC_DIS_RMC2CPU_P0      BIT(16)
0122 #define MAC_EN_FLOW_CTL_P1      BIT(9)
0123 #define MAC_EN_FLOW_CTL_P0      BIT(8)
0124 #define MAC_EN_BACK_PRESS_P1        BIT(1)
0125 #define MAC_EN_BACK_PRESS_P0        BIT(0)
0126
0127 /* Port control 1 */
0128 #define MAC_DIS_SA_LRN_P1       BIT(9)
0129 #define MAC_DIS_SA_LRN_P0       BIT(8)
0130
0131 /* Port control 2 */
0132 #define MAC_EN_AGING_P1         BIT(9)
0133 #define MAC_EN_AGING_P0         BIT(8)
0134
0135 /* Switch Global control */
0136 #define MAC_RMC_TB_FAULT_RULE       GENMASK(26, 25)
0137 #define MAC_LED_FLASH_TIME      GENMASK(24, 23)
0138 #define MAC_BC_STORM_PREV       GENMASK(5, 4)
0139
0140 /* LED port 0 */
0141 #define MAC_LED_ACT_HI          BIT(28)
0142
0143 /* PHY control register 0  */
0144 #define MAC_CPU_PHY_WT_DATA     GENMASK(31, 16)
0145 #define MAC_CPU_PHY_CMD         GENMASK(14, 13)
0146 #define MAC_CPU_PHY_REG_ADDR        GENMASK(12, 8)
0147 #define MAC_CPU_PHY_ADDR        GENMASK(4, 0)
0148
0149 /* PHY control register 1 */
0150 #define MAC_CPU_PHY_RD_DATA     GENMASK(31, 16)
0151 #define MAC_PHY_RD_RDY          BIT(1)
0152 #define MAC_PHY_WT_DONE         BIT(0)
0153
0154 /* MAC force mode */
0155 #define MAC_EXT_PHY1_ADDR       GENMASK(28, 24)
0156 #define MAC_EXT_PHY0_ADDR       GENMASK(20, 16)
0157 #define MAC_FORCE_RMII_LINK     GENMASK(9, 8)
0158 #define MAC_FORCE_RMII_EN_1     BIT(7)
0159 #define MAC_FORCE_RMII_EN_0     BIT(6)
0160 #define MAC_FORCE_RMII_FC       GENMASK(5, 4)
0161 #define MAC_FORCE_RMII_DPX      GENMASK(3, 2)
0162 #define MAC_FORCE_RMII_SPD      GENMASK(1, 0)
0163
0164 /* CPU transmit trigger */
0165 #define MAC_TRIG_L_SOC0         BIT(1)
0166 #define MAC_TRIG_H_SOC0         BIT(0)
0167
0168 /* Config descriptor queue */
0169 #define TX_DESC_NUM         16  /* # of descriptors in TX queue   */
0170 #define MAC_GUARD_DESC_NUM      2   /* # of descriptors of gap      0 */
0171 #define RX_QUEUE0_DESC_NUM      16  /* # of descriptors in RX queue 0 */
0172 #define RX_QUEUE1_DESC_NUM      16  /* # of descriptors in RX queue 1 */
0173 #define TX_DESC_QUEUE_NUM       1   /* # of TX queue                  */
0174 #define RX_DESC_QUEUE_NUM       2   /* # of RX queue                  */
0175
0176 #define MAC_RX_LEN_MAX          2047    /* Size of RX buffer       */
0177
0178 /* Tx descriptor */
0179 /* cmd1 */
0180 #define TXD_OWN             BIT(31)
0181 #define TXD_ERR_CODE            GENMASK(29, 26)
0182 #define TXD_SOP             BIT(25)     /* start of a packet */
0183 #define TXD_EOP             BIT(24)     /* end of a packet */
0184 #define TXD_VLAN            GENMASK(17, 12)
0185 #define TXD_PKT_LEN         GENMASK(10, 0)  /* packet length */
0186 /* cmd2 */
0187 #define TXD_EOR             BIT(31)     /* end of ring */
0188 #define TXD_BUF_LEN2            GENMASK(22, 12)
0189 #define TXD_BUF_LEN1            GENMASK(10, 0)
0190
0191 /* Rx descriptor */
0192 /* cmd1 */
0193 #define RXD_OWN             BIT(31)
0194 #define RXD_ERR_CODE            GENMASK(29, 26)
0195 #define RXD_TCP_UDP_CHKSUM      BIT(23)
0196 #define RXD_PROXY           BIT(22)
0197 #define RXD_PROTOCOL            GENMASK(21, 20)
0198 #define RXD_VLAN_TAG            BIT(19)
0199 #define RXD_IP_CHKSUM           BIT(18)
0200 #define RXD_ROUTE_TYPE          GENMASK(17, 16)
0201 #define RXD_PKT_SP          GENMASK(14, 12) /* packet source port */
0202 #define RXD_PKT_LEN         GENMASK(10, 0)  /* packet length */
0203 /* cmd2 */
0204 #define RXD_EOR             BIT(31)     /* end of ring */
0205 #define RXD_BUF_LEN2            GENMASK(22, 12)
0206 #define RXD_BUF_LEN1            GENMASK(10, 0)
0207
0208 /* structure of descriptor */
0209 struct spl2sw_mac_desc {
0210     u32 cmd1;
0211     u32 cmd2;
0212     u32 addr1;
0213     u32 addr2;
0214 };
0215
0216 struct spl2sw_skb_info {
0217     struct sk_buff *skb;
0218     u32 mapping;
0219     u32 len;
0220 };
0221
0222 struct spl2sw_common {
0223     void __iomem *l2sw_reg_base;
0224
0225     struct platform_device *pdev;
0226     struct reset_control *rstc;
0227     struct clk *clk;
0228
0229     void *desc_base;
0230     dma_addr_t desc_dma;
0231     s32 desc_size;
0232     struct spl2sw_mac_desc *rx_desc[RX_DESC_QUEUE_NUM];
0233     struct spl2sw_skb_info *rx_skb_info[RX_DESC_QUEUE_NUM];
0234     u32 rx_pos[RX_DESC_QUEUE_NUM];
0235     u32 rx_desc_num[RX_DESC_QUEUE_NUM];
0236     u32 rx_desc_buff_size;
0237
0238     struct spl2sw_mac_desc *tx_desc;
0239     struct spl2sw_skb_info tx_temp_skb_info[TX_DESC_NUM];
0240     u32 tx_done_pos;
0241     u32 tx_pos;
0242     u32 tx_desc_full;
0243
0244     struct net_device *ndev[MAX_NETDEV_NUM];
0245     struct mii_bus *mii_bus;
0246
0247     struct napi_struct rx_napi;
0248     struct napi_struct tx_napi;
0249
0250     spinlock_t tx_lock;     /* spinlock for accessing tx buffer */
0251     spinlock_t mdio_lock;       /* spinlock for mdio commands */
0252     spinlock_t int_mask_lock;   /* spinlock for accessing int mask reg. */
0253
0254     u8 enable;
0255 };
0256
0257 struct spl2sw_mac {
0258     struct net_device *ndev;
0259     struct spl2sw_common *comm;
0260
0261     u8 mac_addr[ETH_ALEN];
0262     phy_interface_t phy_mode;
0263     struct device_node *phy_node;
0264
0265     u8 lan_port;
0266     u8 to_vlan;
0267     u8 vlan_id;
0268 };
0269
0270 #endif