ethernet/sun/sunbmac.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* $Id: sunbmac.h,v 1.7 2000/07/11 22:35:22 davem Exp $
0003  * sunbmac.h: Defines for the Sun "Big MAC" 100baseT ethernet cards.
0004  *
0005  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
0006  */
0007
0008 #ifndef _SUNBMAC_H
0009 #define _SUNBMAC_H
0010
0011 /* QEC global registers. */
0012 #define GLOB_CTRL   0x00UL  /* Control                  */
0013 #define GLOB_STAT   0x04UL  /* Status                   */
0014 #define GLOB_PSIZE  0x08UL  /* Packet Size              */
0015 #define GLOB_MSIZE  0x0cUL  /* Local-mem size (64K)     */
0016 #define GLOB_RSIZE  0x10UL  /* Receive partition size   */
0017 #define GLOB_TSIZE  0x14UL  /* Transmit partition size  */
0018 #define GLOB_REG_SIZE   0x18UL
0019
0020 #define GLOB_CTRL_MMODE       0x40000000 /* MACE qec mode            */
0021 #define GLOB_CTRL_BMODE       0x10000000 /* BigMAC qec mode          */
0022 #define GLOB_CTRL_EPAR        0x00000020 /* Enable parity            */
0023 #define GLOB_CTRL_ACNTRL      0x00000018 /* SBUS arbitration control */
0024 #define GLOB_CTRL_B64         0x00000004 /* 64 byte dvma bursts      */
0025 #define GLOB_CTRL_B32         0x00000002 /* 32 byte dvma bursts      */
0026 #define GLOB_CTRL_B16         0x00000000 /* 16 byte dvma bursts      */
0027 #define GLOB_CTRL_RESET       0x00000001 /* Reset the QEC            */
0028
0029 #define GLOB_STAT_TX          0x00000008 /* BigMAC Transmit IRQ      */
0030 #define GLOB_STAT_RX          0x00000004 /* BigMAC Receive IRQ       */
0031 #define GLOB_STAT_BM          0x00000002 /* BigMAC Global IRQ        */
0032 #define GLOB_STAT_ER          0x00000001 /* BigMAC Error IRQ         */
0033
0034 #define GLOB_PSIZE_2048       0x00       /* 2k packet size           */
0035 #define GLOB_PSIZE_4096       0x01       /* 4k packet size           */
0036 #define GLOB_PSIZE_6144       0x10       /* 6k packet size           */
0037 #define GLOB_PSIZE_8192       0x11       /* 8k packet size           */
0038
0039 /* QEC BigMAC channel registers. */
0040 #define CREG_CTRL   0x00UL  /* Control                   */
0041 #define CREG_STAT   0x04UL  /* Status                    */
0042 #define CREG_RXDS   0x08UL  /* RX descriptor ring ptr    */
0043 #define CREG_TXDS   0x0cUL  /* TX descriptor ring ptr    */
0044 #define CREG_RIMASK 0x10UL  /* RX Interrupt Mask         */
0045 #define CREG_TIMASK 0x14UL  /* TX Interrupt Mask         */
0046 #define CREG_QMASK  0x18UL  /* QEC Error Interrupt Mask  */
0047 #define CREG_BMASK  0x1cUL  /* BigMAC Error Interrupt Mask*/
0048 #define CREG_RXWBUFPTR  0x20UL  /* Local memory rx write ptr */
0049 #define CREG_RXRBUFPTR  0x24UL  /* Local memory rx read ptr  */
0050 #define CREG_TXWBUFPTR  0x28UL  /* Local memory tx write ptr */
0051 #define CREG_TXRBUFPTR  0x2cUL  /* Local memory tx read ptr  */
0052 #define CREG_CCNT   0x30UL  /* Collision Counter         */
0053 #define CREG_REG_SIZE   0x34UL
0054
0055 #define CREG_CTRL_TWAKEUP     0x00000001  /* Transmitter Wakeup, 'go'. */
0056
0057 #define CREG_STAT_BERROR      0x80000000  /* BigMAC error              */
0058 #define CREG_STAT_TXIRQ       0x00200000  /* Transmit Interrupt        */
0059 #define CREG_STAT_TXDERROR    0x00080000  /* TX Descriptor is bogus    */
0060 #define CREG_STAT_TXLERR      0x00040000  /* Late Transmit Error       */
0061 #define CREG_STAT_TXPERR      0x00020000  /* Transmit Parity Error     */
0062 #define CREG_STAT_TXSERR      0x00010000  /* Transmit SBUS error ack   */
0063 #define CREG_STAT_RXIRQ       0x00000020  /* Receive Interrupt         */
0064 #define CREG_STAT_RXDROP      0x00000010  /* Dropped a RX'd packet     */
0065 #define CREG_STAT_RXSMALL     0x00000008  /* Receive buffer too small  */
0066 #define CREG_STAT_RXLERR      0x00000004  /* Receive Late Error        */
0067 #define CREG_STAT_RXPERR      0x00000002  /* Receive Parity Error      */
0068 #define CREG_STAT_RXSERR      0x00000001  /* Receive SBUS Error ACK    */
0069
0070 #define CREG_STAT_ERRORS      (CREG_STAT_BERROR|CREG_STAT_TXDERROR|CREG_STAT_TXLERR|   \
0071                                CREG_STAT_TXPERR|CREG_STAT_TXSERR|CREG_STAT_RXDROP|     \
0072                                CREG_STAT_RXSMALL|CREG_STAT_RXLERR|CREG_STAT_RXPERR|    \
0073                                CREG_STAT_RXSERR)
0074
0075 #define CREG_QMASK_TXDERROR   0x00080000  /* TXD error                 */
0076 #define CREG_QMASK_TXLERR     0x00040000  /* TX late error             */
0077 #define CREG_QMASK_TXPERR     0x00020000  /* TX parity error           */
0078 #define CREG_QMASK_TXSERR     0x00010000  /* TX sbus error ack         */
0079 #define CREG_QMASK_RXDROP     0x00000010  /* RX drop                   */
0080 #define CREG_QMASK_RXBERROR   0x00000008  /* RX buffer error           */
0081 #define CREG_QMASK_RXLEERR    0x00000004  /* RX late error             */
0082 #define CREG_QMASK_RXPERR     0x00000002  /* RX parity error           */
0083 #define CREG_QMASK_RXSERR     0x00000001  /* RX sbus error ack         */
0084
0085 /* BIGMAC core registers */
0086 #define BMAC_XIFCFG 0x000UL /* XIF config register                */
0087     /* 0x004-->0x0fc, reserved */
0088 #define BMAC_STATUS 0x100UL /* Status register, clear on read     */
0089 #define BMAC_IMASK  0x104UL /* Interrupt mask register            */
0090     /* 0x108-->0x204, reserved */
0091 #define BMAC_TXSWRESET  0x208UL /* Transmitter software reset         */
0092 #define BMAC_TXCFG  0x20cUL /* Transmitter config register        */
0093 #define BMAC_IGAP1  0x210UL /* Inter-packet gap 1                 */
0094 #define BMAC_IGAP2  0x214UL /* Inter-packet gap 2                 */
0095 #define BMAC_ALIMIT 0x218UL /* Transmit attempt limit             */
0096 #define BMAC_STIME  0x21cUL /* Transmit slot time                 */
0097 #define BMAC_PLEN   0x220UL /* Size of transmit preamble          */
0098 #define BMAC_PPAT   0x224UL /* Pattern for transmit preamble      */
0099 #define BMAC_TXDELIM    0x228UL /* Transmit delimiter                 */
0100 #define BMAC_JSIZE  0x22cUL /* Toe jam...                         */
0101 #define BMAC_TXPMAX 0x230UL /* Transmit max pkt size              */
0102 #define BMAC_TXPMIN 0x234UL /* Transmit min pkt size              */
0103 #define BMAC_PATTEMPT   0x238UL /* Count of transmit peak attempts    */
0104 #define BMAC_DTCTR  0x23cUL /* Transmit defer timer               */
0105 #define BMAC_NCCTR  0x240UL /* Transmit normal-collision counter  */
0106 #define BMAC_FCCTR  0x244UL /* Transmit first-collision counter   */
0107 #define BMAC_EXCTR  0x248UL /* Transmit excess-collision counter  */
0108 #define BMAC_LTCTR  0x24cUL /* Transmit late-collision counter    */
0109 #define BMAC_RSEED  0x250UL /* Transmit random number seed        */
0110 #define BMAC_TXSMACHINE 0x254UL /* Transmit state machine             */
0111     /* 0x258-->0x304, reserved */
0112 #define BMAC_RXSWRESET  0x308UL /* Receiver software reset            */
0113 #define BMAC_RXCFG  0x30cUL /* Receiver config register           */
0114 #define BMAC_RXPMAX 0x310UL /* Receive max pkt size               */
0115 #define BMAC_RXPMIN 0x314UL /* Receive min pkt size               */
0116 #define BMAC_MACADDR2   0x318UL /* Ether address register 2           */
0117 #define BMAC_MACADDR1   0x31cUL /* Ether address register 1           */
0118 #define BMAC_MACADDR0   0x320UL /* Ether address register 0           */
0119 #define BMAC_FRCTR  0x324UL /* Receive frame receive counter      */
0120 #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
0121 #define BMAC_UNALECTR   0x32cUL /* Receive unaligned error counter    */
0122 #define BMAC_RCRCECTR   0x330UL /* Receive CRC error counter          */
0123 #define BMAC_RXSMACHINE 0x334UL /* Receiver state machine             */
0124 #define BMAC_RXCVALID   0x338UL /* Receiver code violation            */
0125     /* 0x33c, reserved */
0126 #define BMAC_HTABLE3    0x340UL /* Hash table 3                       */
0127 #define BMAC_HTABLE2    0x344UL /* Hash table 2                       */
0128 #define BMAC_HTABLE1    0x348UL /* Hash table 1                       */
0129 #define BMAC_HTABLE0    0x34cUL /* Hash table 0                       */
0130 #define BMAC_AFILTER2   0x350UL /* Address filter 2                   */
0131 #define BMAC_AFILTER1   0x354UL /* Address filter 1                   */
0132 #define BMAC_AFILTER0   0x358UL /* Address filter 0                   */
0133 #define BMAC_AFMASK 0x35cUL /* Address filter mask                */
0134 #define BMAC_REG_SIZE   0x360UL
0135
0136 /* BigMac XIF config register. */
0137 #define BIGMAC_XCFG_ODENABLE   0x00000001 /* Output driver enable                     */
0138 #define BIGMAC_XCFG_RESV       0x00000002 /* Reserved, write always as 1              */
0139 #define BIGMAC_XCFG_MLBACK     0x00000004 /* Loopback-mode MII enable                 */
0140 #define BIGMAC_XCFG_SMODE      0x00000008 /* Enable serial mode                       */
0141
0142 /* BigMAC status register. */
0143 #define BIGMAC_STAT_GOTFRAME   0x00000001 /* Received a frame                         */
0144 #define BIGMAC_STAT_RCNTEXP    0x00000002 /* Receive frame counter expired            */
0145 #define BIGMAC_STAT_ACNTEXP    0x00000004 /* Align-error counter expired              */
0146 #define BIGMAC_STAT_CCNTEXP    0x00000008 /* CRC-error counter expired                */
0147 #define BIGMAC_STAT_LCNTEXP    0x00000010 /* Length-error counter expired             */
0148 #define BIGMAC_STAT_RFIFOVF    0x00000020 /* Receive FIFO overflow                    */
0149 #define BIGMAC_STAT_CVCNTEXP   0x00000040 /* Code-violation counter expired           */
0150 #define BIGMAC_STAT_SENTFRAME  0x00000100 /* Transmitted a frame                      */
0151 #define BIGMAC_STAT_TFIFO_UND  0x00000200 /* Transmit FIFO underrun                   */
0152 #define BIGMAC_STAT_MAXPKTERR  0x00000400 /* Max-packet size error                    */
0153 #define BIGMAC_STAT_NCNTEXP    0x00000800 /* Normal-collision counter expired         */
0154 #define BIGMAC_STAT_ECNTEXP    0x00001000 /* Excess-collision counter expired         */
0155 #define BIGMAC_STAT_LCCNTEXP   0x00002000 /* Late-collision counter expired           */
0156 #define BIGMAC_STAT_FCNTEXP    0x00004000 /* First-collision counter expired          */
0157 #define BIGMAC_STAT_DTIMEXP    0x00008000 /* Defer-timer expired                      */
0158
0159 /* BigMAC interrupt mask register. */
0160 #define BIGMAC_IMASK_GOTFRAME  0x00000001 /* Received a frame                         */
0161 #define BIGMAC_IMASK_RCNTEXP   0x00000002 /* Receive frame counter expired            */
0162 #define BIGMAC_IMASK_ACNTEXP   0x00000004 /* Align-error counter expired              */
0163 #define BIGMAC_IMASK_CCNTEXP   0x00000008 /* CRC-error counter expired                */
0164 #define BIGMAC_IMASK_LCNTEXP   0x00000010 /* Length-error counter expired             */
0165 #define BIGMAC_IMASK_RFIFOVF   0x00000020 /* Receive FIFO overflow                    */
0166 #define BIGMAC_IMASK_CVCNTEXP  0x00000040 /* Code-violation counter expired           */
0167 #define BIGMAC_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame                      */
0168 #define BIGMAC_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun                   */
0169 #define BIGMAC_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error                    */
0170 #define BIGMAC_IMASK_NCNTEXP   0x00000800 /* Normal-collision counter expired         */
0171 #define BIGMAC_IMASK_ECNTEXP   0x00001000 /* Excess-collision counter expired         */
0172 #define BIGMAC_IMASK_LCCNTEXP  0x00002000 /* Late-collision counter expired           */
0173 #define BIGMAC_IMASK_FCNTEXP   0x00004000 /* First-collision counter expired          */
0174 #define BIGMAC_IMASK_DTIMEXP   0x00008000 /* Defer-timer expired                      */
0175
0176 /* BigMac transmit config register. */
0177 #define BIGMAC_TXCFG_ENABLE    0x00000001 /* Enable the transmitter                   */
0178 #define BIGMAC_TXCFG_FIFO      0x00000010 /* Default tx fthresh...                    */
0179 #define BIGMAC_TXCFG_SMODE     0x00000020 /* Enable slow transmit mode                */
0180 #define BIGMAC_TXCFG_CIGN      0x00000040 /* Ignore transmit collisions               */
0181 #define BIGMAC_TXCFG_FCSOFF    0x00000080 /* Do not emit FCS                          */
0182 #define BIGMAC_TXCFG_DBACKOFF  0x00000100 /* Disable backoff                          */
0183 #define BIGMAC_TXCFG_FULLDPLX  0x00000200 /* Enable full-duplex                       */
0184
0185 /* BigMac receive config register. */
0186 #define BIGMAC_RXCFG_ENABLE    0x00000001 /* Enable the receiver                      */
0187 #define BIGMAC_RXCFG_FIFO      0x0000000e /* Default rx fthresh...                    */
0188 #define BIGMAC_RXCFG_PSTRIP    0x00000020 /* Pad byte strip enable                    */
0189 #define BIGMAC_RXCFG_PMISC     0x00000040 /* Enable promiscuous mode                   */
0190 #define BIGMAC_RXCFG_DERR      0x00000080 /* Disable error checking                   */
0191 #define BIGMAC_RXCFG_DCRCS     0x00000100 /* Disable CRC stripping                    */
0192 #define BIGMAC_RXCFG_ME        0x00000200 /* Receive packets addressed to me          */
0193 #define BIGMAC_RXCFG_PGRP      0x00000400 /* Enable promisc group mode                */
0194 #define BIGMAC_RXCFG_HENABLE   0x00000800 /* Enable the hash filter                   */
0195 #define BIGMAC_RXCFG_AENABLE   0x00001000 /* Enable the address filter                */
0196
0197 /* The BigMAC PHY transceiver.  Not nearly as sophisticated as the happy meal
0198  * one.  But it does have the "bit banger", oh baby.
0199  */
0200 #define TCVR_TPAL   0x00UL
0201 #define TCVR_MPAL   0x04UL
0202 #define TCVR_REG_SIZE   0x08UL
0203
0204 /* Frame commands. */
0205 #define FRAME_WRITE           0x50020000
0206 #define FRAME_READ            0x60020000
0207
0208 /* Tranceiver registers. */
0209 #define TCVR_PAL_SERIAL       0x00000001 /* Enable serial mode              */
0210 #define TCVR_PAL_EXTLBACK     0x00000002 /* Enable external loopback        */
0211 #define TCVR_PAL_MSENSE       0x00000004 /* Media sense                     */
0212 #define TCVR_PAL_LTENABLE     0x00000008 /* Link test enable                */
0213 #define TCVR_PAL_LTSTATUS     0x00000010 /* Link test status  (P1 only)     */
0214
0215 /* Management PAL. */
0216 #define MGMT_PAL_DCLOCK       0x00000001 /* Data clock                      */
0217 #define MGMT_PAL_OENAB        0x00000002 /* Output enabler                  */
0218 #define MGMT_PAL_MDIO         0x00000004 /* MDIO Data/attached              */
0219 #define MGMT_PAL_TIMEO        0x00000008 /* Transmit enable timeout error   */
0220 #define MGMT_PAL_EXT_MDIO     MGMT_PAL_MDIO
0221 #define MGMT_PAL_INT_MDIO     MGMT_PAL_TIMEO
0222
0223 /* Here are some PHY addresses. */
0224 #define BIGMAC_PHY_EXTERNAL   0 /* External transceiver */
0225 #define BIGMAC_PHY_INTERNAL   1 /* Internal transceiver */
0226
0227 /* Ring descriptors and such, same as Quad Ethernet. */
0228 struct be_rxd {
0229     u32 rx_flags;
0230     u32 rx_addr;
0231 };
0232
0233 #define RXD_OWN      0x80000000 /* Ownership.      */
0234 #define RXD_UPDATE   0x10000000 /* Being Updated?  */
0235 #define RXD_LENGTH   0x000007ff /* Packet Length.  */
0236
0237 struct be_txd {
0238     u32 tx_flags;
0239     u32 tx_addr;
0240 };
0241
0242 #define TXD_OWN      0x80000000 /* Ownership.      */
0243 #define TXD_SOP      0x40000000 /* Start Of Packet */
0244 #define TXD_EOP      0x20000000 /* End Of Packet   */
0245 #define TXD_UPDATE   0x10000000 /* Being Updated?  */
0246 #define TXD_LENGTH   0x000007ff /* Packet Length.  */
0247
0248 #define TX_RING_MAXSIZE   256
0249 #define RX_RING_MAXSIZE   256
0250
0251 #define TX_RING_SIZE      256
0252 #define RX_RING_SIZE      256
0253
0254 #define NEXT_RX(num)       (((num) + 1) & (RX_RING_SIZE - 1))
0255 #define NEXT_TX(num)       (((num) + 1) & (TX_RING_SIZE - 1))
0256 #define PREV_RX(num)       (((num) - 1) & (RX_RING_SIZE - 1))
0257 #define PREV_TX(num)       (((num) - 1) & (TX_RING_SIZE - 1))
0258
0259 #define TX_BUFFS_AVAIL(bp)                                    \
0260         (((bp)->tx_old <= (bp)->tx_new) ?                     \
0261       (bp)->tx_old + (TX_RING_SIZE - 1) - (bp)->tx_new :  \
0262                 (bp)->tx_old - (bp)->tx_new - 1)
0263
0264
0265 #define RX_COPY_THRESHOLD  256
0266 #define RX_BUF_ALLOC_SIZE  (ETH_FRAME_LEN + (64 * 3))
0267
0268 struct bmac_init_block {
0269     struct be_rxd be_rxd[RX_RING_MAXSIZE];
0270     struct be_txd be_txd[TX_RING_MAXSIZE];
0271 };
0272
0273 #define bib_offset(mem, elem) \
0274 ((__u32)((unsigned long)(&(((struct bmac_init_block *)0)->mem[elem]))))
0275
0276 /* Now software state stuff. */
0277 enum bigmac_transceiver {
0278     external = 0,
0279     internal = 1,
0280     none     = 2,
0281 };
0282
0283 /* Timer state engine. */
0284 enum bigmac_timer_state {
0285     ltrywait = 1,  /* Forcing try of all modes, from fastest to slowest. */
0286     asleep   = 2,  /* Timer inactive.                                    */
0287 };
0288
0289 struct bigmac {
0290     void __iomem    *gregs; /* QEC Global Registers               */
0291     void __iomem    *creg;  /* QEC BigMAC Channel Registers       */
0292     void __iomem    *bregs; /* BigMAC Registers                   */
0293     void __iomem    *tregs; /* BigMAC Transceiver                 */
0294     struct bmac_init_block  *bmac_block;    /* RX and TX descriptors */
0295     dma_addr_t      bblock_dvma;    /* RX and TX descriptors */
0296
0297     spinlock_t      lock;
0298
0299     struct sk_buff      *rx_skbs[RX_RING_SIZE];
0300     struct sk_buff      *tx_skbs[TX_RING_SIZE];
0301
0302     int rx_new, tx_new, rx_old, tx_old;
0303
0304     int board_rev;              /* BigMAC board revision.             */
0305
0306     enum bigmac_transceiver tcvr_type;
0307     unsigned int        bigmac_bursts;
0308     unsigned int        paddr;
0309     unsigned short      sw_bmsr;         /* SW copy of PHY BMSR               */
0310     unsigned short      sw_bmcr;         /* SW copy of PHY BMCR               */
0311     struct timer_list   bigmac_timer;
0312     enum bigmac_timer_state timer_state;
0313     unsigned int        timer_ticks;
0314
0315     struct platform_device  *qec_op;
0316     struct platform_device  *bigmac_op;
0317     struct net_device   *dev;
0318 };
0319
0320 /* We use this to acquire receive skb's that we can DMA directly into. */
0321 #define ALIGNED_RX_SKB_ADDR(addr) \
0322         ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
0323
0324 static inline struct sk_buff *big_mac_alloc_skb(unsigned int length, gfp_t gfp_flags)
0325 {
0326     struct sk_buff *skb;
0327
0328     skb = alloc_skb(length + 64, gfp_flags);
0329     if(skb) {
0330         int offset = ALIGNED_RX_SKB_ADDR(skb->data);
0331
0332         if(offset)
0333             skb_reserve(skb, offset);
0334     }
0335     return skb;
0336 }
0337
0338 #endif /* !(_SUNBMAC_H) */