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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
0003  *
0004  * Copyright (C) 1997, 1998, 1999, 2003, 2008 David S. Miller (davem@davemloft.net)
0005  */
0006 
0007 #include <linux/module.h>
0008 #include <linux/pgtable.h>
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/types.h>
0012 #include <linux/fcntl.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/ioport.h>
0015 #include <linux/in.h>
0016 #include <linux/string.h>
0017 #include <linux/delay.h>
0018 #include <linux/crc32.h>
0019 #include <linux/errno.h>
0020 #include <linux/ethtool.h>
0021 #include <linux/mii.h>
0022 #include <linux/netdevice.h>
0023 #include <linux/etherdevice.h>
0024 #include <linux/skbuff.h>
0025 #include <linux/bitops.h>
0026 #include <linux/dma-mapping.h>
0027 #include <linux/of.h>
0028 #include <linux/of_device.h>
0029 #include <linux/gfp.h>
0030 
0031 #include <asm/auxio.h>
0032 #include <asm/byteorder.h>
0033 #include <asm/dma.h>
0034 #include <asm/idprom.h>
0035 #include <asm/io.h>
0036 #include <asm/openprom.h>
0037 #include <asm/oplib.h>
0038 
0039 #include "sunbmac.h"
0040 
0041 #define DRV_NAME    "sunbmac"
0042 #define DRV_VERSION "2.1"
0043 #define DRV_RELDATE "August 26, 2008"
0044 #define DRV_AUTHOR  "David S. Miller (davem@davemloft.net)"
0045 
0046 static char version[] =
0047     DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
0048 
0049 MODULE_VERSION(DRV_VERSION);
0050 MODULE_AUTHOR(DRV_AUTHOR);
0051 MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver");
0052 MODULE_LICENSE("GPL");
0053 
0054 #undef DEBUG_PROBE
0055 #undef DEBUG_TX
0056 #undef DEBUG_IRQ
0057 
0058 #ifdef DEBUG_PROBE
0059 #define DP(x)  printk x
0060 #else
0061 #define DP(x)
0062 #endif
0063 
0064 #ifdef DEBUG_TX
0065 #define DTX(x)  printk x
0066 #else
0067 #define DTX(x)
0068 #endif
0069 
0070 #ifdef DEBUG_IRQ
0071 #define DIRQ(x)  printk x
0072 #else
0073 #define DIRQ(x)
0074 #endif
0075 
0076 #define DEFAULT_JAMSIZE    4 /* Toe jam */
0077 
0078 #define QEC_RESET_TRIES 200
0079 
0080 static int qec_global_reset(void __iomem *gregs)
0081 {
0082     int tries = QEC_RESET_TRIES;
0083 
0084     sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
0085     while (--tries) {
0086         if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) {
0087             udelay(20);
0088             continue;
0089         }
0090         break;
0091     }
0092     if (tries)
0093         return 0;
0094     printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n");
0095     return -1;
0096 }
0097 
0098 static void qec_init(struct bigmac *bp)
0099 {
0100     struct platform_device *qec_op = bp->qec_op;
0101     void __iomem *gregs = bp->gregs;
0102     u8 bsizes = bp->bigmac_bursts;
0103     u32 regval;
0104 
0105     /* 64byte bursts do not work at the moment, do
0106      * not even try to enable them.  -DaveM
0107      */
0108     if (bsizes & DMA_BURST32)
0109         regval = GLOB_CTRL_B32;
0110     else
0111         regval = GLOB_CTRL_B16;
0112     sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL);
0113     sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE);
0114 
0115     /* All of memsize is given to bigmac. */
0116     sbus_writel(resource_size(&qec_op->resource[1]),
0117             gregs + GLOB_MSIZE);
0118 
0119     /* Half to the transmitter, half to the receiver. */
0120     sbus_writel(resource_size(&qec_op->resource[1]) >> 1,
0121             gregs + GLOB_TSIZE);
0122     sbus_writel(resource_size(&qec_op->resource[1]) >> 1,
0123             gregs + GLOB_RSIZE);
0124 }
0125 
0126 #define TX_RESET_TRIES     32
0127 #define RX_RESET_TRIES     32
0128 
0129 static void bigmac_tx_reset(void __iomem *bregs)
0130 {
0131     int tries = TX_RESET_TRIES;
0132 
0133     sbus_writel(0, bregs + BMAC_TXCFG);
0134 
0135     /* The fifo threshold bit is read-only and does
0136      * not clear.  -DaveM
0137      */
0138     while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
0139            --tries != 0)
0140         udelay(20);
0141 
0142     if (!tries) {
0143         printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n");
0144         printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n",
0145                sbus_readl(bregs + BMAC_TXCFG));
0146     }
0147 }
0148 
0149 static void bigmac_rx_reset(void __iomem *bregs)
0150 {
0151     int tries = RX_RESET_TRIES;
0152 
0153     sbus_writel(0, bregs + BMAC_RXCFG);
0154     while (sbus_readl(bregs + BMAC_RXCFG) && --tries)
0155         udelay(20);
0156 
0157     if (!tries) {
0158         printk(KERN_ERR "BIGMAC: Receiver will not reset.\n");
0159         printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n",
0160                sbus_readl(bregs + BMAC_RXCFG));
0161     }
0162 }
0163 
0164 /* Reset the transmitter and receiver. */
0165 static void bigmac_stop(struct bigmac *bp)
0166 {
0167     bigmac_tx_reset(bp->bregs);
0168     bigmac_rx_reset(bp->bregs);
0169 }
0170 
0171 static void bigmac_get_counters(struct bigmac *bp, void __iomem *bregs)
0172 {
0173     struct net_device_stats *stats = &bp->dev->stats;
0174 
0175     stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR);
0176     sbus_writel(0, bregs + BMAC_RCRCECTR);
0177 
0178     stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR);
0179     sbus_writel(0, bregs + BMAC_UNALECTR);
0180 
0181     stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR);
0182     sbus_writel(0, bregs + BMAC_GLECTR);
0183 
0184     stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR);
0185 
0186     stats->collisions +=
0187         (sbus_readl(bregs + BMAC_EXCTR) +
0188          sbus_readl(bregs + BMAC_LTCTR));
0189     sbus_writel(0, bregs + BMAC_EXCTR);
0190     sbus_writel(0, bregs + BMAC_LTCTR);
0191 }
0192 
0193 static void bigmac_clean_rings(struct bigmac *bp)
0194 {
0195     int i;
0196 
0197     for (i = 0; i < RX_RING_SIZE; i++) {
0198         if (bp->rx_skbs[i] != NULL) {
0199             dev_kfree_skb_any(bp->rx_skbs[i]);
0200             bp->rx_skbs[i] = NULL;
0201         }
0202     }
0203 
0204     for (i = 0; i < TX_RING_SIZE; i++) {
0205         if (bp->tx_skbs[i] != NULL) {
0206             dev_kfree_skb_any(bp->tx_skbs[i]);
0207             bp->tx_skbs[i] = NULL;
0208         }
0209     }
0210 }
0211 
0212 static void bigmac_init_rings(struct bigmac *bp, bool non_blocking)
0213 {
0214     struct bmac_init_block *bb = bp->bmac_block;
0215     int i;
0216     gfp_t gfp_flags = GFP_KERNEL;
0217 
0218     if (non_blocking)
0219         gfp_flags = GFP_ATOMIC;
0220 
0221     bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
0222 
0223     /* Free any skippy bufs left around in the rings. */
0224     bigmac_clean_rings(bp);
0225 
0226     /* Now get new skbufs for the receive ring. */
0227     for (i = 0; i < RX_RING_SIZE; i++) {
0228         struct sk_buff *skb;
0229 
0230         skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
0231         if (!skb)
0232             continue;
0233 
0234         bp->rx_skbs[i] = skb;
0235 
0236         /* Because we reserve afterwards. */
0237         skb_put(skb, ETH_FRAME_LEN);
0238         skb_reserve(skb, 34);
0239 
0240         bb->be_rxd[i].rx_addr =
0241             dma_map_single(&bp->bigmac_op->dev,
0242                        skb->data,
0243                        RX_BUF_ALLOC_SIZE - 34,
0244                        DMA_FROM_DEVICE);
0245         bb->be_rxd[i].rx_flags =
0246             (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
0247     }
0248 
0249     for (i = 0; i < TX_RING_SIZE; i++)
0250         bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
0251 }
0252 
0253 #define MGMT_CLKON  (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
0254 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
0255 
0256 static void idle_transceiver(void __iomem *tregs)
0257 {
0258     int i = 20;
0259 
0260     while (i--) {
0261         sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL);
0262         sbus_readl(tregs + TCVR_MPAL);
0263         sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL);
0264         sbus_readl(tregs + TCVR_MPAL);
0265     }
0266 }
0267 
0268 static void write_tcvr_bit(struct bigmac *bp, void __iomem *tregs, int bit)
0269 {
0270     if (bp->tcvr_type == internal) {
0271         bit = (bit & 1) << 3;
0272         sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO),
0273                 tregs + TCVR_MPAL);
0274         sbus_readl(tregs + TCVR_MPAL);
0275         sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
0276                 tregs + TCVR_MPAL);
0277         sbus_readl(tregs + TCVR_MPAL);
0278     } else if (bp->tcvr_type == external) {
0279         bit = (bit & 1) << 2;
0280         sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB,
0281                 tregs + TCVR_MPAL);
0282         sbus_readl(tregs + TCVR_MPAL);
0283         sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK,
0284                 tregs + TCVR_MPAL);
0285         sbus_readl(tregs + TCVR_MPAL);
0286     } else {
0287         printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n");
0288     }
0289 }
0290 
0291 static int read_tcvr_bit(struct bigmac *bp, void __iomem *tregs)
0292 {
0293     int retval = 0;
0294 
0295     if (bp->tcvr_type == internal) {
0296         sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
0297         sbus_readl(tregs + TCVR_MPAL);
0298         sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
0299                 tregs + TCVR_MPAL);
0300         sbus_readl(tregs + TCVR_MPAL);
0301         retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
0302     } else if (bp->tcvr_type == external) {
0303         sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
0304         sbus_readl(tregs + TCVR_MPAL);
0305         sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
0306         sbus_readl(tregs + TCVR_MPAL);
0307         retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
0308     } else {
0309         printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n");
0310     }
0311     return retval;
0312 }
0313 
0314 static int read_tcvr_bit2(struct bigmac *bp, void __iomem *tregs)
0315 {
0316     int retval = 0;
0317 
0318     if (bp->tcvr_type == internal) {
0319         sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
0320         sbus_readl(tregs + TCVR_MPAL);
0321         retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
0322         sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
0323         sbus_readl(tregs + TCVR_MPAL);
0324     } else if (bp->tcvr_type == external) {
0325         sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
0326         sbus_readl(tregs + TCVR_MPAL);
0327         retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
0328         sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
0329         sbus_readl(tregs + TCVR_MPAL);
0330     } else {
0331         printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n");
0332     }
0333     return retval;
0334 }
0335 
0336 static void put_tcvr_byte(struct bigmac *bp,
0337               void __iomem *tregs,
0338               unsigned int byte)
0339 {
0340     int shift = 4;
0341 
0342     do {
0343         write_tcvr_bit(bp, tregs, ((byte >> shift) & 1));
0344         shift -= 1;
0345     } while (shift >= 0);
0346 }
0347 
0348 static void bigmac_tcvr_write(struct bigmac *bp, void __iomem *tregs,
0349                   int reg, unsigned short val)
0350 {
0351     int shift;
0352 
0353     reg &= 0xff;
0354     val &= 0xffff;
0355     switch(bp->tcvr_type) {
0356     case internal:
0357     case external:
0358         break;
0359 
0360     default:
0361         printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
0362         return;
0363     }
0364 
0365     idle_transceiver(tregs);
0366     write_tcvr_bit(bp, tregs, 0);
0367     write_tcvr_bit(bp, tregs, 1);
0368     write_tcvr_bit(bp, tregs, 0);
0369     write_tcvr_bit(bp, tregs, 1);
0370 
0371     put_tcvr_byte(bp, tregs,
0372               ((bp->tcvr_type == internal) ?
0373                BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
0374 
0375     put_tcvr_byte(bp, tregs, reg);
0376 
0377     write_tcvr_bit(bp, tregs, 1);
0378     write_tcvr_bit(bp, tregs, 0);
0379 
0380     shift = 15;
0381     do {
0382         write_tcvr_bit(bp, tregs, (val >> shift) & 1);
0383         shift -= 1;
0384     } while (shift >= 0);
0385 }
0386 
0387 static unsigned short bigmac_tcvr_read(struct bigmac *bp,
0388                        void __iomem *tregs,
0389                        int reg)
0390 {
0391     unsigned short retval = 0;
0392 
0393     reg &= 0xff;
0394     switch(bp->tcvr_type) {
0395     case internal:
0396     case external:
0397         break;
0398 
0399     default:
0400         printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
0401         return 0xffff;
0402     }
0403 
0404     idle_transceiver(tregs);
0405     write_tcvr_bit(bp, tregs, 0);
0406     write_tcvr_bit(bp, tregs, 1);
0407     write_tcvr_bit(bp, tregs, 1);
0408     write_tcvr_bit(bp, tregs, 0);
0409 
0410     put_tcvr_byte(bp, tregs,
0411               ((bp->tcvr_type == internal) ?
0412                BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
0413 
0414     put_tcvr_byte(bp, tregs, reg);
0415 
0416     if (bp->tcvr_type == external) {
0417         int shift = 15;
0418 
0419         (void) read_tcvr_bit2(bp, tregs);
0420         (void) read_tcvr_bit2(bp, tregs);
0421 
0422         do {
0423             int tmp;
0424 
0425             tmp = read_tcvr_bit2(bp, tregs);
0426             retval |= ((tmp & 1) << shift);
0427             shift -= 1;
0428         } while (shift >= 0);
0429 
0430         (void) read_tcvr_bit2(bp, tregs);
0431         (void) read_tcvr_bit2(bp, tregs);
0432         (void) read_tcvr_bit2(bp, tregs);
0433     } else {
0434         int shift = 15;
0435 
0436         (void) read_tcvr_bit(bp, tregs);
0437         (void) read_tcvr_bit(bp, tregs);
0438 
0439         do {
0440             int tmp;
0441 
0442             tmp = read_tcvr_bit(bp, tregs);
0443             retval |= ((tmp & 1) << shift);
0444             shift -= 1;
0445         } while (shift >= 0);
0446 
0447         (void) read_tcvr_bit(bp, tregs);
0448         (void) read_tcvr_bit(bp, tregs);
0449         (void) read_tcvr_bit(bp, tregs);
0450     }
0451     return retval;
0452 }
0453 
0454 static void bigmac_tcvr_init(struct bigmac *bp)
0455 {
0456     void __iomem *tregs = bp->tregs;
0457     u32 mpal;
0458 
0459     idle_transceiver(tregs);
0460     sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
0461             tregs + TCVR_MPAL);
0462     sbus_readl(tregs + TCVR_MPAL);
0463 
0464     /* Only the bit for the present transceiver (internal or
0465      * external) will stick, set them both and see what stays.
0466      */
0467     sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
0468     sbus_readl(tregs + TCVR_MPAL);
0469     udelay(20);
0470 
0471     mpal = sbus_readl(tregs + TCVR_MPAL);
0472     if (mpal & MGMT_PAL_EXT_MDIO) {
0473         bp->tcvr_type = external;
0474         sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
0475                 tregs + TCVR_TPAL);
0476         sbus_readl(tregs + TCVR_TPAL);
0477     } else if (mpal & MGMT_PAL_INT_MDIO) {
0478         bp->tcvr_type = internal;
0479         sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK |
0480                   TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
0481                 tregs + TCVR_TPAL);
0482         sbus_readl(tregs + TCVR_TPAL);
0483     } else {
0484         printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor "
0485                "external MDIO available!\n");
0486         printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
0487                sbus_readl(tregs + TCVR_MPAL),
0488                sbus_readl(tregs + TCVR_TPAL));
0489     }
0490 }
0491 
0492 static int bigmac_init_hw(struct bigmac *, bool);
0493 
0494 static int try_next_permutation(struct bigmac *bp, void __iomem *tregs)
0495 {
0496     if (bp->sw_bmcr & BMCR_SPEED100) {
0497         int timeout;
0498 
0499         /* Reset the PHY. */
0500         bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
0501         bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
0502         bp->sw_bmcr = (BMCR_RESET);
0503         bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
0504 
0505         timeout = 64;
0506         while (--timeout) {
0507             bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
0508             if ((bp->sw_bmcr & BMCR_RESET) == 0)
0509                 break;
0510             udelay(20);
0511         }
0512         if (timeout == 0)
0513             printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
0514 
0515         bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
0516 
0517         /* Now we try 10baseT. */
0518         bp->sw_bmcr &= ~(BMCR_SPEED100);
0519         bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
0520         return 0;
0521     }
0522 
0523     /* We've tried them all. */
0524     return -1;
0525 }
0526 
0527 static void bigmac_timer(struct timer_list *t)
0528 {
0529     struct bigmac *bp = from_timer(bp, t, bigmac_timer);
0530     void __iomem *tregs = bp->tregs;
0531     int restart_timer = 0;
0532 
0533     bp->timer_ticks++;
0534     if (bp->timer_state == ltrywait) {
0535         bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, MII_BMSR);
0536         bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
0537         if (bp->sw_bmsr & BMSR_LSTATUS) {
0538             printk(KERN_INFO "%s: Link is now up at %s.\n",
0539                    bp->dev->name,
0540                    (bp->sw_bmcr & BMCR_SPEED100) ?
0541                    "100baseT" : "10baseT");
0542             bp->timer_state = asleep;
0543             restart_timer = 0;
0544         } else {
0545             if (bp->timer_ticks >= 4) {
0546                 int ret;
0547 
0548                 ret = try_next_permutation(bp, tregs);
0549                 if (ret == -1) {
0550                     printk(KERN_ERR "%s: Link down, cable problem?\n",
0551                            bp->dev->name);
0552                     ret = bigmac_init_hw(bp, true);
0553                     if (ret) {
0554                         printk(KERN_ERR "%s: Error, cannot re-init the "
0555                                "BigMAC.\n", bp->dev->name);
0556                     }
0557                     return;
0558                 }
0559                 bp->timer_ticks = 0;
0560                 restart_timer = 1;
0561             } else {
0562                 restart_timer = 1;
0563             }
0564         }
0565     } else {
0566         /* Can't happens.... */
0567         printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
0568                bp->dev->name);
0569         restart_timer = 0;
0570         bp->timer_ticks = 0;
0571         bp->timer_state = asleep; /* foo on you */
0572     }
0573 
0574     if (restart_timer != 0) {
0575         bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
0576         add_timer(&bp->bigmac_timer);
0577     }
0578 }
0579 
0580 /* Well, really we just force the chip into 100baseT then
0581  * 10baseT, each time checking for a link status.
0582  */
0583 static void bigmac_begin_auto_negotiation(struct bigmac *bp)
0584 {
0585     void __iomem *tregs = bp->tregs;
0586     int timeout;
0587 
0588     /* Grab new software copies of PHY registers. */
0589     bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, MII_BMSR);
0590     bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
0591 
0592     /* Reset the PHY. */
0593     bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
0594     bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
0595     bp->sw_bmcr = (BMCR_RESET);
0596     bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
0597 
0598     timeout = 64;
0599     while (--timeout) {
0600         bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
0601         if ((bp->sw_bmcr & BMCR_RESET) == 0)
0602             break;
0603         udelay(20);
0604     }
0605     if (timeout == 0)
0606         printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
0607 
0608     bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR);
0609 
0610     /* First we try 100baseT. */
0611     bp->sw_bmcr |= BMCR_SPEED100;
0612     bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr);
0613 
0614     bp->timer_state = ltrywait;
0615     bp->timer_ticks = 0;
0616     bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10;
0617     add_timer(&bp->bigmac_timer);
0618 }
0619 
0620 static int bigmac_init_hw(struct bigmac *bp, bool non_blocking)
0621 {
0622     void __iomem *gregs        = bp->gregs;
0623     void __iomem *cregs        = bp->creg;
0624     void __iomem *bregs        = bp->bregs;
0625     __u32 bblk_dvma = (__u32)bp->bblock_dvma;
0626     const unsigned char *e = &bp->dev->dev_addr[0];
0627 
0628     /* Latch current counters into statistics. */
0629     bigmac_get_counters(bp, bregs);
0630 
0631     /* Reset QEC. */
0632     qec_global_reset(gregs);
0633 
0634     /* Init QEC. */
0635     qec_init(bp);
0636 
0637     /* Alloc and reset the tx/rx descriptor chains. */
0638     bigmac_init_rings(bp, non_blocking);
0639 
0640     /* Initialize the PHY. */
0641     bigmac_tcvr_init(bp);
0642 
0643     /* Stop transmitter and receiver. */
0644     bigmac_stop(bp);
0645 
0646     /* Set hardware ethernet address. */
0647     sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2);
0648     sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1);
0649     sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0);
0650 
0651     /* Clear the hash table until mc upload occurs. */
0652     sbus_writel(0, bregs + BMAC_HTABLE3);
0653     sbus_writel(0, bregs + BMAC_HTABLE2);
0654     sbus_writel(0, bregs + BMAC_HTABLE1);
0655     sbus_writel(0, bregs + BMAC_HTABLE0);
0656 
0657     /* Enable Big Mac hash table filter. */
0658     sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO,
0659             bregs + BMAC_RXCFG);
0660     udelay(20);
0661 
0662     /* Ok, configure the Big Mac transmitter. */
0663     sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG);
0664 
0665     /* The HME docs recommend to use the 10LSB of our MAC here. */
0666     sbus_writel(((e[5] | e[4] << 8) & 0x3ff),
0667             bregs + BMAC_RSEED);
0668 
0669     /* Enable the output drivers no matter what. */
0670     sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV,
0671             bregs + BMAC_XIFCFG);
0672 
0673     /* Tell the QEC where the ring descriptors are. */
0674     sbus_writel(bblk_dvma + bib_offset(be_rxd, 0),
0675             cregs + CREG_RXDS);
0676     sbus_writel(bblk_dvma + bib_offset(be_txd, 0),
0677             cregs + CREG_TXDS);
0678 
0679     /* Setup the FIFO pointers into QEC local memory. */
0680     sbus_writel(0, cregs + CREG_RXRBUFPTR);
0681     sbus_writel(0, cregs + CREG_RXWBUFPTR);
0682     sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
0683             cregs + CREG_TXRBUFPTR);
0684     sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
0685             cregs + CREG_TXWBUFPTR);
0686 
0687     /* Tell bigmac what interrupts we don't want to hear about. */
0688     sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME,
0689             bregs + BMAC_IMASK);
0690 
0691     /* Enable the various other irq's. */
0692     sbus_writel(0, cregs + CREG_RIMASK);
0693     sbus_writel(0, cregs + CREG_TIMASK);
0694     sbus_writel(0, cregs + CREG_QMASK);
0695     sbus_writel(0, cregs + CREG_BMASK);
0696 
0697     /* Set jam size to a reasonable default. */
0698     sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE);
0699 
0700     /* Clear collision counter. */
0701     sbus_writel(0, cregs + CREG_CCNT);
0702 
0703     /* Enable transmitter and receiver. */
0704     sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE,
0705             bregs + BMAC_TXCFG);
0706     sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE,
0707             bregs + BMAC_RXCFG);
0708 
0709     /* Ok, start detecting link speed/duplex. */
0710     bigmac_begin_auto_negotiation(bp);
0711 
0712     /* Success. */
0713     return 0;
0714 }
0715 
0716 /* Error interrupts get sent here. */
0717 static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status)
0718 {
0719     printk(KERN_ERR "bigmac_is_medium_rare: ");
0720     if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) {
0721         if (qec_status & GLOB_STAT_ER)
0722             printk("QEC_ERROR, ");
0723         if (qec_status & GLOB_STAT_BM)
0724             printk("QEC_BMAC_ERROR, ");
0725     }
0726     if (bmac_status & CREG_STAT_ERRORS) {
0727         if (bmac_status & CREG_STAT_BERROR)
0728             printk("BMAC_ERROR, ");
0729         if (bmac_status & CREG_STAT_TXDERROR)
0730             printk("TXD_ERROR, ");
0731         if (bmac_status & CREG_STAT_TXLERR)
0732             printk("TX_LATE_ERROR, ");
0733         if (bmac_status & CREG_STAT_TXPERR)
0734             printk("TX_PARITY_ERROR, ");
0735         if (bmac_status & CREG_STAT_TXSERR)
0736             printk("TX_SBUS_ERROR, ");
0737 
0738         if (bmac_status & CREG_STAT_RXDROP)
0739             printk("RX_DROP_ERROR, ");
0740 
0741         if (bmac_status & CREG_STAT_RXSMALL)
0742             printk("RX_SMALL_ERROR, ");
0743         if (bmac_status & CREG_STAT_RXLERR)
0744             printk("RX_LATE_ERROR, ");
0745         if (bmac_status & CREG_STAT_RXPERR)
0746             printk("RX_PARITY_ERROR, ");
0747         if (bmac_status & CREG_STAT_RXSERR)
0748             printk("RX_SBUS_ERROR, ");
0749     }
0750 
0751     printk(" RESET\n");
0752     bigmac_init_hw(bp, true);
0753 }
0754 
0755 /* BigMAC transmit complete service routines. */
0756 static void bigmac_tx(struct bigmac *bp)
0757 {
0758     struct be_txd *txbase = &bp->bmac_block->be_txd[0];
0759     struct net_device *dev = bp->dev;
0760     int elem;
0761 
0762     spin_lock(&bp->lock);
0763 
0764     elem = bp->tx_old;
0765     DTX(("bigmac_tx: tx_old[%d] ", elem));
0766     while (elem != bp->tx_new) {
0767         struct sk_buff *skb;
0768         struct be_txd *this = &txbase[elem];
0769 
0770         DTX(("this(%p) [flags(%08x)addr(%08x)]",
0771              this, this->tx_flags, this->tx_addr));
0772 
0773         if (this->tx_flags & TXD_OWN)
0774             break;
0775         skb = bp->tx_skbs[elem];
0776         dev->stats.tx_packets++;
0777         dev->stats.tx_bytes += skb->len;
0778         dma_unmap_single(&bp->bigmac_op->dev,
0779                  this->tx_addr, skb->len,
0780                  DMA_TO_DEVICE);
0781 
0782         DTX(("skb(%p) ", skb));
0783         bp->tx_skbs[elem] = NULL;
0784         dev_consume_skb_irq(skb);
0785 
0786         elem = NEXT_TX(elem);
0787     }
0788     DTX((" DONE, tx_old=%d\n", elem));
0789     bp->tx_old = elem;
0790 
0791     if (netif_queue_stopped(dev) &&
0792         TX_BUFFS_AVAIL(bp) > 0)
0793         netif_wake_queue(bp->dev);
0794 
0795     spin_unlock(&bp->lock);
0796 }
0797 
0798 /* BigMAC receive complete service routines. */
0799 static void bigmac_rx(struct bigmac *bp)
0800 {
0801     struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
0802     struct be_rxd *this;
0803     int elem = bp->rx_new, drops = 0;
0804     u32 flags;
0805 
0806     this = &rxbase[elem];
0807     while (!((flags = this->rx_flags) & RXD_OWN)) {
0808         struct sk_buff *skb;
0809         int len = (flags & RXD_LENGTH); /* FCS not included */
0810 
0811         /* Check for errors. */
0812         if (len < ETH_ZLEN) {
0813             bp->dev->stats.rx_errors++;
0814             bp->dev->stats.rx_length_errors++;
0815 
0816     drop_it:
0817             /* Return it to the BigMAC. */
0818             bp->dev->stats.rx_dropped++;
0819             this->rx_flags =
0820                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
0821             goto next;
0822         }
0823         skb = bp->rx_skbs[elem];
0824         if (len > RX_COPY_THRESHOLD) {
0825             struct sk_buff *new_skb;
0826 
0827             /* Now refill the entry, if we can. */
0828             new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
0829             if (new_skb == NULL) {
0830                 drops++;
0831                 goto drop_it;
0832             }
0833             dma_unmap_single(&bp->bigmac_op->dev,
0834                      this->rx_addr,
0835                      RX_BUF_ALLOC_SIZE - 34,
0836                      DMA_FROM_DEVICE);
0837             bp->rx_skbs[elem] = new_skb;
0838             skb_put(new_skb, ETH_FRAME_LEN);
0839             skb_reserve(new_skb, 34);
0840             this->rx_addr =
0841                 dma_map_single(&bp->bigmac_op->dev,
0842                            new_skb->data,
0843                            RX_BUF_ALLOC_SIZE - 34,
0844                            DMA_FROM_DEVICE);
0845             this->rx_flags =
0846                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
0847 
0848             /* Trim the original skb for the netif. */
0849             skb_trim(skb, len);
0850         } else {
0851             struct sk_buff *copy_skb = netdev_alloc_skb(bp->dev, len + 2);
0852 
0853             if (copy_skb == NULL) {
0854                 drops++;
0855                 goto drop_it;
0856             }
0857             skb_reserve(copy_skb, 2);
0858             skb_put(copy_skb, len);
0859             dma_sync_single_for_cpu(&bp->bigmac_op->dev,
0860                         this->rx_addr, len,
0861                         DMA_FROM_DEVICE);
0862             skb_copy_to_linear_data(copy_skb, (unsigned char *)skb->data, len);
0863             dma_sync_single_for_device(&bp->bigmac_op->dev,
0864                            this->rx_addr, len,
0865                            DMA_FROM_DEVICE);
0866 
0867             /* Reuse original ring buffer. */
0868             this->rx_flags =
0869                 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
0870 
0871             skb = copy_skb;
0872         }
0873 
0874         /* No checksums done by the BigMAC ;-( */
0875         skb->protocol = eth_type_trans(skb, bp->dev);
0876         netif_rx(skb);
0877         bp->dev->stats.rx_packets++;
0878         bp->dev->stats.rx_bytes += len;
0879     next:
0880         elem = NEXT_RX(elem);
0881         this = &rxbase[elem];
0882     }
0883     bp->rx_new = elem;
0884     if (drops)
0885         printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name);
0886 }
0887 
0888 static irqreturn_t bigmac_interrupt(int irq, void *dev_id)
0889 {
0890     struct bigmac *bp = (struct bigmac *) dev_id;
0891     u32 qec_status, bmac_status;
0892 
0893     DIRQ(("bigmac_interrupt: "));
0894 
0895     /* Latch status registers now. */
0896     bmac_status = sbus_readl(bp->creg + CREG_STAT);
0897     qec_status = sbus_readl(bp->gregs + GLOB_STAT);
0898 
0899     DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status));
0900     if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) ||
0901        (bmac_status & CREG_STAT_ERRORS))
0902         bigmac_is_medium_rare(bp, qec_status, bmac_status);
0903 
0904     if (bmac_status & CREG_STAT_TXIRQ)
0905         bigmac_tx(bp);
0906 
0907     if (bmac_status & CREG_STAT_RXIRQ)
0908         bigmac_rx(bp);
0909 
0910     return IRQ_HANDLED;
0911 }
0912 
0913 static int bigmac_open(struct net_device *dev)
0914 {
0915     struct bigmac *bp = netdev_priv(dev);
0916     int ret;
0917 
0918     ret = request_irq(dev->irq, bigmac_interrupt, IRQF_SHARED, dev->name, bp);
0919     if (ret) {
0920         printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq);
0921         return ret;
0922     }
0923     timer_setup(&bp->bigmac_timer, bigmac_timer, 0);
0924     ret = bigmac_init_hw(bp, false);
0925     if (ret)
0926         free_irq(dev->irq, bp);
0927     return ret;
0928 }
0929 
0930 static int bigmac_close(struct net_device *dev)
0931 {
0932     struct bigmac *bp = netdev_priv(dev);
0933 
0934     del_timer(&bp->bigmac_timer);
0935     bp->timer_state = asleep;
0936     bp->timer_ticks = 0;
0937 
0938     bigmac_stop(bp);
0939     bigmac_clean_rings(bp);
0940     free_irq(dev->irq, bp);
0941     return 0;
0942 }
0943 
0944 static void bigmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
0945 {
0946     struct bigmac *bp = netdev_priv(dev);
0947 
0948     bigmac_init_hw(bp, true);
0949     netif_wake_queue(dev);
0950 }
0951 
0952 /* Put a packet on the wire. */
0953 static netdev_tx_t
0954 bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
0955 {
0956     struct bigmac *bp = netdev_priv(dev);
0957     int len, entry;
0958     u32 mapping;
0959 
0960     len = skb->len;
0961     mapping = dma_map_single(&bp->bigmac_op->dev, skb->data,
0962                  len, DMA_TO_DEVICE);
0963 
0964     /* Avoid a race... */
0965     spin_lock_irq(&bp->lock);
0966     entry = bp->tx_new;
0967     DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry));
0968     bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
0969     bp->tx_skbs[entry] = skb;
0970     bp->bmac_block->be_txd[entry].tx_addr = mapping;
0971     bp->bmac_block->be_txd[entry].tx_flags =
0972         (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
0973     bp->tx_new = NEXT_TX(entry);
0974     if (TX_BUFFS_AVAIL(bp) <= 0)
0975         netif_stop_queue(dev);
0976     spin_unlock_irq(&bp->lock);
0977 
0978     /* Get it going. */
0979     sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL);
0980 
0981 
0982     return NETDEV_TX_OK;
0983 }
0984 
0985 static struct net_device_stats *bigmac_get_stats(struct net_device *dev)
0986 {
0987     struct bigmac *bp = netdev_priv(dev);
0988 
0989     bigmac_get_counters(bp, bp->bregs);
0990     return &dev->stats;
0991 }
0992 
0993 static void bigmac_set_multicast(struct net_device *dev)
0994 {
0995     struct bigmac *bp = netdev_priv(dev);
0996     void __iomem *bregs = bp->bregs;
0997     struct netdev_hw_addr *ha;
0998     u32 tmp, crc;
0999 
1000     /* Disable the receiver.  The bit self-clears when
1001      * the operation is complete.
1002      */
1003     tmp = sbus_readl(bregs + BMAC_RXCFG);
1004     tmp &= ~(BIGMAC_RXCFG_ENABLE);
1005     sbus_writel(tmp, bregs + BMAC_RXCFG);
1006     while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0)
1007         udelay(20);
1008 
1009     if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) {
1010         sbus_writel(0xffff, bregs + BMAC_HTABLE0);
1011         sbus_writel(0xffff, bregs + BMAC_HTABLE1);
1012         sbus_writel(0xffff, bregs + BMAC_HTABLE2);
1013         sbus_writel(0xffff, bregs + BMAC_HTABLE3);
1014     } else if (dev->flags & IFF_PROMISC) {
1015         tmp = sbus_readl(bregs + BMAC_RXCFG);
1016         tmp |= BIGMAC_RXCFG_PMISC;
1017         sbus_writel(tmp, bregs + BMAC_RXCFG);
1018     } else {
1019         u16 hash_table[4] = { 0 };
1020 
1021         netdev_for_each_mc_addr(ha, dev) {
1022             crc = ether_crc_le(6, ha->addr);
1023             crc >>= 26;
1024             hash_table[crc >> 4] |= 1 << (crc & 0xf);
1025         }
1026         sbus_writel(hash_table[0], bregs + BMAC_HTABLE0);
1027         sbus_writel(hash_table[1], bregs + BMAC_HTABLE1);
1028         sbus_writel(hash_table[2], bregs + BMAC_HTABLE2);
1029         sbus_writel(hash_table[3], bregs + BMAC_HTABLE3);
1030     }
1031 
1032     /* Re-enable the receiver. */
1033     tmp = sbus_readl(bregs + BMAC_RXCFG);
1034     tmp |= BIGMAC_RXCFG_ENABLE;
1035     sbus_writel(tmp, bregs + BMAC_RXCFG);
1036 }
1037 
1038 /* Ethtool support... */
1039 static void bigmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1040 {
1041     strlcpy(info->driver, "sunbmac", sizeof(info->driver));
1042     strlcpy(info->version, "2.0", sizeof(info->version));
1043 }
1044 
1045 static u32 bigmac_get_link(struct net_device *dev)
1046 {
1047     struct bigmac *bp = netdev_priv(dev);
1048 
1049     spin_lock_irq(&bp->lock);
1050     bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, MII_BMSR);
1051     spin_unlock_irq(&bp->lock);
1052 
1053     return (bp->sw_bmsr & BMSR_LSTATUS);
1054 }
1055 
1056 static const struct ethtool_ops bigmac_ethtool_ops = {
1057     .get_drvinfo        = bigmac_get_drvinfo,
1058     .get_link       = bigmac_get_link,
1059 };
1060 
1061 static const struct net_device_ops bigmac_ops = {
1062     .ndo_open       = bigmac_open,
1063     .ndo_stop       = bigmac_close,
1064     .ndo_start_xmit     = bigmac_start_xmit,
1065     .ndo_get_stats      = bigmac_get_stats,
1066     .ndo_set_rx_mode    = bigmac_set_multicast,
1067     .ndo_tx_timeout     = bigmac_tx_timeout,
1068     .ndo_set_mac_address    = eth_mac_addr,
1069     .ndo_validate_addr  = eth_validate_addr,
1070 };
1071 
1072 static int bigmac_ether_init(struct platform_device *op,
1073                  struct platform_device *qec_op)
1074 {
1075     static int version_printed;
1076     struct net_device *dev;
1077     u8 bsizes, bsizes_more;
1078     struct bigmac *bp;
1079 
1080     /* Get a new device struct for this interface. */
1081     dev = alloc_etherdev(sizeof(struct bigmac));
1082     if (!dev)
1083         return -ENOMEM;
1084 
1085     if (version_printed++ == 0)
1086         printk(KERN_INFO "%s", version);
1087 
1088     eth_hw_addr_set(dev, idprom->id_ethaddr);
1089 
1090     /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
1091     bp = netdev_priv(dev);
1092     bp->qec_op = qec_op;
1093     bp->bigmac_op = op;
1094 
1095     SET_NETDEV_DEV(dev, &op->dev);
1096 
1097     spin_lock_init(&bp->lock);
1098 
1099     /* Map in QEC global control registers. */
1100     bp->gregs = of_ioremap(&qec_op->resource[0], 0,
1101                    GLOB_REG_SIZE, "BigMAC QEC GLobal Regs");
1102     if (!bp->gregs) {
1103         printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n");
1104         goto fail_and_cleanup;
1105     }
1106 
1107     /* Make sure QEC is in BigMAC mode. */
1108     if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) {
1109         printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
1110         goto fail_and_cleanup;
1111     }
1112 
1113     /* Reset the QEC. */
1114     if (qec_global_reset(bp->gregs))
1115         goto fail_and_cleanup;
1116 
1117     /* Get supported SBUS burst sizes. */
1118     bsizes = of_getintprop_default(qec_op->dev.of_node, "burst-sizes", 0xff);
1119     bsizes_more = of_getintprop_default(qec_op->dev.of_node, "burst-sizes", 0xff);
1120 
1121     bsizes &= 0xff;
1122     if (bsizes_more != 0xff)
1123         bsizes &= bsizes_more;
1124     if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
1125         (bsizes & DMA_BURST32) == 0)
1126         bsizes = (DMA_BURST32 - 1);
1127     bp->bigmac_bursts = bsizes;
1128 
1129     /* Perform QEC initialization. */
1130     qec_init(bp);
1131 
1132     /* Map in the BigMAC channel registers. */
1133     bp->creg = of_ioremap(&op->resource[0], 0,
1134                   CREG_REG_SIZE, "BigMAC QEC Channel Regs");
1135     if (!bp->creg) {
1136         printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n");
1137         goto fail_and_cleanup;
1138     }
1139 
1140     /* Map in the BigMAC control registers. */
1141     bp->bregs = of_ioremap(&op->resource[1], 0,
1142                    BMAC_REG_SIZE, "BigMAC Primary Regs");
1143     if (!bp->bregs) {
1144         printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n");
1145         goto fail_and_cleanup;
1146     }
1147 
1148     /* Map in the BigMAC transceiver registers, this is how you poke at
1149      * the BigMAC's PHY.
1150      */
1151     bp->tregs = of_ioremap(&op->resource[2], 0,
1152                    TCVR_REG_SIZE, "BigMAC Transceiver Regs");
1153     if (!bp->tregs) {
1154         printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n");
1155         goto fail_and_cleanup;
1156     }
1157 
1158     /* Stop the BigMAC. */
1159     bigmac_stop(bp);
1160 
1161     /* Allocate transmit/receive descriptor DVMA block. */
1162     bp->bmac_block = dma_alloc_coherent(&bp->bigmac_op->dev,
1163                         PAGE_SIZE,
1164                         &bp->bblock_dvma, GFP_ATOMIC);
1165     if (bp->bmac_block == NULL || bp->bblock_dvma == 0)
1166         goto fail_and_cleanup;
1167 
1168     /* Get the board revision of this BigMAC. */
1169     bp->board_rev = of_getintprop_default(bp->bigmac_op->dev.of_node,
1170                           "board-version", 1);
1171 
1172     /* Init auto-negotiation timer state. */
1173     timer_setup(&bp->bigmac_timer, bigmac_timer, 0);
1174     bp->timer_state = asleep;
1175     bp->timer_ticks = 0;
1176 
1177     /* Backlink to generic net device struct. */
1178     bp->dev = dev;
1179 
1180     /* Set links to our BigMAC open and close routines. */
1181     dev->ethtool_ops = &bigmac_ethtool_ops;
1182     dev->netdev_ops = &bigmac_ops;
1183     dev->watchdog_timeo = 5*HZ;
1184 
1185     /* Finish net device registration. */
1186     dev->irq = bp->bigmac_op->archdata.irqs[0];
1187     dev->dma = 0;
1188 
1189     if (register_netdev(dev)) {
1190         printk(KERN_ERR "BIGMAC: Cannot register device.\n");
1191         goto fail_and_cleanup;
1192     }
1193 
1194     dev_set_drvdata(&bp->bigmac_op->dev, bp);
1195 
1196     printk(KERN_INFO "%s: BigMAC 100baseT Ethernet %pM\n",
1197            dev->name, dev->dev_addr);
1198 
1199     return 0;
1200 
1201 fail_and_cleanup:
1202     /* Something went wrong, undo whatever we did so far. */
1203     /* Free register mappings if any. */
1204     if (bp->gregs)
1205         of_iounmap(&qec_op->resource[0], bp->gregs, GLOB_REG_SIZE);
1206     if (bp->creg)
1207         of_iounmap(&op->resource[0], bp->creg, CREG_REG_SIZE);
1208     if (bp->bregs)
1209         of_iounmap(&op->resource[1], bp->bregs, BMAC_REG_SIZE);
1210     if (bp->tregs)
1211         of_iounmap(&op->resource[2], bp->tregs, TCVR_REG_SIZE);
1212 
1213     if (bp->bmac_block)
1214         dma_free_coherent(&bp->bigmac_op->dev,
1215                   PAGE_SIZE,
1216                   bp->bmac_block,
1217                   bp->bblock_dvma);
1218 
1219     /* This also frees the co-located private data */
1220     free_netdev(dev);
1221     return -ENODEV;
1222 }
1223 
1224 /* QEC can be the parent of either QuadEthernet or a BigMAC.  We want
1225  * the latter.
1226  */
1227 static int bigmac_sbus_probe(struct platform_device *op)
1228 {
1229     struct device *parent = op->dev.parent;
1230     struct platform_device *qec_op;
1231 
1232     qec_op = to_platform_device(parent);
1233 
1234     return bigmac_ether_init(op, qec_op);
1235 }
1236 
1237 static int bigmac_sbus_remove(struct platform_device *op)
1238 {
1239     struct bigmac *bp = platform_get_drvdata(op);
1240     struct device *parent = op->dev.parent;
1241     struct net_device *net_dev = bp->dev;
1242     struct platform_device *qec_op;
1243 
1244     qec_op = to_platform_device(parent);
1245 
1246     unregister_netdev(net_dev);
1247 
1248     of_iounmap(&qec_op->resource[0], bp->gregs, GLOB_REG_SIZE);
1249     of_iounmap(&op->resource[0], bp->creg, CREG_REG_SIZE);
1250     of_iounmap(&op->resource[1], bp->bregs, BMAC_REG_SIZE);
1251     of_iounmap(&op->resource[2], bp->tregs, TCVR_REG_SIZE);
1252     dma_free_coherent(&op->dev,
1253               PAGE_SIZE,
1254               bp->bmac_block,
1255               bp->bblock_dvma);
1256 
1257     free_netdev(net_dev);
1258 
1259     return 0;
1260 }
1261 
1262 static const struct of_device_id bigmac_sbus_match[] = {
1263     {
1264         .name = "be",
1265     },
1266     {},
1267 };
1268 
1269 MODULE_DEVICE_TABLE(of, bigmac_sbus_match);
1270 
1271 static struct platform_driver bigmac_sbus_driver = {
1272     .driver = {
1273         .name = "sunbmac",
1274         .of_match_table = bigmac_sbus_match,
1275     },
1276     .probe      = bigmac_sbus_probe,
1277     .remove     = bigmac_sbus_remove,
1278 };
1279 
1280 module_platform_driver(bigmac_sbus_driver);
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