stmicro/stmmac/stmmac_ptp.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /******************************************************************************
0003   PTP Header file
0004
0005   Copyright (C) 2013  Vayavya Labs Pvt Ltd
0006
0007
0008   Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
0009 ******************************************************************************/
0010
0011 #ifndef __STMMAC_PTP_H__
0012 #define __STMMAC_PTP_H__
0013
0014 #define PTP_XGMAC_OFFSET    0xd00
0015 #define PTP_GMAC4_OFFSET    0xb00
0016 #define PTP_GMAC3_X_OFFSET  0x700
0017
0018 /* IEEE 1588 PTP register offsets */
0019 #define PTP_TCR     0x00    /* Timestamp Control Reg */
0020 #define PTP_SSIR    0x04    /* Sub-Second Increment Reg */
0021 #define PTP_STSR    0x08    /* System Time – Seconds Regr */
0022 #define PTP_STNSR   0x0c    /* System Time – Nanoseconds Reg */
0023 #define PTP_STSUR   0x10    /* System Time – Seconds Update Reg */
0024 #define PTP_STNSUR  0x14    /* System Time – Nanoseconds Update Reg */
0025 #define PTP_TAR     0x18    /* Timestamp Addend Reg */
0026 #define PTP_ACR     0x40    /* Auxiliary Control Reg */
0027 #define PTP_ATNR    0x48    /* Auxiliary Timestamp - Nanoseconds Reg */
0028 #define PTP_ATSR    0x4c    /* Auxiliary Timestamp - Seconds Reg */
0029
0030 #define PTP_STNSUR_ADDSUB_SHIFT 31
0031 #define PTP_DIGITAL_ROLLOVER_MODE   0x3B9ACA00  /* 10e9-1 ns */
0032 #define PTP_BINARY_ROLLOVER_MODE    0x80000000  /* ~0.466 ns */
0033
0034 /* PTP Timestamp control register defines */
0035 #define PTP_TCR_TSENA       BIT(0)  /* Timestamp Enable */
0036 #define PTP_TCR_TSCFUPDT    BIT(1)  /* Timestamp Fine/Coarse Update */
0037 #define PTP_TCR_TSINIT      BIT(2)  /* Timestamp Initialize */
0038 #define PTP_TCR_TSUPDT      BIT(3)  /* Timestamp Update */
0039 #define PTP_TCR_TSTRIG      BIT(4)  /* Timestamp Interrupt Trigger Enable */
0040 #define PTP_TCR_TSADDREG    BIT(5)  /* Addend Reg Update */
0041 #define PTP_TCR_TSENALL     BIT(8)  /* Enable Timestamp for All Frames */
0042 #define PTP_TCR_TSCTRLSSR   BIT(9)  /* Digital or Binary Rollover Control */
0043 /* Enable PTP packet Processing for Version 2 Format */
0044 #define PTP_TCR_TSVER2ENA   BIT(10)
0045 /* Enable Processing of PTP over Ethernet Frames */
0046 #define PTP_TCR_TSIPENA     BIT(11)
0047 /* Enable Processing of PTP Frames Sent over IPv6-UDP */
0048 #define PTP_TCR_TSIPV6ENA   BIT(12)
0049 /* Enable Processing of PTP Frames Sent over IPv4-UDP */
0050 #define PTP_TCR_TSIPV4ENA   BIT(13)
0051 /* Enable Timestamp Snapshot for Event Messages */
0052 #define PTP_TCR_TSEVNTENA   BIT(14)
0053 /* Enable Snapshot for Messages Relevant to Master */
0054 #define PTP_TCR_TSMSTRENA   BIT(15)
0055 /* Select PTP packets for Taking Snapshots
0056  * On gmac4 specifically:
0057  * Enable SYNC, Pdelay_Req, Pdelay_Resp when TSEVNTENA is enabled.
0058  * or
0059  * Enable  SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp,
0060  * Pdelay_Resp_Follow_Up if TSEVNTENA is disabled
0061  */
0062 #define PTP_TCR_SNAPTYPSEL_1    BIT(16)
0063 /* Enable MAC address for PTP Frame Filtering */
0064 #define PTP_TCR_TSENMACADDR BIT(18)
0065
0066 /* SSIR defines */
0067 #define PTP_SSIR_SSINC_MASK     0xff
0068 #define GMAC4_PTP_SSIR_SSINC_SHIFT  16
0069
0070 /* Auxiliary Control defines */
0071 #define PTP_ACR_ATSFC       BIT(0)  /* Auxiliary Snapshot FIFO Clear */
0072 #define PTP_ACR_ATSEN0      BIT(4)  /* Auxiliary Snapshot 0 Enable */
0073 #define PTP_ACR_ATSEN1      BIT(5)  /* Auxiliary Snapshot 1 Enable */
0074 #define PTP_ACR_ATSEN2      BIT(6)  /* Auxiliary Snapshot 2 Enable */
0075 #define PTP_ACR_ATSEN3      BIT(7)  /* Auxiliary Snapshot 3 Enable */
0076 #define PTP_ACR_ATSEN_SHIFT 5   /* Auxiliary Snapshot shift */
0077 #define PTP_ACR_MASK        GENMASK(7, 4)   /* Aux Snapshot Mask */
0078 #define PMC_ART_VALUE0      0x01    /* PMC_ART[15:0] timer value */
0079 #define PMC_ART_VALUE1      0x02    /* PMC_ART[31:16] timer value */
0080 #define PMC_ART_VALUE2      0x03    /* PMC_ART[47:32] timer value */
0081 #define PMC_ART_VALUE3      0x04    /* PMC_ART[63:48] timer value */
0082 #define GMAC4_ART_TIME_SHIFT    16  /* ART TIME 16-bits shift */
0083
0084 enum aux_snapshot {
0085     AUX_SNAPSHOT0 = 0x10,
0086     AUX_SNAPSHOT1 = 0x20,
0087     AUX_SNAPSHOT2 = 0x40,
0088     AUX_SNAPSHOT3 = 0x80,
0089 };
0090
0091 #endif  /* __STMMAC_PTP_H__ */