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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*******************************************************************************
0003   STMMAC Ethernet Driver -- MDIO bus implementation
0004   Provides Bus interface for MII registers
0005 
0006   Copyright (C) 2007-2009  STMicroelectronics Ltd
0007 
0008 
0009   Author: Carl Shaw <carl.shaw@st.com>
0010   Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0011 *******************************************************************************/
0012 
0013 #include <linux/gpio/consumer.h>
0014 #include <linux/io.h>
0015 #include <linux/iopoll.h>
0016 #include <linux/mii.h>
0017 #include <linux/of_mdio.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/phy.h>
0020 #include <linux/property.h>
0021 #include <linux/slab.h>
0022 
0023 #include "dwxgmac2.h"
0024 #include "stmmac.h"
0025 
0026 #define MII_BUSY 0x00000001
0027 #define MII_WRITE 0x00000002
0028 #define MII_DATA_MASK GENMASK(15, 0)
0029 
0030 /* GMAC4 defines */
0031 #define MII_GMAC4_GOC_SHIFT     2
0032 #define MII_GMAC4_REG_ADDR_SHIFT    16
0033 #define MII_GMAC4_WRITE         (1 << MII_GMAC4_GOC_SHIFT)
0034 #define MII_GMAC4_READ          (3 << MII_GMAC4_GOC_SHIFT)
0035 #define MII_GMAC4_C45E          BIT(1)
0036 
0037 /* XGMAC defines */
0038 #define MII_XGMAC_SADDR         BIT(18)
0039 #define MII_XGMAC_CMD_SHIFT     16
0040 #define MII_XGMAC_WRITE         (1 << MII_XGMAC_CMD_SHIFT)
0041 #define MII_XGMAC_READ          (3 << MII_XGMAC_CMD_SHIFT)
0042 #define MII_XGMAC_BUSY          BIT(22)
0043 #define MII_XGMAC_MAX_C22ADDR       3
0044 #define MII_XGMAC_C22P_MASK     GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
0045 #define MII_XGMAC_PA_SHIFT      16
0046 #define MII_XGMAC_DA_SHIFT      21
0047 
0048 static int stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr,
0049                     int phyreg, u32 *hw_addr)
0050 {
0051     u32 tmp;
0052 
0053     /* Set port as Clause 45 */
0054     tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
0055     tmp &= ~BIT(phyaddr);
0056     writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
0057 
0058     *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff);
0059     *hw_addr |= (phyreg >> MII_DEVADDR_C45_SHIFT) << MII_XGMAC_DA_SHIFT;
0060     return 0;
0061 }
0062 
0063 static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,
0064                     int phyreg, u32 *hw_addr)
0065 {
0066     u32 tmp;
0067 
0068     /* HW does not support C22 addr >= 4 */
0069     if (phyaddr > MII_XGMAC_MAX_C22ADDR)
0070         return -ENODEV;
0071 
0072     /* Set port as Clause 22 */
0073     tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
0074     tmp &= ~MII_XGMAC_C22P_MASK;
0075     tmp |= BIT(phyaddr);
0076     writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
0077 
0078     *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f);
0079     return 0;
0080 }
0081 
0082 static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
0083 {
0084     struct net_device *ndev = bus->priv;
0085     struct stmmac_priv *priv = netdev_priv(ndev);
0086     unsigned int mii_address = priv->hw->mii.addr;
0087     unsigned int mii_data = priv->hw->mii.data;
0088     u32 tmp, addr, value = MII_XGMAC_BUSY;
0089     int ret;
0090 
0091     ret = pm_runtime_resume_and_get(priv->device);
0092     if (ret < 0)
0093         return ret;
0094 
0095     /* Wait until any existing MII operation is complete */
0096     if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
0097                    !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
0098         ret = -EBUSY;
0099         goto err_disable_clks;
0100     }
0101 
0102     if (phyreg & MII_ADDR_C45) {
0103         phyreg &= ~MII_ADDR_C45;
0104 
0105         ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr);
0106         if (ret)
0107             goto err_disable_clks;
0108     } else {
0109         ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
0110         if (ret)
0111             goto err_disable_clks;
0112 
0113         value |= MII_XGMAC_SADDR;
0114     }
0115 
0116     value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
0117         & priv->hw->mii.clk_csr_mask;
0118     value |= MII_XGMAC_READ;
0119 
0120     /* Wait until any existing MII operation is complete */
0121     if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
0122                    !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
0123         ret = -EBUSY;
0124         goto err_disable_clks;
0125     }
0126 
0127     /* Set the MII address register to read */
0128     writel(addr, priv->ioaddr + mii_address);
0129     writel(value, priv->ioaddr + mii_data);
0130 
0131     /* Wait until any existing MII operation is complete */
0132     if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
0133                    !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
0134         ret = -EBUSY;
0135         goto err_disable_clks;
0136     }
0137 
0138     /* Read the data from the MII data register */
0139     ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
0140 
0141 err_disable_clks:
0142     pm_runtime_put(priv->device);
0143 
0144     return ret;
0145 }
0146 
0147 static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr,
0148                     int phyreg, u16 phydata)
0149 {
0150     struct net_device *ndev = bus->priv;
0151     struct stmmac_priv *priv = netdev_priv(ndev);
0152     unsigned int mii_address = priv->hw->mii.addr;
0153     unsigned int mii_data = priv->hw->mii.data;
0154     u32 addr, tmp, value = MII_XGMAC_BUSY;
0155     int ret;
0156 
0157     ret = pm_runtime_resume_and_get(priv->device);
0158     if (ret < 0)
0159         return ret;
0160 
0161     /* Wait until any existing MII operation is complete */
0162     if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
0163                    !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
0164         ret = -EBUSY;
0165         goto err_disable_clks;
0166     }
0167 
0168     if (phyreg & MII_ADDR_C45) {
0169         phyreg &= ~MII_ADDR_C45;
0170 
0171         ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr);
0172         if (ret)
0173             goto err_disable_clks;
0174     } else {
0175         ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
0176         if (ret)
0177             goto err_disable_clks;
0178 
0179         value |= MII_XGMAC_SADDR;
0180     }
0181 
0182     value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
0183         & priv->hw->mii.clk_csr_mask;
0184     value |= phydata;
0185     value |= MII_XGMAC_WRITE;
0186 
0187     /* Wait until any existing MII operation is complete */
0188     if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
0189                    !(tmp & MII_XGMAC_BUSY), 100, 10000)) {
0190         ret = -EBUSY;
0191         goto err_disable_clks;
0192     }
0193 
0194     /* Set the MII address register to write */
0195     writel(addr, priv->ioaddr + mii_address);
0196     writel(value, priv->ioaddr + mii_data);
0197 
0198     /* Wait until any existing MII operation is complete */
0199     ret = readl_poll_timeout(priv->ioaddr + mii_data, tmp,
0200                  !(tmp & MII_XGMAC_BUSY), 100, 10000);
0201 
0202 err_disable_clks:
0203     pm_runtime_put(priv->device);
0204 
0205     return ret;
0206 }
0207 
0208 /**
0209  * stmmac_mdio_read
0210  * @bus: points to the mii_bus structure
0211  * @phyaddr: MII addr
0212  * @phyreg: MII reg
0213  * Description: it reads data from the MII register from within the phy device.
0214  * For the 7111 GMAC, we must set the bit 0 in the MII address register while
0215  * accessing the PHY registers.
0216  * Fortunately, it seems this has no drawback for the 7109 MAC.
0217  */
0218 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
0219 {
0220     struct net_device *ndev = bus->priv;
0221     struct stmmac_priv *priv = netdev_priv(ndev);
0222     unsigned int mii_address = priv->hw->mii.addr;
0223     unsigned int mii_data = priv->hw->mii.data;
0224     u32 value = MII_BUSY;
0225     int data = 0;
0226     u32 v;
0227 
0228     data = pm_runtime_resume_and_get(priv->device);
0229     if (data < 0)
0230         return data;
0231 
0232     value |= (phyaddr << priv->hw->mii.addr_shift)
0233         & priv->hw->mii.addr_mask;
0234     value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
0235     value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
0236         & priv->hw->mii.clk_csr_mask;
0237     if (priv->plat->has_gmac4) {
0238         value |= MII_GMAC4_READ;
0239         if (phyreg & MII_ADDR_C45) {
0240             value |= MII_GMAC4_C45E;
0241             value &= ~priv->hw->mii.reg_mask;
0242             value |= ((phyreg >> MII_DEVADDR_C45_SHIFT) <<
0243                    priv->hw->mii.reg_shift) &
0244                    priv->hw->mii.reg_mask;
0245 
0246             data |= (phyreg & MII_REGADDR_C45_MASK) <<
0247                 MII_GMAC4_REG_ADDR_SHIFT;
0248         }
0249     }
0250 
0251     if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
0252                    100, 10000)) {
0253         data = -EBUSY;
0254         goto err_disable_clks;
0255     }
0256 
0257     writel(data, priv->ioaddr + mii_data);
0258     writel(value, priv->ioaddr + mii_address);
0259 
0260     if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
0261                    100, 10000)) {
0262         data = -EBUSY;
0263         goto err_disable_clks;
0264     }
0265 
0266     /* Read the data from the MII data register */
0267     data = (int)readl(priv->ioaddr + mii_data) & MII_DATA_MASK;
0268 
0269 err_disable_clks:
0270     pm_runtime_put(priv->device);
0271 
0272     return data;
0273 }
0274 
0275 /**
0276  * stmmac_mdio_write
0277  * @bus: points to the mii_bus structure
0278  * @phyaddr: MII addr
0279  * @phyreg: MII reg
0280  * @phydata: phy data
0281  * Description: it writes the data into the MII register from within the device.
0282  */
0283 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
0284                  u16 phydata)
0285 {
0286     struct net_device *ndev = bus->priv;
0287     struct stmmac_priv *priv = netdev_priv(ndev);
0288     unsigned int mii_address = priv->hw->mii.addr;
0289     unsigned int mii_data = priv->hw->mii.data;
0290     int ret, data = phydata;
0291     u32 value = MII_BUSY;
0292     u32 v;
0293 
0294     ret = pm_runtime_resume_and_get(priv->device);
0295     if (ret < 0)
0296         return ret;
0297 
0298     value |= (phyaddr << priv->hw->mii.addr_shift)
0299         & priv->hw->mii.addr_mask;
0300     value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
0301 
0302     value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
0303         & priv->hw->mii.clk_csr_mask;
0304     if (priv->plat->has_gmac4) {
0305         value |= MII_GMAC4_WRITE;
0306         if (phyreg & MII_ADDR_C45) {
0307             value |= MII_GMAC4_C45E;
0308             value &= ~priv->hw->mii.reg_mask;
0309             value |= ((phyreg >> MII_DEVADDR_C45_SHIFT) <<
0310                    priv->hw->mii.reg_shift) &
0311                    priv->hw->mii.reg_mask;
0312 
0313             data |= (phyreg & MII_REGADDR_C45_MASK) <<
0314                 MII_GMAC4_REG_ADDR_SHIFT;
0315         }
0316     } else {
0317         value |= MII_WRITE;
0318     }
0319 
0320     /* Wait until any existing MII operation is complete */
0321     if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
0322                    100, 10000)) {
0323         ret = -EBUSY;
0324         goto err_disable_clks;
0325     }
0326 
0327     /* Set the MII address register to write */
0328     writel(data, priv->ioaddr + mii_data);
0329     writel(value, priv->ioaddr + mii_address);
0330 
0331     /* Wait until any existing MII operation is complete */
0332     ret = readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
0333                  100, 10000);
0334 
0335 err_disable_clks:
0336     pm_runtime_put(priv->device);
0337 
0338     return ret;
0339 }
0340 
0341 /**
0342  * stmmac_mdio_reset
0343  * @bus: points to the mii_bus structure
0344  * Description: reset the MII bus
0345  */
0346 int stmmac_mdio_reset(struct mii_bus *bus)
0347 {
0348 #if IS_ENABLED(CONFIG_STMMAC_PLATFORM)
0349     struct net_device *ndev = bus->priv;
0350     struct stmmac_priv *priv = netdev_priv(ndev);
0351     unsigned int mii_address = priv->hw->mii.addr;
0352 
0353 #ifdef CONFIG_OF
0354     if (priv->device->of_node) {
0355         struct gpio_desc *reset_gpio;
0356         u32 delays[3] = { 0, 0, 0 };
0357 
0358         reset_gpio = devm_gpiod_get_optional(priv->device,
0359                              "snps,reset",
0360                              GPIOD_OUT_LOW);
0361         if (IS_ERR(reset_gpio))
0362             return PTR_ERR(reset_gpio);
0363 
0364         device_property_read_u32_array(priv->device,
0365                            "snps,reset-delays-us",
0366                            delays, ARRAY_SIZE(delays));
0367 
0368         if (delays[0])
0369             msleep(DIV_ROUND_UP(delays[0], 1000));
0370 
0371         gpiod_set_value_cansleep(reset_gpio, 1);
0372         if (delays[1])
0373             msleep(DIV_ROUND_UP(delays[1], 1000));
0374 
0375         gpiod_set_value_cansleep(reset_gpio, 0);
0376         if (delays[2])
0377             msleep(DIV_ROUND_UP(delays[2], 1000));
0378     }
0379 #endif
0380 
0381     /* This is a workaround for problems with the STE101P PHY.
0382      * It doesn't complete its reset until at least one clock cycle
0383      * on MDC, so perform a dummy mdio read. To be updated for GMAC4
0384      * if needed.
0385      */
0386     if (!priv->plat->has_gmac4)
0387         writel(0, priv->ioaddr + mii_address);
0388 #endif
0389     return 0;
0390 }
0391 
0392 int stmmac_xpcs_setup(struct mii_bus *bus)
0393 {
0394     struct net_device *ndev = bus->priv;
0395     struct mdio_device *mdiodev;
0396     struct stmmac_priv *priv;
0397     struct dw_xpcs *xpcs;
0398     int mode, addr;
0399 
0400     priv = netdev_priv(ndev);
0401     mode = priv->plat->phy_interface;
0402 
0403     /* Try to probe the XPCS by scanning all addresses. */
0404     for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
0405         mdiodev = mdio_device_create(bus, addr);
0406         if (IS_ERR(mdiodev))
0407             continue;
0408 
0409         xpcs = xpcs_create(mdiodev, mode);
0410         if (IS_ERR_OR_NULL(xpcs)) {
0411             mdio_device_free(mdiodev);
0412             continue;
0413         }
0414 
0415         priv->hw->xpcs = xpcs;
0416         break;
0417     }
0418 
0419     if (!priv->hw->xpcs) {
0420         dev_warn(priv->device, "No xPCS found\n");
0421         return -ENODEV;
0422     }
0423 
0424     return 0;
0425 }
0426 
0427 /**
0428  * stmmac_mdio_register
0429  * @ndev: net device structure
0430  * Description: it registers the MII bus
0431  */
0432 int stmmac_mdio_register(struct net_device *ndev)
0433 {
0434     int err = 0;
0435     struct mii_bus *new_bus;
0436     struct stmmac_priv *priv = netdev_priv(ndev);
0437     struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
0438     struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
0439     struct device_node *mdio_node = priv->plat->mdio_node;
0440     struct device *dev = ndev->dev.parent;
0441     struct fwnode_handle *fixed_node;
0442     int addr, found, max_addr;
0443 
0444     if (!mdio_bus_data)
0445         return 0;
0446 
0447     new_bus = mdiobus_alloc();
0448     if (!new_bus)
0449         return -ENOMEM;
0450 
0451     if (mdio_bus_data->irqs)
0452         memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
0453 
0454     new_bus->name = "stmmac";
0455 
0456     if (priv->plat->has_gmac4)
0457         new_bus->probe_capabilities = MDIOBUS_C22_C45;
0458 
0459     if (priv->plat->has_xgmac) {
0460         new_bus->read = &stmmac_xgmac2_mdio_read;
0461         new_bus->write = &stmmac_xgmac2_mdio_write;
0462 
0463         /* Right now only C22 phys are supported */
0464         max_addr = MII_XGMAC_MAX_C22ADDR + 1;
0465 
0466         /* Check if DT specified an unsupported phy addr */
0467         if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR)
0468             dev_err(dev, "Unsupported phy_addr (max=%d)\n",
0469                     MII_XGMAC_MAX_C22ADDR);
0470     } else {
0471         new_bus->read = &stmmac_mdio_read;
0472         new_bus->write = &stmmac_mdio_write;
0473         max_addr = PHY_MAX_ADDR;
0474     }
0475 
0476     if (mdio_bus_data->needs_reset)
0477         new_bus->reset = &stmmac_mdio_reset;
0478 
0479     snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
0480          new_bus->name, priv->plat->bus_id);
0481     new_bus->priv = ndev;
0482     new_bus->phy_mask = mdio_bus_data->phy_mask;
0483     new_bus->parent = priv->device;
0484 
0485     err = of_mdiobus_register(new_bus, mdio_node);
0486     if (err != 0) {
0487         dev_err_probe(dev, err, "Cannot register the MDIO bus\n");
0488         goto bus_register_fail;
0489     }
0490 
0491     /* Looks like we need a dummy read for XGMAC only and C45 PHYs */
0492     if (priv->plat->has_xgmac)
0493         stmmac_xgmac2_mdio_read(new_bus, 0, MII_ADDR_C45);
0494 
0495     /* If fixed-link is set, skip PHY scanning */
0496     if (!fwnode)
0497         fwnode = dev_fwnode(priv->device);
0498 
0499     if (fwnode) {
0500         fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
0501         if (fixed_node) {
0502             fwnode_handle_put(fixed_node);
0503             goto bus_register_done;
0504         }
0505     }
0506 
0507     if (priv->plat->phy_node || mdio_node)
0508         goto bus_register_done;
0509 
0510     found = 0;
0511     for (addr = 0; addr < max_addr; addr++) {
0512         struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
0513 
0514         if (!phydev)
0515             continue;
0516 
0517         /*
0518          * If an IRQ was provided to be assigned after
0519          * the bus probe, do it here.
0520          */
0521         if (!mdio_bus_data->irqs &&
0522             (mdio_bus_data->probed_phy_irq > 0)) {
0523             new_bus->irq[addr] = mdio_bus_data->probed_phy_irq;
0524             phydev->irq = mdio_bus_data->probed_phy_irq;
0525         }
0526 
0527         /*
0528          * If we're going to bind the MAC to this PHY bus,
0529          * and no PHY number was provided to the MAC,
0530          * use the one probed here.
0531          */
0532         if (priv->plat->phy_addr == -1)
0533             priv->plat->phy_addr = addr;
0534 
0535         phy_attached_info(phydev);
0536         found = 1;
0537     }
0538 
0539     if (!found && !mdio_node) {
0540         dev_warn(dev, "No PHY found\n");
0541         err = -ENODEV;
0542         goto no_phy_found;
0543     }
0544 
0545 bus_register_done:
0546     priv->mii = new_bus;
0547 
0548     return 0;
0549 
0550 no_phy_found:
0551     mdiobus_unregister(new_bus);
0552 bus_register_fail:
0553     mdiobus_free(new_bus);
0554     return err;
0555 }
0556 
0557 /**
0558  * stmmac_mdio_unregister
0559  * @ndev: net device structure
0560  * Description: it unregisters the MII bus
0561  */
0562 int stmmac_mdio_unregister(struct net_device *ndev)
0563 {
0564     struct stmmac_priv *priv = netdev_priv(ndev);
0565 
0566     if (!priv->mii)
0567         return 0;
0568 
0569     if (priv->hw->xpcs) {
0570         mdio_device_free(priv->hw->xpcs->mdiodev);
0571         xpcs_destroy(priv->hw->xpcs);
0572     }
0573 
0574     mdiobus_unregister(priv->mii);
0575     priv->mii->priv = NULL;
0576     mdiobus_free(priv->mii);
0577     priv->mii = NULL;
0578 
0579     return 0;
0580 }
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