stmicro/stmmac/norm_desc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*******************************************************************************
0003   This contains the functions to handle the normal descriptors.
0004
0005   Copyright (C) 2007-2009  STMicroelectronics Ltd
0006
0007
0008   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0009 *******************************************************************************/
0010
0011 #include <linux/stmmac.h>
0012 #include "common.h"
0013 #include "descs_com.h"
0014
0015 static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x,
0016                    struct dma_desc *p, void __iomem *ioaddr)
0017 {
0018     struct net_device_stats *stats = (struct net_device_stats *)data;
0019     unsigned int tdes0 = le32_to_cpu(p->des0);
0020     unsigned int tdes1 = le32_to_cpu(p->des1);
0021     int ret = tx_done;
0022
0023     /* Get tx owner first */
0024     if (unlikely(tdes0 & TDES0_OWN))
0025         return tx_dma_own;
0026
0027     /* Verify tx error by looking at the last segment. */
0028     if (likely(!(tdes1 & TDES1_LAST_SEGMENT)))
0029         return tx_not_ls;
0030
0031     if (unlikely(tdes0 & TDES0_ERROR_SUMMARY)) {
0032         if (unlikely(tdes0 & TDES0_UNDERFLOW_ERROR)) {
0033             x->tx_underflow++;
0034             stats->tx_fifo_errors++;
0035         }
0036         if (unlikely(tdes0 & TDES0_NO_CARRIER)) {
0037             x->tx_carrier++;
0038             stats->tx_carrier_errors++;
0039         }
0040         if (unlikely(tdes0 & TDES0_LOSS_CARRIER)) {
0041             x->tx_losscarrier++;
0042             stats->tx_carrier_errors++;
0043         }
0044         if (unlikely((tdes0 & TDES0_EXCESSIVE_DEFERRAL) ||
0045                  (tdes0 & TDES0_EXCESSIVE_COLLISIONS) ||
0046                  (tdes0 & TDES0_LATE_COLLISION))) {
0047             unsigned int collisions;
0048
0049             collisions = (tdes0 & TDES0_COLLISION_COUNT_MASK) >> 3;
0050             stats->collisions += collisions;
0051         }
0052         ret = tx_err;
0053     }
0054
0055     if (tdes0 & TDES0_VLAN_FRAME)
0056         x->tx_vlan++;
0057
0058     if (unlikely(tdes0 & TDES0_DEFERRED))
0059         x->tx_deferred++;
0060
0061     return ret;
0062 }
0063
0064 static int ndesc_get_tx_len(struct dma_desc *p)
0065 {
0066     return (le32_to_cpu(p->des1) & RDES1_BUFFER1_SIZE_MASK);
0067 }
0068
0069 /* This function verifies if each incoming frame has some errors
0070  * and, if required, updates the multicast statistics.
0071  * In case of success, it returns good_frame because the GMAC device
0072  * is supposed to be able to compute the csum in HW. */
0073 static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
0074                    struct dma_desc *p)
0075 {
0076     int ret = good_frame;
0077     unsigned int rdes0 = le32_to_cpu(p->des0);
0078     struct net_device_stats *stats = (struct net_device_stats *)data;
0079
0080     if (unlikely(rdes0 & RDES0_OWN))
0081         return dma_own;
0082
0083     if (unlikely(!(rdes0 & RDES0_LAST_DESCRIPTOR))) {
0084         stats->rx_length_errors++;
0085         return discard_frame;
0086     }
0087
0088     if (unlikely(rdes0 & RDES0_ERROR_SUMMARY)) {
0089         if (unlikely(rdes0 & RDES0_DESCRIPTOR_ERROR))
0090             x->rx_desc++;
0091         if (unlikely(rdes0 & RDES0_SA_FILTER_FAIL))
0092             x->sa_filter_fail++;
0093         if (unlikely(rdes0 & RDES0_OVERFLOW_ERROR))
0094             x->overflow_error++;
0095         if (unlikely(rdes0 & RDES0_IPC_CSUM_ERROR))
0096             x->ipc_csum_error++;
0097         if (unlikely(rdes0 & RDES0_COLLISION)) {
0098             x->rx_collision++;
0099             stats->collisions++;
0100         }
0101         if (unlikely(rdes0 & RDES0_CRC_ERROR)) {
0102             x->rx_crc_errors++;
0103             stats->rx_crc_errors++;
0104         }
0105         ret = discard_frame;
0106     }
0107     if (unlikely(rdes0 & RDES0_DRIBBLING))
0108         x->dribbling_bit++;
0109
0110     if (unlikely(rdes0 & RDES0_LENGTH_ERROR)) {
0111         x->rx_length++;
0112         ret = discard_frame;
0113     }
0114     if (unlikely(rdes0 & RDES0_MII_ERROR)) {
0115         x->rx_mii++;
0116         ret = discard_frame;
0117     }
0118 #ifdef STMMAC_VLAN_TAG_USED
0119     if (rdes0 & RDES0_VLAN_TAG)
0120         x->vlan_tag++;
0121 #endif
0122     return ret;
0123 }
0124
0125 static void ndesc_init_rx_desc(struct dma_desc *p, int disable_rx_ic, int mode,
0126                    int end, int bfsize)
0127 {
0128     int bfsize1;
0129
0130     p->des0 |= cpu_to_le32(RDES0_OWN);
0131
0132     bfsize1 = min(bfsize, BUF_SIZE_2KiB - 1);
0133     p->des1 |= cpu_to_le32(bfsize1 & RDES1_BUFFER1_SIZE_MASK);
0134
0135     if (mode == STMMAC_CHAIN_MODE)
0136         ndesc_rx_set_on_chain(p, end);
0137     else
0138         ndesc_rx_set_on_ring(p, end, bfsize);
0139
0140     if (disable_rx_ic)
0141         p->des1 |= cpu_to_le32(RDES1_DISABLE_IC);
0142 }
0143
0144 static void ndesc_init_tx_desc(struct dma_desc *p, int mode, int end)
0145 {
0146     p->des0 &= cpu_to_le32(~TDES0_OWN);
0147     if (mode == STMMAC_CHAIN_MODE)
0148         ndesc_tx_set_on_chain(p);
0149     else
0150         ndesc_end_tx_desc_on_ring(p, end);
0151 }
0152
0153 static int ndesc_get_tx_owner(struct dma_desc *p)
0154 {
0155     return (le32_to_cpu(p->des0) & TDES0_OWN) >> 31;
0156 }
0157
0158 static void ndesc_set_tx_owner(struct dma_desc *p)
0159 {
0160     p->des0 |= cpu_to_le32(TDES0_OWN);
0161 }
0162
0163 static void ndesc_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
0164 {
0165     p->des0 |= cpu_to_le32(RDES0_OWN);
0166 }
0167
0168 static int ndesc_get_tx_ls(struct dma_desc *p)
0169 {
0170     return (le32_to_cpu(p->des1) & TDES1_LAST_SEGMENT) >> 30;
0171 }
0172
0173 static void ndesc_release_tx_desc(struct dma_desc *p, int mode)
0174 {
0175     int ter = (le32_to_cpu(p->des1) & TDES1_END_RING) >> 25;
0176
0177     memset(p, 0, offsetof(struct dma_desc, des2));
0178     if (mode == STMMAC_CHAIN_MODE)
0179         ndesc_tx_set_on_chain(p);
0180     else
0181         ndesc_end_tx_desc_on_ring(p, ter);
0182 }
0183
0184 static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
0185                   bool csum_flag, int mode, bool tx_own,
0186                   bool ls, unsigned int tot_pkt_len)
0187 {
0188     unsigned int tdes1 = le32_to_cpu(p->des1);
0189
0190     if (is_fs)
0191         tdes1 |= TDES1_FIRST_SEGMENT;
0192     else
0193         tdes1 &= ~TDES1_FIRST_SEGMENT;
0194
0195     if (likely(csum_flag))
0196         tdes1 |= (TX_CIC_FULL) << TDES1_CHECKSUM_INSERTION_SHIFT;
0197     else
0198         tdes1 &= ~(TX_CIC_FULL << TDES1_CHECKSUM_INSERTION_SHIFT);
0199
0200     if (ls)
0201         tdes1 |= TDES1_LAST_SEGMENT;
0202
0203     p->des1 = cpu_to_le32(tdes1);
0204
0205     if (mode == STMMAC_CHAIN_MODE)
0206         norm_set_tx_desc_len_on_chain(p, len);
0207     else
0208         norm_set_tx_desc_len_on_ring(p, len);
0209
0210     if (tx_own)
0211         p->des0 |= cpu_to_le32(TDES0_OWN);
0212 }
0213
0214 static void ndesc_set_tx_ic(struct dma_desc *p)
0215 {
0216     p->des1 |= cpu_to_le32(TDES1_INTERRUPT);
0217 }
0218
0219 static int ndesc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
0220 {
0221     unsigned int csum = 0;
0222
0223     /* The type-1 checksum offload engines append the checksum at
0224      * the end of frame and the two bytes of checksum are added in
0225      * the length.
0226      * Adjust for that in the framelen for type-1 checksum offload
0227      * engines
0228      */
0229     if (rx_coe_type == STMMAC_RX_COE_TYPE1)
0230         csum = 2;
0231
0232     return (((le32_to_cpu(p->des0) & RDES0_FRAME_LEN_MASK)
0233                 >> RDES0_FRAME_LEN_SHIFT) -
0234         csum);
0235
0236 }
0237
0238 static void ndesc_enable_tx_timestamp(struct dma_desc *p)
0239 {
0240     p->des1 |= cpu_to_le32(TDES1_TIME_STAMP_ENABLE);
0241 }
0242
0243 static int ndesc_get_tx_timestamp_status(struct dma_desc *p)
0244 {
0245     return (le32_to_cpu(p->des0) & TDES0_TIME_STAMP_STATUS) >> 17;
0246 }
0247
0248 static void ndesc_get_timestamp(void *desc, u32 ats, u64 *ts)
0249 {
0250     struct dma_desc *p = (struct dma_desc *)desc;
0251     u64 ns;
0252
0253     ns = le32_to_cpu(p->des2);
0254     /* convert high/sec time stamp value to nanosecond */
0255     ns += le32_to_cpu(p->des3) * 1000000000ULL;
0256
0257     *ts = ns;
0258 }
0259
0260 static int ndesc_get_rx_timestamp_status(void *desc, void *next_desc, u32 ats)
0261 {
0262     struct dma_desc *p = (struct dma_desc *)desc;
0263
0264     if ((le32_to_cpu(p->des2) == 0xffffffff) &&
0265         (le32_to_cpu(p->des3) == 0xffffffff))
0266         /* timestamp is corrupted, hence don't store it */
0267         return 0;
0268     else
0269         return 1;
0270 }
0271
0272 static void ndesc_display_ring(void *head, unsigned int size, bool rx,
0273                    dma_addr_t dma_rx_phy, unsigned int desc_size)
0274 {
0275     struct dma_desc *p = (struct dma_desc *)head;
0276     dma_addr_t dma_addr;
0277     int i;
0278
0279     pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
0280
0281     for (i = 0; i < size; i++) {
0282         u64 x;
0283         dma_addr = dma_rx_phy + i * sizeof(*p);
0284
0285         x = *(u64 *)p;
0286         pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x",
0287             i, &dma_addr,
0288             (unsigned int)x, (unsigned int)(x >> 32),
0289             p->des2, p->des3);
0290         p++;
0291     }
0292     pr_info("\n");
0293 }
0294
0295 static void ndesc_set_addr(struct dma_desc *p, dma_addr_t addr)
0296 {
0297     p->des2 = cpu_to_le32(addr);
0298 }
0299
0300 static void ndesc_clear(struct dma_desc *p)
0301 {
0302     p->des2 = 0;
0303 }
0304
0305 const struct stmmac_desc_ops ndesc_ops = {
0306     .tx_status = ndesc_get_tx_status,
0307     .rx_status = ndesc_get_rx_status,
0308     .get_tx_len = ndesc_get_tx_len,
0309     .init_rx_desc = ndesc_init_rx_desc,
0310     .init_tx_desc = ndesc_init_tx_desc,
0311     .get_tx_owner = ndesc_get_tx_owner,
0312     .release_tx_desc = ndesc_release_tx_desc,
0313     .prepare_tx_desc = ndesc_prepare_tx_desc,
0314     .set_tx_ic = ndesc_set_tx_ic,
0315     .get_tx_ls = ndesc_get_tx_ls,
0316     .set_tx_owner = ndesc_set_tx_owner,
0317     .set_rx_owner = ndesc_set_rx_owner,
0318     .get_rx_frame_len = ndesc_get_rx_frame_len,
0319     .enable_tx_timestamp = ndesc_enable_tx_timestamp,
0320     .get_tx_timestamp_status = ndesc_get_tx_timestamp_status,
0321     .get_timestamp = ndesc_get_timestamp,
0322     .get_rx_timestamp_status = ndesc_get_rx_timestamp_status,
0323     .display_ring = ndesc_display_ring,
0324     .set_addr = ndesc_set_addr,
0325     .clear = ndesc_clear,
0326 };