stmicro/stmmac/mmc_core.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*******************************************************************************
0003   DWMAC Management Counters
0004
0005   Copyright (C) 2011  STMicroelectronics Ltd
0006
0007
0008   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0009 *******************************************************************************/
0010
0011 #include <linux/kernel.h>
0012 #include <linux/io.h>
0013 #include "hwif.h"
0014 #include "mmc.h"
0015
0016 /* MAC Management Counters register offset */
0017
0018 #define MMC_CNTRL       0x00    /* MMC Control */
0019 #define MMC_RX_INTR     0x04    /* MMC RX Interrupt */
0020 #define MMC_TX_INTR     0x08    /* MMC TX Interrupt */
0021 #define MMC_RX_INTR_MASK    0x0c    /* MMC Interrupt Mask */
0022 #define MMC_TX_INTR_MASK    0x10    /* MMC Interrupt Mask */
0023 #define MMC_DEFAULT_MASK    0xffffffff
0024
0025 /* MMC TX counter registers */
0026
0027 /* Note:
0028  * _GB register stands for good and bad frames
0029  * _G is for good only.
0030  */
0031 #define MMC_TX_OCTETCOUNT_GB        0x14
0032 #define MMC_TX_FRAMECOUNT_GB        0x18
0033 #define MMC_TX_BROADCASTFRAME_G     0x1c
0034 #define MMC_TX_MULTICASTFRAME_G     0x20
0035 #define MMC_TX_64_OCTETS_GB     0x24
0036 #define MMC_TX_65_TO_127_OCTETS_GB  0x28
0037 #define MMC_TX_128_TO_255_OCTETS_GB 0x2c
0038 #define MMC_TX_256_TO_511_OCTETS_GB 0x30
0039 #define MMC_TX_512_TO_1023_OCTETS_GB    0x34
0040 #define MMC_TX_1024_TO_MAX_OCTETS_GB    0x38
0041 #define MMC_TX_UNICAST_GB       0x3c
0042 #define MMC_TX_MULTICAST_GB     0x40
0043 #define MMC_TX_BROADCAST_GB     0x44
0044 #define MMC_TX_UNDERFLOW_ERROR      0x48
0045 #define MMC_TX_SINGLECOL_G      0x4c
0046 #define MMC_TX_MULTICOL_G       0x50
0047 #define MMC_TX_DEFERRED         0x54
0048 #define MMC_TX_LATECOL          0x58
0049 #define MMC_TX_EXESSCOL         0x5c
0050 #define MMC_TX_CARRIER_ERROR        0x60
0051 #define MMC_TX_OCTETCOUNT_G     0x64
0052 #define MMC_TX_FRAMECOUNT_G     0x68
0053 #define MMC_TX_EXCESSDEF        0x6c
0054 #define MMC_TX_PAUSE_FRAME      0x70
0055 #define MMC_TX_VLAN_FRAME_G     0x74
0056
0057 /* MMC RX counter registers */
0058 #define MMC_RX_FRAMECOUNT_GB        0x80
0059 #define MMC_RX_OCTETCOUNT_GB        0x84
0060 #define MMC_RX_OCTETCOUNT_G     0x88
0061 #define MMC_RX_BROADCASTFRAME_G     0x8c
0062 #define MMC_RX_MULTICASTFRAME_G     0x90
0063 #define MMC_RX_CRC_ERROR        0x94
0064 #define MMC_RX_ALIGN_ERROR      0x98
0065 #define MMC_RX_RUN_ERROR        0x9C
0066 #define MMC_RX_JABBER_ERROR     0xA0
0067 #define MMC_RX_UNDERSIZE_G      0xA4
0068 #define MMC_RX_OVERSIZE_G       0xA8
0069 #define MMC_RX_64_OCTETS_GB     0xAC
0070 #define MMC_RX_65_TO_127_OCTETS_GB  0xb0
0071 #define MMC_RX_128_TO_255_OCTETS_GB 0xb4
0072 #define MMC_RX_256_TO_511_OCTETS_GB 0xb8
0073 #define MMC_RX_512_TO_1023_OCTETS_GB    0xbc
0074 #define MMC_RX_1024_TO_MAX_OCTETS_GB    0xc0
0075 #define MMC_RX_UNICAST_G        0xc4
0076 #define MMC_RX_LENGTH_ERROR     0xc8
0077 #define MMC_RX_AUTOFRANGETYPE       0xcc
0078 #define MMC_RX_PAUSE_FRAMES     0xd0
0079 #define MMC_RX_FIFO_OVERFLOW        0xd4
0080 #define MMC_RX_VLAN_FRAMES_GB       0xd8
0081 #define MMC_RX_WATCHDOG_ERROR       0xdc
0082 /* IPC*/
0083 #define MMC_RX_IPC_INTR_MASK        0x100
0084 #define MMC_RX_IPC_INTR         0x108
0085 /* IPv4*/
0086 #define MMC_RX_IPV4_GD          0x110
0087 #define MMC_RX_IPV4_HDERR       0x114
0088 #define MMC_RX_IPV4_NOPAY       0x118
0089 #define MMC_RX_IPV4_FRAG        0x11C
0090 #define MMC_RX_IPV4_UDSBL       0x120
0091
0092 #define MMC_RX_IPV4_GD_OCTETS       0x150
0093 #define MMC_RX_IPV4_HDERR_OCTETS    0x154
0094 #define MMC_RX_IPV4_NOPAY_OCTETS    0x158
0095 #define MMC_RX_IPV4_FRAG_OCTETS     0x15c
0096 #define MMC_RX_IPV4_UDSBL_OCTETS    0x160
0097
0098 /* IPV6*/
0099 #define MMC_RX_IPV6_GD_OCTETS       0x164
0100 #define MMC_RX_IPV6_HDERR_OCTETS    0x168
0101 #define MMC_RX_IPV6_NOPAY_OCTETS    0x16c
0102
0103 #define MMC_RX_IPV6_GD          0x124
0104 #define MMC_RX_IPV6_HDERR       0x128
0105 #define MMC_RX_IPV6_NOPAY       0x12c
0106
0107 /* Protocols*/
0108 #define MMC_RX_UDP_GD           0x130
0109 #define MMC_RX_UDP_ERR          0x134
0110 #define MMC_RX_TCP_GD           0x138
0111 #define MMC_RX_TCP_ERR          0x13c
0112 #define MMC_RX_ICMP_GD          0x140
0113 #define MMC_RX_ICMP_ERR         0x144
0114
0115 #define MMC_RX_UDP_GD_OCTETS        0x170
0116 #define MMC_RX_UDP_ERR_OCTETS       0x174
0117 #define MMC_RX_TCP_GD_OCTETS        0x178
0118 #define MMC_RX_TCP_ERR_OCTETS       0x17c
0119 #define MMC_RX_ICMP_GD_OCTETS       0x180
0120 #define MMC_RX_ICMP_ERR_OCTETS      0x184
0121
0122 #define MMC_TX_FPE_FRAG         0x1a8
0123 #define MMC_TX_HOLD_REQ         0x1ac
0124 #define MMC_RX_PKT_ASSEMBLY_ERR     0x1c8
0125 #define MMC_RX_PKT_SMD_ERR      0x1cc
0126 #define MMC_RX_PKT_ASSEMBLY_OK      0x1d0
0127 #define MMC_RX_FPE_FRAG         0x1d4
0128
0129 /* XGMAC MMC Registers */
0130 #define MMC_XGMAC_TX_OCTET_GB       0x14
0131 #define MMC_XGMAC_TX_PKT_GB     0x1c
0132 #define MMC_XGMAC_TX_BROAD_PKT_G    0x24
0133 #define MMC_XGMAC_TX_MULTI_PKT_G    0x2c
0134 #define MMC_XGMAC_TX_64OCT_GB       0x34
0135 #define MMC_XGMAC_TX_65OCT_GB       0x3c
0136 #define MMC_XGMAC_TX_128OCT_GB      0x44
0137 #define MMC_XGMAC_TX_256OCT_GB      0x4c
0138 #define MMC_XGMAC_TX_512OCT_GB      0x54
0139 #define MMC_XGMAC_TX_1024OCT_GB     0x5c
0140 #define MMC_XGMAC_TX_UNI_PKT_GB     0x64
0141 #define MMC_XGMAC_TX_MULTI_PKT_GB   0x6c
0142 #define MMC_XGMAC_TX_BROAD_PKT_GB   0x74
0143 #define MMC_XGMAC_TX_UNDER      0x7c
0144 #define MMC_XGMAC_TX_OCTET_G        0x84
0145 #define MMC_XGMAC_TX_PKT_G      0x8c
0146 #define MMC_XGMAC_TX_PAUSE      0x94
0147 #define MMC_XGMAC_TX_VLAN_PKT_G     0x9c
0148 #define MMC_XGMAC_TX_LPI_USEC       0xa4
0149 #define MMC_XGMAC_TX_LPI_TRAN       0xa8
0150
0151 #define MMC_XGMAC_RX_PKT_GB     0x100
0152 #define MMC_XGMAC_RX_OCTET_GB       0x108
0153 #define MMC_XGMAC_RX_OCTET_G        0x110
0154 #define MMC_XGMAC_RX_BROAD_PKT_G    0x118
0155 #define MMC_XGMAC_RX_MULTI_PKT_G    0x120
0156 #define MMC_XGMAC_RX_CRC_ERR        0x128
0157 #define MMC_XGMAC_RX_RUNT_ERR       0x130
0158 #define MMC_XGMAC_RX_JABBER_ERR     0x134
0159 #define MMC_XGMAC_RX_UNDER      0x138
0160 #define MMC_XGMAC_RX_OVER       0x13c
0161 #define MMC_XGMAC_RX_64OCT_GB       0x140
0162 #define MMC_XGMAC_RX_65OCT_GB       0x148
0163 #define MMC_XGMAC_RX_128OCT_GB      0x150
0164 #define MMC_XGMAC_RX_256OCT_GB      0x158
0165 #define MMC_XGMAC_RX_512OCT_GB      0x160
0166 #define MMC_XGMAC_RX_1024OCT_GB     0x168
0167 #define MMC_XGMAC_RX_UNI_PKT_G      0x170
0168 #define MMC_XGMAC_RX_LENGTH_ERR     0x178
0169 #define MMC_XGMAC_RX_RANGE      0x180
0170 #define MMC_XGMAC_RX_PAUSE      0x188
0171 #define MMC_XGMAC_RX_FIFOOVER_PKT   0x190
0172 #define MMC_XGMAC_RX_VLAN_PKT_GB    0x198
0173 #define MMC_XGMAC_RX_WATCHDOG_ERR   0x1a0
0174 #define MMC_XGMAC_RX_LPI_USEC       0x1a4
0175 #define MMC_XGMAC_RX_LPI_TRAN       0x1a8
0176 #define MMC_XGMAC_RX_DISCARD_PKT_GB 0x1ac
0177 #define MMC_XGMAC_RX_DISCARD_OCT_GB 0x1b4
0178 #define MMC_XGMAC_RX_ALIGN_ERR_PKT  0x1bc
0179
0180 #define MMC_XGMAC_TX_FPE_FRAG       0x208
0181 #define MMC_XGMAC_TX_HOLD_REQ       0x20c
0182 #define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR   0x228
0183 #define MMC_XGMAC_RX_PKT_SMD_ERR    0x22c
0184 #define MMC_XGMAC_RX_PKT_ASSEMBLY_OK    0x230
0185 #define MMC_XGMAC_RX_FPE_FRAG       0x234
0186 #define MMC_XGMAC_RX_IPC_INTR_MASK  0x25c
0187
0188 static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
0189 {
0190     u32 value = readl(mmcaddr + MMC_CNTRL);
0191
0192     value |= (mode & 0x3F);
0193
0194     writel(value, mmcaddr + MMC_CNTRL);
0195
0196     pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n",
0197          MMC_CNTRL, value);
0198 }
0199
0200 /* To mask all interrupts.*/
0201 static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)
0202 {
0203     writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);
0204     writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);
0205     writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK);
0206 }
0207
0208 /* This reads the MAC core counters (if actaully supported).
0209  * by default the MMC core is programmed to reset each
0210  * counter after a read. So all the field of the mmc struct
0211  * have to be incremented.
0212  */
0213 static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
0214 {
0215     mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB);
0216     mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB);
0217     mmc->mmc_tx_broadcastframe_g += readl(mmcaddr +
0218                           MMC_TX_BROADCASTFRAME_G);
0219     mmc->mmc_tx_multicastframe_g += readl(mmcaddr +
0220                           MMC_TX_MULTICASTFRAME_G);
0221     mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB);
0222     mmc->mmc_tx_65_to_127_octets_gb +=
0223         readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB);
0224     mmc->mmc_tx_128_to_255_octets_gb +=
0225         readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB);
0226     mmc->mmc_tx_256_to_511_octets_gb +=
0227         readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB);
0228     mmc->mmc_tx_512_to_1023_octets_gb +=
0229         readl(mmcaddr + MMC_TX_512_TO_1023_OCTETS_GB);
0230     mmc->mmc_tx_1024_to_max_octets_gb +=
0231         readl(mmcaddr + MMC_TX_1024_TO_MAX_OCTETS_GB);
0232     mmc->mmc_tx_unicast_gb += readl(mmcaddr + MMC_TX_UNICAST_GB);
0233     mmc->mmc_tx_multicast_gb += readl(mmcaddr + MMC_TX_MULTICAST_GB);
0234     mmc->mmc_tx_broadcast_gb += readl(mmcaddr + MMC_TX_BROADCAST_GB);
0235     mmc->mmc_tx_underflow_error += readl(mmcaddr + MMC_TX_UNDERFLOW_ERROR);
0236     mmc->mmc_tx_singlecol_g += readl(mmcaddr + MMC_TX_SINGLECOL_G);
0237     mmc->mmc_tx_multicol_g += readl(mmcaddr + MMC_TX_MULTICOL_G);
0238     mmc->mmc_tx_deferred += readl(mmcaddr + MMC_TX_DEFERRED);
0239     mmc->mmc_tx_latecol += readl(mmcaddr + MMC_TX_LATECOL);
0240     mmc->mmc_tx_exesscol += readl(mmcaddr + MMC_TX_EXESSCOL);
0241     mmc->mmc_tx_carrier_error += readl(mmcaddr + MMC_TX_CARRIER_ERROR);
0242     mmc->mmc_tx_octetcount_g += readl(mmcaddr + MMC_TX_OCTETCOUNT_G);
0243     mmc->mmc_tx_framecount_g += readl(mmcaddr + MMC_TX_FRAMECOUNT_G);
0244     mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF);
0245     mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME);
0246     mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G);
0247
0248     /* MMC RX counter registers */
0249     mmc->mmc_rx_framecount_gb += readl(mmcaddr + MMC_RX_FRAMECOUNT_GB);
0250     mmc->mmc_rx_octetcount_gb += readl(mmcaddr + MMC_RX_OCTETCOUNT_GB);
0251     mmc->mmc_rx_octetcount_g += readl(mmcaddr + MMC_RX_OCTETCOUNT_G);
0252     mmc->mmc_rx_broadcastframe_g += readl(mmcaddr +
0253                           MMC_RX_BROADCASTFRAME_G);
0254     mmc->mmc_rx_multicastframe_g += readl(mmcaddr +
0255                           MMC_RX_MULTICASTFRAME_G);
0256     mmc->mmc_rx_crc_error += readl(mmcaddr + MMC_RX_CRC_ERROR);
0257     mmc->mmc_rx_align_error += readl(mmcaddr + MMC_RX_ALIGN_ERROR);
0258     mmc->mmc_rx_run_error += readl(mmcaddr + MMC_RX_RUN_ERROR);
0259     mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_RX_JABBER_ERROR);
0260     mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_RX_UNDERSIZE_G);
0261     mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_RX_OVERSIZE_G);
0262     mmc->mmc_rx_64_octets_gb += readl(mmcaddr + MMC_RX_64_OCTETS_GB);
0263     mmc->mmc_rx_65_to_127_octets_gb +=
0264         readl(mmcaddr + MMC_RX_65_TO_127_OCTETS_GB);
0265     mmc->mmc_rx_128_to_255_octets_gb +=
0266         readl(mmcaddr + MMC_RX_128_TO_255_OCTETS_GB);
0267     mmc->mmc_rx_256_to_511_octets_gb +=
0268         readl(mmcaddr + MMC_RX_256_TO_511_OCTETS_GB);
0269     mmc->mmc_rx_512_to_1023_octets_gb +=
0270         readl(mmcaddr + MMC_RX_512_TO_1023_OCTETS_GB);
0271     mmc->mmc_rx_1024_to_max_octets_gb +=
0272         readl(mmcaddr + MMC_RX_1024_TO_MAX_OCTETS_GB);
0273     mmc->mmc_rx_unicast_g += readl(mmcaddr + MMC_RX_UNICAST_G);
0274     mmc->mmc_rx_length_error += readl(mmcaddr + MMC_RX_LENGTH_ERROR);
0275     mmc->mmc_rx_autofrangetype += readl(mmcaddr + MMC_RX_AUTOFRANGETYPE);
0276     mmc->mmc_rx_pause_frames += readl(mmcaddr + MMC_RX_PAUSE_FRAMES);
0277     mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW);
0278     mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB);
0279     mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR);
0280     /* IPC */
0281     mmc->mmc_rx_ipc_intr_mask += readl(mmcaddr + MMC_RX_IPC_INTR_MASK);
0282     mmc->mmc_rx_ipc_intr += readl(mmcaddr + MMC_RX_IPC_INTR);
0283     /* IPv4 */
0284     mmc->mmc_rx_ipv4_gd += readl(mmcaddr + MMC_RX_IPV4_GD);
0285     mmc->mmc_rx_ipv4_hderr += readl(mmcaddr + MMC_RX_IPV4_HDERR);
0286     mmc->mmc_rx_ipv4_nopay += readl(mmcaddr + MMC_RX_IPV4_NOPAY);
0287     mmc->mmc_rx_ipv4_frag += readl(mmcaddr + MMC_RX_IPV4_FRAG);
0288     mmc->mmc_rx_ipv4_udsbl += readl(mmcaddr + MMC_RX_IPV4_UDSBL);
0289
0290     mmc->mmc_rx_ipv4_gd_octets += readl(mmcaddr + MMC_RX_IPV4_GD_OCTETS);
0291     mmc->mmc_rx_ipv4_hderr_octets +=
0292         readl(mmcaddr + MMC_RX_IPV4_HDERR_OCTETS);
0293     mmc->mmc_rx_ipv4_nopay_octets +=
0294         readl(mmcaddr + MMC_RX_IPV4_NOPAY_OCTETS);
0295     mmc->mmc_rx_ipv4_frag_octets += readl(mmcaddr +
0296                           MMC_RX_IPV4_FRAG_OCTETS);
0297     mmc->mmc_rx_ipv4_udsbl_octets +=
0298         readl(mmcaddr + MMC_RX_IPV4_UDSBL_OCTETS);
0299
0300     /* IPV6 */
0301     mmc->mmc_rx_ipv6_gd_octets += readl(mmcaddr + MMC_RX_IPV6_GD_OCTETS);
0302     mmc->mmc_rx_ipv6_hderr_octets +=
0303         readl(mmcaddr + MMC_RX_IPV6_HDERR_OCTETS);
0304     mmc->mmc_rx_ipv6_nopay_octets +=
0305         readl(mmcaddr + MMC_RX_IPV6_NOPAY_OCTETS);
0306
0307     mmc->mmc_rx_ipv6_gd += readl(mmcaddr + MMC_RX_IPV6_GD);
0308     mmc->mmc_rx_ipv6_hderr += readl(mmcaddr + MMC_RX_IPV6_HDERR);
0309     mmc->mmc_rx_ipv6_nopay += readl(mmcaddr + MMC_RX_IPV6_NOPAY);
0310
0311     /* Protocols */
0312     mmc->mmc_rx_udp_gd += readl(mmcaddr + MMC_RX_UDP_GD);
0313     mmc->mmc_rx_udp_err += readl(mmcaddr + MMC_RX_UDP_ERR);
0314     mmc->mmc_rx_tcp_gd += readl(mmcaddr + MMC_RX_TCP_GD);
0315     mmc->mmc_rx_tcp_err += readl(mmcaddr + MMC_RX_TCP_ERR);
0316     mmc->mmc_rx_icmp_gd += readl(mmcaddr + MMC_RX_ICMP_GD);
0317     mmc->mmc_rx_icmp_err += readl(mmcaddr + MMC_RX_ICMP_ERR);
0318
0319     mmc->mmc_rx_udp_gd_octets += readl(mmcaddr + MMC_RX_UDP_GD_OCTETS);
0320     mmc->mmc_rx_udp_err_octets += readl(mmcaddr + MMC_RX_UDP_ERR_OCTETS);
0321     mmc->mmc_rx_tcp_gd_octets += readl(mmcaddr + MMC_RX_TCP_GD_OCTETS);
0322     mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS);
0323     mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS);
0324     mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS);
0325
0326     mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_TX_FPE_FRAG);
0327     mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_TX_HOLD_REQ);
0328     mmc->mmc_rx_packet_assembly_err_cntr +=
0329         readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_ERR);
0330     mmc->mmc_rx_packet_smd_err_cntr += readl(mmcaddr + MMC_RX_PKT_SMD_ERR);
0331     mmc->mmc_rx_packet_assembly_ok_cntr +=
0332         readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_OK);
0333     mmc->mmc_rx_fpe_fragment_cntr += readl(mmcaddr + MMC_RX_FPE_FRAG);
0334 }
0335
0336 const struct stmmac_mmc_ops dwmac_mmc_ops = {
0337     .ctrl = dwmac_mmc_ctrl,
0338     .intr_all_mask = dwmac_mmc_intr_all_mask,
0339     .read = dwmac_mmc_read,
0340 };
0341
0342 static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
0343 {
0344     u32 value = readl(mmcaddr + MMC_CNTRL);
0345
0346     value |= (mode & 0x3F);
0347
0348     writel(value, mmcaddr + MMC_CNTRL);
0349 }
0350
0351 static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)
0352 {
0353     writel(0x0, mmcaddr + MMC_RX_INTR_MASK);
0354     writel(0x0, mmcaddr + MMC_TX_INTR_MASK);
0355     writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK);
0356 }
0357
0358 static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest)
0359 {
0360     u64 tmp = 0;
0361
0362     tmp += readl(addr + reg);
0363     tmp += ((u64 )readl(addr + reg + 0x4)) << 32;
0364     if (tmp > GENMASK(31, 0))
0365         *dest = ~0x0;
0366     else
0367         *dest = *dest + tmp;
0368 }
0369
0370 /* This reads the MAC core counters (if actaully supported).
0371  * by default the MMC core is programmed to reset each
0372  * counter after a read. So all the field of the mmc struct
0373  * have to be incremented.
0374  */
0375 static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
0376 {
0377     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_GB,
0378                  &mmc->mmc_tx_octetcount_gb);
0379     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_GB,
0380                  &mmc->mmc_tx_framecount_gb);
0381     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_G,
0382                  &mmc->mmc_tx_broadcastframe_g);
0383     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_G,
0384                  &mmc->mmc_tx_multicastframe_g);
0385     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_64OCT_GB,
0386                  &mmc->mmc_tx_64_octets_gb);
0387     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_65OCT_GB,
0388                  &mmc->mmc_tx_65_to_127_octets_gb);
0389     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_128OCT_GB,
0390                  &mmc->mmc_tx_128_to_255_octets_gb);
0391     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_256OCT_GB,
0392                  &mmc->mmc_tx_256_to_511_octets_gb);
0393     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_512OCT_GB,
0394                  &mmc->mmc_tx_512_to_1023_octets_gb);
0395     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_1024OCT_GB,
0396                  &mmc->mmc_tx_1024_to_max_octets_gb);
0397     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNI_PKT_GB,
0398                  &mmc->mmc_tx_unicast_gb);
0399     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_GB,
0400                  &mmc->mmc_tx_multicast_gb);
0401     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_GB,
0402                  &mmc->mmc_tx_broadcast_gb);
0403     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNDER,
0404                  &mmc->mmc_tx_underflow_error);
0405     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_G,
0406                  &mmc->mmc_tx_octetcount_g);
0407     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_G,
0408                  &mmc->mmc_tx_framecount_g);
0409     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PAUSE,
0410                  &mmc->mmc_tx_pause_frame);
0411     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_VLAN_PKT_G,
0412                  &mmc->mmc_tx_vlan_frame_g);
0413
0414     /* MMC RX counter registers */
0415     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PKT_GB,
0416                  &mmc->mmc_rx_framecount_gb);
0417     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_GB,
0418                  &mmc->mmc_rx_octetcount_gb);
0419     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_G,
0420                  &mmc->mmc_rx_octetcount_g);
0421     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_BROAD_PKT_G,
0422                  &mmc->mmc_rx_broadcastframe_g);
0423     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_MULTI_PKT_G,
0424                  &mmc->mmc_rx_multicastframe_g);
0425     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
0426                  &mmc->mmc_rx_crc_error);
0427     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
0428                  &mmc->mmc_rx_crc_error);
0429     mmc->mmc_rx_run_error += readl(mmcaddr + MMC_XGMAC_RX_RUNT_ERR);
0430     mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_XGMAC_RX_JABBER_ERR);
0431     mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_XGMAC_RX_UNDER);
0432     mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_XGMAC_RX_OVER);
0433     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_64OCT_GB,
0434                  &mmc->mmc_rx_64_octets_gb);
0435     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_65OCT_GB,
0436                  &mmc->mmc_rx_65_to_127_octets_gb);
0437     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_128OCT_GB,
0438                  &mmc->mmc_rx_128_to_255_octets_gb);
0439     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_256OCT_GB,
0440                  &mmc->mmc_rx_256_to_511_octets_gb);
0441     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_512OCT_GB,
0442                  &mmc->mmc_rx_512_to_1023_octets_gb);
0443     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_1024OCT_GB,
0444                  &mmc->mmc_rx_1024_to_max_octets_gb);
0445     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UNI_PKT_G,
0446                  &mmc->mmc_rx_unicast_g);
0447     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_LENGTH_ERR,
0448                  &mmc->mmc_rx_length_error);
0449     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_RANGE,
0450                  &mmc->mmc_rx_autofrangetype);
0451     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PAUSE,
0452                  &mmc->mmc_rx_pause_frames);
0453     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_FIFOOVER_PKT,
0454                  &mmc->mmc_rx_fifo_overflow);
0455     dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_VLAN_PKT_GB,
0456                  &mmc->mmc_rx_vlan_frames_gb);
0457     mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_XGMAC_RX_WATCHDOG_ERR);
0458
0459     mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_XGMAC_TX_FPE_FRAG);
0460     mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_XGMAC_TX_HOLD_REQ);
0461     mmc->mmc_rx_packet_assembly_err_cntr +=
0462         readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_ERR);
0463     mmc->mmc_rx_packet_smd_err_cntr +=
0464         readl(mmcaddr + MMC_XGMAC_RX_PKT_SMD_ERR);
0465     mmc->mmc_rx_packet_assembly_ok_cntr +=
0466         readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_OK);
0467     mmc->mmc_rx_fpe_fragment_cntr +=
0468         readl(mmcaddr + MMC_XGMAC_RX_FPE_FRAG);
0469 }
0470
0471 const struct stmmac_mmc_ops dwxgmac_mmc_ops = {
0472     .ctrl = dwxgmac_mmc_ctrl,
0473     .intr_all_mask = dwxgmac_mmc_intr_all_mask,
0474     .read = dwxgmac_mmc_read,
0475 };