stmicro/stmmac/dwxgmac2_descs.c

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003  * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
0004  * stmmac XGMAC support.
0005  */
0006
0007 #include <linux/stmmac.h>
0008 #include "common.h"
0009 #include "dwxgmac2.h"
0010
0011 static int dwxgmac2_get_tx_status(void *data, struct stmmac_extra_stats *x,
0012                   struct dma_desc *p, void __iomem *ioaddr)
0013 {
0014     unsigned int tdes3 = le32_to_cpu(p->des3);
0015     int ret = tx_done;
0016
0017     if (unlikely(tdes3 & XGMAC_TDES3_OWN))
0018         return tx_dma_own;
0019     if (likely(!(tdes3 & XGMAC_TDES3_LD)))
0020         return tx_not_ls;
0021
0022     return ret;
0023 }
0024
0025 static int dwxgmac2_get_rx_status(void *data, struct stmmac_extra_stats *x,
0026                   struct dma_desc *p)
0027 {
0028     unsigned int rdes3 = le32_to_cpu(p->des3);
0029
0030     if (unlikely(rdes3 & XGMAC_RDES3_OWN))
0031         return dma_own;
0032     if (unlikely(rdes3 & XGMAC_RDES3_CTXT))
0033         return discard_frame;
0034     if (likely(!(rdes3 & XGMAC_RDES3_LD)))
0035         return rx_not_ls;
0036     if (unlikely((rdes3 & XGMAC_RDES3_ES) && (rdes3 & XGMAC_RDES3_LD)))
0037         return discard_frame;
0038
0039     return good_frame;
0040 }
0041
0042 static int dwxgmac2_get_tx_len(struct dma_desc *p)
0043 {
0044     return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L);
0045 }
0046
0047 static int dwxgmac2_get_tx_owner(struct dma_desc *p)
0048 {
0049     return (le32_to_cpu(p->des3) & XGMAC_TDES3_OWN) > 0;
0050 }
0051
0052 static void dwxgmac2_set_tx_owner(struct dma_desc *p)
0053 {
0054     p->des3 |= cpu_to_le32(XGMAC_TDES3_OWN);
0055 }
0056
0057 static void dwxgmac2_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
0058 {
0059     p->des3 |= cpu_to_le32(XGMAC_RDES3_OWN);
0060
0061     if (!disable_rx_ic)
0062         p->des3 |= cpu_to_le32(XGMAC_RDES3_IOC);
0063 }
0064
0065 static int dwxgmac2_get_tx_ls(struct dma_desc *p)
0066 {
0067     return (le32_to_cpu(p->des3) & XGMAC_RDES3_LD) > 0;
0068 }
0069
0070 static int dwxgmac2_get_rx_frame_len(struct dma_desc *p, int rx_coe)
0071 {
0072     return (le32_to_cpu(p->des3) & XGMAC_RDES3_PL);
0073 }
0074
0075 static void dwxgmac2_enable_tx_timestamp(struct dma_desc *p)
0076 {
0077     p->des2 |= cpu_to_le32(XGMAC_TDES2_TTSE);
0078 }
0079
0080 static int dwxgmac2_get_tx_timestamp_status(struct dma_desc *p)
0081 {
0082     return 0; /* Not supported */
0083 }
0084
0085 static inline void dwxgmac2_get_timestamp(void *desc, u32 ats, u64 *ts)
0086 {
0087     struct dma_desc *p = (struct dma_desc *)desc;
0088     u64 ns = 0;
0089
0090     ns += le32_to_cpu(p->des1) * 1000000000ULL;
0091     ns += le32_to_cpu(p->des0);
0092
0093     *ts = ns;
0094 }
0095
0096 static int dwxgmac2_rx_check_timestamp(void *desc)
0097 {
0098     struct dma_desc *p = (struct dma_desc *)desc;
0099     unsigned int rdes3 = le32_to_cpu(p->des3);
0100     bool desc_valid, ts_valid;
0101
0102     dma_rmb();
0103
0104     desc_valid = !(rdes3 & XGMAC_RDES3_OWN) && (rdes3 & XGMAC_RDES3_CTXT);
0105     ts_valid = !(rdes3 & XGMAC_RDES3_TSD) && (rdes3 & XGMAC_RDES3_TSA);
0106
0107     if (likely(desc_valid && ts_valid)) {
0108         if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff))
0109             return -EINVAL;
0110         return 0;
0111     }
0112
0113     return -EINVAL;
0114 }
0115
0116 static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,
0117                         u32 ats)
0118 {
0119     struct dma_desc *p = (struct dma_desc *)desc;
0120     unsigned int rdes3 = le32_to_cpu(p->des3);
0121     int ret = -EBUSY;
0122
0123     if (likely(rdes3 & XGMAC_RDES3_CDA))
0124         ret = dwxgmac2_rx_check_timestamp(next_desc);
0125
0126     return !ret;
0127 }
0128
0129 static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
0130                   int mode, int end, int bfsize)
0131 {
0132     dwxgmac2_set_rx_owner(p, disable_rx_ic);
0133 }
0134
0135 static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end)
0136 {
0137     p->des0 = 0;
0138     p->des1 = 0;
0139     p->des2 = 0;
0140     p->des3 = 0;
0141 }
0142
0143 static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
0144                      bool csum_flag, int mode, bool tx_own,
0145                      bool ls, unsigned int tot_pkt_len)
0146 {
0147     unsigned int tdes3 = le32_to_cpu(p->des3);
0148
0149     p->des2 |= cpu_to_le32(len & XGMAC_TDES2_B1L);
0150
0151     tdes3 |= tot_pkt_len & XGMAC_TDES3_FL;
0152     if (is_fs)
0153         tdes3 |= XGMAC_TDES3_FD;
0154     else
0155         tdes3 &= ~XGMAC_TDES3_FD;
0156
0157     if (csum_flag)
0158         tdes3 |= 0x3 << XGMAC_TDES3_CIC_SHIFT;
0159     else
0160         tdes3 &= ~XGMAC_TDES3_CIC;
0161
0162     if (ls)
0163         tdes3 |= XGMAC_TDES3_LD;
0164     else
0165         tdes3 &= ~XGMAC_TDES3_LD;
0166
0167     /* Finally set the OWN bit. Later the DMA will start! */
0168     if (tx_own)
0169         tdes3 |= XGMAC_TDES3_OWN;
0170
0171     if (is_fs && tx_own)
0172         /* When the own bit, for the first frame, has to be set, all
0173          * descriptors for the same frame has to be set before, to
0174          * avoid race condition.
0175          */
0176         dma_wmb();
0177
0178     p->des3 = cpu_to_le32(tdes3);
0179 }
0180
0181 static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
0182                      int len1, int len2, bool tx_own,
0183                      bool ls, unsigned int tcphdrlen,
0184                      unsigned int tcppayloadlen)
0185 {
0186     unsigned int tdes3 = le32_to_cpu(p->des3);
0187
0188     if (len1)
0189         p->des2 |= cpu_to_le32(len1 & XGMAC_TDES2_B1L);
0190     if (len2)
0191         p->des2 |= cpu_to_le32((len2 << XGMAC_TDES2_B2L_SHIFT) &
0192                 XGMAC_TDES2_B2L);
0193     if (is_fs) {
0194         tdes3 |= XGMAC_TDES3_FD | XGMAC_TDES3_TSE;
0195         tdes3 |= (tcphdrlen << XGMAC_TDES3_THL_SHIFT) &
0196             XGMAC_TDES3_THL;
0197         tdes3 |= tcppayloadlen & XGMAC_TDES3_TPL;
0198     } else {
0199         tdes3 &= ~XGMAC_TDES3_FD;
0200     }
0201
0202     if (ls)
0203         tdes3 |= XGMAC_TDES3_LD;
0204     else
0205         tdes3 &= ~XGMAC_TDES3_LD;
0206
0207     /* Finally set the OWN bit. Later the DMA will start! */
0208     if (tx_own)
0209         tdes3 |= XGMAC_TDES3_OWN;
0210
0211     if (is_fs && tx_own)
0212         /* When the own bit, for the first frame, has to be set, all
0213          * descriptors for the same frame has to be set before, to
0214          * avoid race condition.
0215          */
0216         dma_wmb();
0217
0218     p->des3 = cpu_to_le32(tdes3);
0219 }
0220
0221 static void dwxgmac2_release_tx_desc(struct dma_desc *p, int mode)
0222 {
0223     p->des0 = 0;
0224     p->des1 = 0;
0225     p->des2 = 0;
0226     p->des3 = 0;
0227 }
0228
0229 static void dwxgmac2_set_tx_ic(struct dma_desc *p)
0230 {
0231     p->des2 |= cpu_to_le32(XGMAC_TDES2_IOC);
0232 }
0233
0234 static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)
0235 {
0236     p->des0 = 0;
0237     p->des1 = 0;
0238     p->des2 = cpu_to_le32(mss);
0239     p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV);
0240 }
0241
0242 static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)
0243 {
0244     p->des0 = cpu_to_le32(lower_32_bits(addr));
0245     p->des1 = cpu_to_le32(upper_32_bits(addr));
0246 }
0247
0248 static void dwxgmac2_clear(struct dma_desc *p)
0249 {
0250     p->des0 = 0;
0251     p->des1 = 0;
0252     p->des2 = 0;
0253     p->des3 = 0;
0254 }
0255
0256 static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,
0257                 enum pkt_hash_types *type)
0258 {
0259     unsigned int rdes3 = le32_to_cpu(p->des3);
0260     u32 ptype;
0261
0262     if (rdes3 & XGMAC_RDES3_RSV) {
0263         ptype = (rdes3 & XGMAC_RDES3_L34T) >> XGMAC_RDES3_L34T_SHIFT;
0264
0265         switch (ptype) {
0266         case XGMAC_L34T_IP4TCP:
0267         case XGMAC_L34T_IP4UDP:
0268         case XGMAC_L34T_IP6TCP:
0269         case XGMAC_L34T_IP6UDP:
0270             *type = PKT_HASH_TYPE_L4;
0271             break;
0272         default:
0273             *type = PKT_HASH_TYPE_L3;
0274             break;
0275         }
0276
0277         *hash = le32_to_cpu(p->des1);
0278         return 0;
0279     }
0280
0281     return -EINVAL;
0282 }
0283
0284 static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)
0285 {
0286     if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T)
0287         *len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL;
0288 }
0289
0290 static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid)
0291 {
0292     p->des2 = cpu_to_le32(lower_32_bits(addr));
0293     p->des3 = cpu_to_le32(upper_32_bits(addr));
0294 }
0295
0296 static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type)
0297 {
0298     sarc_type <<= XGMAC_TDES3_SAIC_SHIFT;
0299
0300     p->des3 |= cpu_to_le32(sarc_type & XGMAC_TDES3_SAIC);
0301 }
0302
0303 static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
0304                   u32 inner_type)
0305 {
0306     p->des0 = 0;
0307     p->des1 = 0;
0308     p->des2 = 0;
0309     p->des3 = 0;
0310
0311     /* Inner VLAN */
0312     if (inner_type) {
0313         u32 des = inner_tag << XGMAC_TDES2_IVT_SHIFT;
0314
0315         des &= XGMAC_TDES2_IVT;
0316         p->des2 = cpu_to_le32(des);
0317
0318         des = inner_type << XGMAC_TDES3_IVTIR_SHIFT;
0319         des &= XGMAC_TDES3_IVTIR;
0320         p->des3 = cpu_to_le32(des | XGMAC_TDES3_IVLTV);
0321     }
0322
0323     /* Outer VLAN */
0324     p->des3 |= cpu_to_le32(tag & XGMAC_TDES3_VT);
0325     p->des3 |= cpu_to_le32(XGMAC_TDES3_VLTV);
0326
0327     p->des3 |= cpu_to_le32(XGMAC_TDES3_CTXT);
0328 }
0329
0330 static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type)
0331 {
0332     type <<= XGMAC_TDES2_VTIR_SHIFT;
0333     p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR);
0334 }
0335
0336 static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
0337 {
0338     p->des4 = cpu_to_le32((sec & XGMAC_TDES0_LT) | XGMAC_TDES0_LTV);
0339     p->des5 = cpu_to_le32(nsec & XGMAC_TDES1_LT);
0340     p->des6 = 0;
0341     p->des7 = 0;
0342 }
0343
0344 const struct stmmac_desc_ops dwxgmac210_desc_ops = {
0345     .tx_status = dwxgmac2_get_tx_status,
0346     .rx_status = dwxgmac2_get_rx_status,
0347     .get_tx_len = dwxgmac2_get_tx_len,
0348     .get_tx_owner = dwxgmac2_get_tx_owner,
0349     .set_tx_owner = dwxgmac2_set_tx_owner,
0350     .set_rx_owner = dwxgmac2_set_rx_owner,
0351     .get_tx_ls = dwxgmac2_get_tx_ls,
0352     .get_rx_frame_len = dwxgmac2_get_rx_frame_len,
0353     .enable_tx_timestamp = dwxgmac2_enable_tx_timestamp,
0354     .get_tx_timestamp_status = dwxgmac2_get_tx_timestamp_status,
0355     .get_rx_timestamp_status = dwxgmac2_get_rx_timestamp_status,
0356     .get_timestamp = dwxgmac2_get_timestamp,
0357     .set_tx_ic = dwxgmac2_set_tx_ic,
0358     .prepare_tx_desc = dwxgmac2_prepare_tx_desc,
0359     .prepare_tso_tx_desc = dwxgmac2_prepare_tso_tx_desc,
0360     .release_tx_desc = dwxgmac2_release_tx_desc,
0361     .init_rx_desc = dwxgmac2_init_rx_desc,
0362     .init_tx_desc = dwxgmac2_init_tx_desc,
0363     .set_mss = dwxgmac2_set_mss,
0364     .set_addr = dwxgmac2_set_addr,
0365     .clear = dwxgmac2_clear,
0366     .get_rx_hash = dwxgmac2_get_rx_hash,
0367     .get_rx_header_len = dwxgmac2_get_rx_header_len,
0368     .set_sec_addr = dwxgmac2_set_sec_addr,
0369     .set_sarc = dwxgmac2_set_sarc,
0370     .set_vlan_tag = dwxgmac2_set_vlan_tag,
0371     .set_vlan = dwxgmac2_set_vlan,
0372     .set_tbs = dwxgmac2_set_tbs,
0373 };