stmicro/stmmac/dwmac_lib.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*******************************************************************************
0003   Copyright (C) 2007-2009  STMicroelectronics Ltd
0004
0005
0006   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0007 *******************************************************************************/
0008
0009 #include <linux/io.h>
0010 #include <linux/iopoll.h>
0011 #include "common.h"
0012 #include "dwmac_dma.h"
0013
0014 #define GMAC_HI_REG_AE      0x80000000
0015
0016 int dwmac_dma_reset(void __iomem *ioaddr)
0017 {
0018     u32 value = readl(ioaddr + DMA_BUS_MODE);
0019
0020     /* DMA SW reset */
0021     value |= DMA_BUS_MODE_SFT_RESET;
0022     writel(value, ioaddr + DMA_BUS_MODE);
0023
0024     return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
0025                  !(value & DMA_BUS_MODE_SFT_RESET),
0026                  10000, 200000);
0027 }
0028
0029 /* CSR1 enables the transmit DMA to check for new descriptor */
0030 void dwmac_enable_dma_transmission(void __iomem *ioaddr)
0031 {
0032     writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
0033 }
0034
0035 void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
0036 {
0037     u32 value = readl(ioaddr + DMA_INTR_ENA);
0038
0039     if (rx)
0040         value |= DMA_INTR_DEFAULT_RX;
0041     if (tx)
0042         value |= DMA_INTR_DEFAULT_TX;
0043
0044     writel(value, ioaddr + DMA_INTR_ENA);
0045 }
0046
0047 void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx)
0048 {
0049     u32 value = readl(ioaddr + DMA_INTR_ENA);
0050
0051     if (rx)
0052         value &= ~DMA_INTR_DEFAULT_RX;
0053     if (tx)
0054         value &= ~DMA_INTR_DEFAULT_TX;
0055
0056     writel(value, ioaddr + DMA_INTR_ENA);
0057 }
0058
0059 void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
0060 {
0061     u32 value = readl(ioaddr + DMA_CONTROL);
0062     value |= DMA_CONTROL_ST;
0063     writel(value, ioaddr + DMA_CONTROL);
0064 }
0065
0066 void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
0067 {
0068     u32 value = readl(ioaddr + DMA_CONTROL);
0069     value &= ~DMA_CONTROL_ST;
0070     writel(value, ioaddr + DMA_CONTROL);
0071 }
0072
0073 void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
0074 {
0075     u32 value = readl(ioaddr + DMA_CONTROL);
0076     value |= DMA_CONTROL_SR;
0077     writel(value, ioaddr + DMA_CONTROL);
0078 }
0079
0080 void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
0081 {
0082     u32 value = readl(ioaddr + DMA_CONTROL);
0083     value &= ~DMA_CONTROL_SR;
0084     writel(value, ioaddr + DMA_CONTROL);
0085 }
0086
0087 #ifdef DWMAC_DMA_DEBUG
0088 static void show_tx_process_state(unsigned int status)
0089 {
0090     unsigned int state;
0091     state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
0092
0093     switch (state) {
0094     case 0:
0095         pr_debug("- TX (Stopped): Reset or Stop command\n");
0096         break;
0097     case 1:
0098         pr_debug("- TX (Running): Fetching the Tx desc\n");
0099         break;
0100     case 2:
0101         pr_debug("- TX (Running): Waiting for end of tx\n");
0102         break;
0103     case 3:
0104         pr_debug("- TX (Running): Reading the data "
0105                "and queuing the data into the Tx buf\n");
0106         break;
0107     case 6:
0108         pr_debug("- TX (Suspended): Tx Buff Underflow "
0109                "or an unavailable Transmit descriptor\n");
0110         break;
0111     case 7:
0112         pr_debug("- TX (Running): Closing Tx descriptor\n");
0113         break;
0114     default:
0115         break;
0116     }
0117 }
0118
0119 static void show_rx_process_state(unsigned int status)
0120 {
0121     unsigned int state;
0122     state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
0123
0124     switch (state) {
0125     case 0:
0126         pr_debug("- RX (Stopped): Reset or Stop command\n");
0127         break;
0128     case 1:
0129         pr_debug("- RX (Running): Fetching the Rx desc\n");
0130         break;
0131     case 2:
0132         pr_debug("- RX (Running): Checking for end of pkt\n");
0133         break;
0134     case 3:
0135         pr_debug("- RX (Running): Waiting for Rx pkt\n");
0136         break;
0137     case 4:
0138         pr_debug("- RX (Suspended): Unavailable Rx buf\n");
0139         break;
0140     case 5:
0141         pr_debug("- RX (Running): Closing Rx descriptor\n");
0142         break;
0143     case 6:
0144         pr_debug("- RX(Running): Flushing the current frame"
0145                " from the Rx buf\n");
0146         break;
0147     case 7:
0148         pr_debug("- RX (Running): Queuing the Rx frame"
0149                " from the Rx buf into memory\n");
0150         break;
0151     default:
0152         break;
0153     }
0154 }
0155 #endif
0156
0157 int dwmac_dma_interrupt(void __iomem *ioaddr,
0158             struct stmmac_extra_stats *x, u32 chan, u32 dir)
0159 {
0160     int ret = 0;
0161     /* read the status register (CSR5) */
0162     u32 intr_status = readl(ioaddr + DMA_STATUS);
0163
0164 #ifdef DWMAC_DMA_DEBUG
0165     /* Enable it to monitor DMA rx/tx status in case of critical problems */
0166     pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status);
0167     show_tx_process_state(intr_status);
0168     show_rx_process_state(intr_status);
0169 #endif
0170
0171     if (dir == DMA_DIR_RX)
0172         intr_status &= DMA_STATUS_MSK_RX;
0173     else if (dir == DMA_DIR_TX)
0174         intr_status &= DMA_STATUS_MSK_TX;
0175
0176     /* ABNORMAL interrupts */
0177     if (unlikely(intr_status & DMA_STATUS_AIS)) {
0178         if (unlikely(intr_status & DMA_STATUS_UNF)) {
0179             ret = tx_hard_error_bump_tc;
0180             x->tx_undeflow_irq++;
0181         }
0182         if (unlikely(intr_status & DMA_STATUS_TJT))
0183             x->tx_jabber_irq++;
0184
0185         if (unlikely(intr_status & DMA_STATUS_OVF))
0186             x->rx_overflow_irq++;
0187
0188         if (unlikely(intr_status & DMA_STATUS_RU))
0189             x->rx_buf_unav_irq++;
0190         if (unlikely(intr_status & DMA_STATUS_RPS))
0191             x->rx_process_stopped_irq++;
0192         if (unlikely(intr_status & DMA_STATUS_RWT))
0193             x->rx_watchdog_irq++;
0194         if (unlikely(intr_status & DMA_STATUS_ETI))
0195             x->tx_early_irq++;
0196         if (unlikely(intr_status & DMA_STATUS_TPS)) {
0197             x->tx_process_stopped_irq++;
0198             ret = tx_hard_error;
0199         }
0200         if (unlikely(intr_status & DMA_STATUS_FBI)) {
0201             x->fatal_bus_error_irq++;
0202             ret = tx_hard_error;
0203         }
0204     }
0205     /* TX/RX NORMAL interrupts */
0206     if (likely(intr_status & DMA_STATUS_NIS)) {
0207         x->normal_irq_n++;
0208         if (likely(intr_status & DMA_STATUS_RI)) {
0209             u32 value = readl(ioaddr + DMA_INTR_ENA);
0210             /* to schedule NAPI on real RIE event. */
0211             if (likely(value & DMA_INTR_ENA_RIE)) {
0212                 x->rx_normal_irq_n++;
0213                 ret |= handle_rx;
0214             }
0215         }
0216         if (likely(intr_status & DMA_STATUS_TI)) {
0217             x->tx_normal_irq_n++;
0218             ret |= handle_tx;
0219         }
0220         if (unlikely(intr_status & DMA_STATUS_ERI))
0221             x->rx_early_irq++;
0222     }
0223     /* Optional hardware blocks, interrupts should be disabled */
0224     if (unlikely(intr_status &
0225              (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
0226         pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
0227
0228     /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
0229     writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
0230
0231     return ret;
0232 }
0233
0234 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
0235 {
0236     u32 csr6 = readl(ioaddr + DMA_CONTROL);
0237     writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
0238
0239     do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
0240 }
0241
0242 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
0243              unsigned int high, unsigned int low)
0244 {
0245     unsigned long data;
0246
0247     data = (addr[5] << 8) | addr[4];
0248     /* For MAC Addr registers we have to set the Address Enable (AE)
0249      * bit that has no effect on the High Reg 0 where the bit 31 (MO)
0250      * is RO.
0251      */
0252     writel(data | GMAC_HI_REG_AE, ioaddr + high);
0253     data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
0254     writel(data, ioaddr + low);
0255 }
0256 EXPORT_SYMBOL_GPL(stmmac_set_mac_addr);
0257
0258 /* Enable disable MAC RX/TX */
0259 void stmmac_set_mac(void __iomem *ioaddr, bool enable)
0260 {
0261     u32 old_val, value;
0262
0263     old_val = readl(ioaddr + MAC_CTRL_REG);
0264     value = old_val;
0265
0266     if (enable)
0267         value |= MAC_ENABLE_RX | MAC_ENABLE_TX;
0268     else
0269         value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX);
0270
0271     if (value != old_val)
0272         writel(value, ioaddr + MAC_CTRL_REG);
0273 }
0274
0275 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
0276              unsigned int high, unsigned int low)
0277 {
0278     unsigned int hi_addr, lo_addr;
0279
0280     /* Read the MAC address from the hardware */
0281     hi_addr = readl(ioaddr + high);
0282     lo_addr = readl(ioaddr + low);
0283
0284     /* Extract the MAC address from the high and low words */
0285     addr[0] = lo_addr & 0xff;
0286     addr[1] = (lo_addr >> 8) & 0xff;
0287     addr[2] = (lo_addr >> 16) & 0xff;
0288     addr[3] = (lo_addr >> 24) & 0xff;
0289     addr[4] = hi_addr & 0xff;
0290     addr[5] = (hi_addr >> 8) & 0xff;
0291 }
0292 EXPORT_SYMBOL_GPL(stmmac_get_mac_addr);