stmicro/stmmac/dwmac_dma.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*******************************************************************************
0003   DWMAC DMA Header file.
0004
0005   Copyright (C) 2007-2009  STMicroelectronics Ltd
0006
0007
0008   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0009 *******************************************************************************/
0010
0011 #ifndef __DWMAC_DMA_H__
0012 #define __DWMAC_DMA_H__
0013
0014 /* DMA CRS Control and Status Register Mapping */
0015 #define DMA_BUS_MODE        0x00001000  /* Bus Mode */
0016 #define DMA_XMT_POLL_DEMAND 0x00001004  /* Transmit Poll Demand */
0017 #define DMA_RCV_POLL_DEMAND 0x00001008  /* Received Poll Demand */
0018 #define DMA_RCV_BASE_ADDR   0x0000100c  /* Receive List Base */
0019 #define DMA_TX_BASE_ADDR    0x00001010  /* Transmit List Base */
0020 #define DMA_STATUS      0x00001014  /* Status Register */
0021 #define DMA_CONTROL     0x00001018  /* Ctrl (Operational Mode) */
0022 #define DMA_INTR_ENA        0x0000101c  /* Interrupt Enable */
0023 #define DMA_MISSED_FRAME_CTR    0x00001020  /* Missed Frame Counter */
0024
0025 /* SW Reset */
0026 #define DMA_BUS_MODE_SFT_RESET  0x00000001  /* Software Reset */
0027
0028 /* Rx watchdog register */
0029 #define DMA_RX_WATCHDOG     0x00001024
0030
0031 /* AXI Master Bus Mode */
0032 #define DMA_AXI_BUS_MODE    0x00001028
0033
0034 #define DMA_AXI_EN_LPI      BIT(31)
0035 #define DMA_AXI_LPI_XIT_FRM BIT(30)
0036 #define DMA_AXI_WR_OSR_LMT  GENMASK(23, 20)
0037 #define DMA_AXI_WR_OSR_LMT_SHIFT    20
0038 #define DMA_AXI_WR_OSR_LMT_MASK 0xf
0039 #define DMA_AXI_RD_OSR_LMT  GENMASK(19, 16)
0040 #define DMA_AXI_RD_OSR_LMT_SHIFT    16
0041 #define DMA_AXI_RD_OSR_LMT_MASK 0xf
0042
0043 #define DMA_AXI_OSR_MAX     0xf
0044 #define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
0045                    (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
0046 #define DMA_AXI_1KBBE       BIT(13)
0047 #define DMA_AXI_AAL     BIT(12)
0048 #define DMA_AXI_BLEN256     BIT(7)
0049 #define DMA_AXI_BLEN128     BIT(6)
0050 #define DMA_AXI_BLEN64      BIT(5)
0051 #define DMA_AXI_BLEN32      BIT(4)
0052 #define DMA_AXI_BLEN16      BIT(3)
0053 #define DMA_AXI_BLEN8       BIT(2)
0054 #define DMA_AXI_BLEN4       BIT(1)
0055 #define DMA_BURST_LEN_DEFAULT   (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
0056                  DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
0057                  DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
0058                  DMA_AXI_BLEN4)
0059
0060 #define DMA_AXI_UNDEF       BIT(0)
0061
0062 #define DMA_AXI_BURST_LEN_MASK  0x000000FE
0063
0064 #define DMA_CUR_TX_BUF_ADDR 0x00001050  /* Current Host Tx Buffer */
0065 #define DMA_CUR_RX_BUF_ADDR 0x00001054  /* Current Host Rx Buffer */
0066 #define DMA_HW_FEATURE      0x00001058  /* HW Feature Register */
0067
0068 /* DMA Control register defines */
0069 #define DMA_CONTROL_ST      0x00002000  /* Start/Stop Transmission */
0070 #define DMA_CONTROL_SR      0x00000002  /* Start/Stop Receive */
0071
0072 /* DMA Normal interrupt */
0073 #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
0074 #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
0075 #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
0076 #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
0077 #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
0078
0079 #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
0080             DMA_INTR_ENA_TIE)
0081
0082 /* DMA Abnormal interrupt */
0083 #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
0084 #define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
0085 #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
0086 #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
0087 #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
0088 #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
0089 #define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
0090 #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
0091 #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
0092 #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
0093
0094 #define DMA_INTR_ABNORMAL   (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
0095                 DMA_INTR_ENA_UNE)
0096
0097 /* DMA default interrupt mask */
0098 #define DMA_INTR_DEFAULT_MASK   (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
0099 #define DMA_INTR_DEFAULT_RX (DMA_INTR_ENA_RIE)
0100 #define DMA_INTR_DEFAULT_TX (DMA_INTR_ENA_TIE)
0101
0102 /* DMA Status register defines */
0103 #define DMA_STATUS_GLPII    0x40000000  /* GMAC LPI interrupt */
0104 #define DMA_STATUS_GPI      0x10000000  /* PMT interrupt */
0105 #define DMA_STATUS_GMI      0x08000000  /* MMC interrupt */
0106 #define DMA_STATUS_GLI      0x04000000  /* GMAC Line interface int */
0107 #define DMA_STATUS_EB_MASK  0x00380000  /* Error Bits Mask */
0108 #define DMA_STATUS_EB_TX_ABORT  0x00080000  /* Error Bits - TX Abort */
0109 #define DMA_STATUS_EB_RX_ABORT  0x00100000  /* Error Bits - RX Abort */
0110 #define DMA_STATUS_TS_MASK  0x00700000  /* Transmit Process State */
0111 #define DMA_STATUS_TS_SHIFT 20
0112 #define DMA_STATUS_RS_MASK  0x000e0000  /* Receive Process State */
0113 #define DMA_STATUS_RS_SHIFT 17
0114 #define DMA_STATUS_NIS  0x00010000  /* Normal Interrupt Summary */
0115 #define DMA_STATUS_AIS  0x00008000  /* Abnormal Interrupt Summary */
0116 #define DMA_STATUS_ERI  0x00004000  /* Early Receive Interrupt */
0117 #define DMA_STATUS_FBI  0x00002000  /* Fatal Bus Error Interrupt */
0118 #define DMA_STATUS_ETI  0x00000400  /* Early Transmit Interrupt */
0119 #define DMA_STATUS_RWT  0x00000200  /* Receive Watchdog Timeout */
0120 #define DMA_STATUS_RPS  0x00000100  /* Receive Process Stopped */
0121 #define DMA_STATUS_RU   0x00000080  /* Receive Buffer Unavailable */
0122 #define DMA_STATUS_RI   0x00000040  /* Receive Interrupt */
0123 #define DMA_STATUS_UNF  0x00000020  /* Transmit Underflow */
0124 #define DMA_STATUS_OVF  0x00000010  /* Receive Overflow */
0125 #define DMA_STATUS_TJT  0x00000008  /* Transmit Jabber Timeout */
0126 #define DMA_STATUS_TU   0x00000004  /* Transmit Buffer Unavailable */
0127 #define DMA_STATUS_TPS  0x00000002  /* Transmit Process Stopped */
0128 #define DMA_STATUS_TI   0x00000001  /* Transmit Interrupt */
0129 #define DMA_CONTROL_FTF     0x00100000  /* Flush transmit FIFO */
0130
0131 #define DMA_STATUS_MSK_COMMON       (DMA_STATUS_NIS | \
0132                      DMA_STATUS_AIS | \
0133                      DMA_STATUS_FBI)
0134
0135 #define DMA_STATUS_MSK_RX       (DMA_STATUS_ERI | \
0136                      DMA_STATUS_RWT | \
0137                      DMA_STATUS_RPS | \
0138                      DMA_STATUS_RU | \
0139                      DMA_STATUS_RI | \
0140                      DMA_STATUS_OVF | \
0141                      DMA_STATUS_MSK_COMMON)
0142
0143 #define DMA_STATUS_MSK_TX       (DMA_STATUS_ETI | \
0144                      DMA_STATUS_UNF | \
0145                      DMA_STATUS_TJT | \
0146                      DMA_STATUS_TU | \
0147                      DMA_STATUS_TPS | \
0148                      DMA_STATUS_TI | \
0149                      DMA_STATUS_MSK_COMMON)
0150
0151 #define NUM_DWMAC100_DMA_REGS   9
0152 #define NUM_DWMAC1000_DMA_REGS  23
0153 #define NUM_DWMAC4_DMA_REGS 27
0154
0155 void dwmac_enable_dma_transmission(void __iomem *ioaddr);
0156 void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
0157 void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
0158 void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan);
0159 void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan);
0160 void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan);
0161 void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan);
0162 int dwmac_dma_interrupt(void __iomem *ioaddr, struct stmmac_extra_stats *x,
0163             u32 chan, u32 dir);
0164 int dwmac_dma_reset(void __iomem *ioaddr);
0165
0166 #endif /* __DWMAC_DMA_H__ */