stmicro/stmmac/dwmac5.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
0002 // Copyright (c) 2017 Synopsys, Inc. and/or its affiliates.
0003 // stmmac Support for 5.xx Ethernet QoS cores
0004
0005 #ifndef __DWMAC5_H__
0006 #define __DWMAC5_H__
0007
0008 #define MAC_DPP_FSM_INT_STATUS      0x00000140
0009 #define MAC_AXI_SLV_DPE_ADDR_STATUS 0x00000144
0010 #define MAC_FSM_CONTROL         0x00000148
0011 #define PRTYEN              BIT(1)
0012 #define TMOUTEN             BIT(0)
0013
0014 #define MAC_FPE_CTRL_STS        0x00000234
0015 #define TRSP                BIT(19)
0016 #define TVER                BIT(18)
0017 #define RRSP                BIT(17)
0018 #define RVER                BIT(16)
0019 #define SRSP                BIT(2)
0020 #define SVER                BIT(1)
0021 #define EFPE                BIT(0)
0022
0023 #define MAC_PPS_CONTROL         0x00000b70
0024 #define PPS_MAXIDX(x)           ((((x) + 1) * 8) - 1)
0025 #define PPS_MINIDX(x)           ((x) * 8)
0026 #define PPSx_MASK(x)            GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x))
0027 #define MCGRENx(x)          BIT(PPS_MAXIDX(x))
0028 #define TRGTMODSELx(x, val)     \
0029     GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) & \
0030     ((val) << (PPS_MAXIDX(x) - 2))
0031 #define PPSCMDx(x, val)         \
0032     GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) & \
0033     ((val) << PPS_MINIDX(x))
0034 #define PPSEN0              BIT(4)
0035 #define MAC_PPSx_TARGET_TIME_SEC(x) (0x00000b80 + ((x) * 0x10))
0036 #define MAC_PPSx_TARGET_TIME_NSEC(x)    (0x00000b84 + ((x) * 0x10))
0037 #define TRGTBUSY0           BIT(31)
0038 #define TTSL0               GENMASK(30, 0)
0039 #define MAC_PPSx_INTERVAL(x)        (0x00000b88 + ((x) * 0x10))
0040 #define MAC_PPSx_WIDTH(x)       (0x00000b8c + ((x) * 0x10))
0041
0042 #define MTL_EST_CONTROL         0x00000c50
0043 #define PTOV                GENMASK(31, 24)
0044 #define PTOV_SHIFT          24
0045 #define SSWL                BIT(1)
0046 #define EEST                BIT(0)
0047
0048 #define MTL_EST_STATUS          0x00000c58
0049 #define BTRL                GENMASK(11, 8)
0050 #define BTRL_SHIFT          8
0051 #define BTRL_MAX            (0xF << BTRL_SHIFT)
0052 #define SWOL                BIT(7)
0053 #define SWOL_SHIFT          7
0054 #define CGCE                BIT(4)
0055 #define HLBS                BIT(3)
0056 #define HLBF                BIT(2)
0057 #define BTRE                BIT(1)
0058 #define SWLC                BIT(0)
0059
0060 #define MTL_EST_SCH_ERR         0x00000c60
0061 #define MTL_EST_FRM_SZ_ERR      0x00000c64
0062 #define MTL_EST_FRM_SZ_CAP      0x00000c68
0063 #define SZ_CAP_HBFS_MASK        GENMASK(14, 0)
0064 #define SZ_CAP_HBFQ_SHIFT       16
0065 #define SZ_CAP_HBFQ_MASK(_val)      ({ typeof(_val) (val) = (_val); \
0066                     ((val) > 4 ? GENMASK(18, 16) :  \
0067                      (val) > 2 ? GENMASK(17, 16) :  \
0068                      BIT(16)); })
0069
0070 #define MTL_EST_INT_EN          0x00000c70
0071 #define IECGCE              CGCE
0072 #define IEHS                HLBS
0073 #define IEHF                HLBF
0074 #define IEBE                BTRE
0075 #define IECC                SWLC
0076
0077 #define MTL_EST_GCL_CONTROL     0x00000c80
0078 #define BTR_LOW             0x0
0079 #define BTR_HIGH            0x1
0080 #define CTR_LOW             0x2
0081 #define CTR_HIGH            0x3
0082 #define TER             0x4
0083 #define LLR             0x5
0084 #define ADDR_SHIFT          8
0085 #define GCRR                BIT(2)
0086 #define SRWO                BIT(0)
0087 #define MTL_EST_GCL_DATA        0x00000c84
0088
0089 #define MTL_RXP_CONTROL_STATUS      0x00000ca0
0090 #define RXPI                BIT(31)
0091 #define NPE             GENMASK(23, 16)
0092 #define NVE             GENMASK(7, 0)
0093 #define MTL_RXP_IACC_CTRL_STATUS    0x00000cb0
0094 #define STARTBUSY           BIT(31)
0095 #define RXPEIEC             GENMASK(22, 21)
0096 #define RXPEIEE             BIT(20)
0097 #define WRRDN               BIT(16)
0098 #define ADDR                GENMASK(15, 0)
0099 #define MTL_RXP_IACC_DATA       0x00000cb4
0100 #define MTL_ECC_CONTROL         0x00000cc0
0101 #define MEEAO               BIT(8)
0102 #define TSOEE               BIT(4)
0103 #define MRXPEE              BIT(3)
0104 #define MESTEE              BIT(2)
0105 #define MRXEE               BIT(1)
0106 #define MTXEE               BIT(0)
0107
0108 #define MTL_SAFETY_INT_STATUS       0x00000cc4
0109 #define MCSIS               BIT(31)
0110 #define MEUIS               BIT(1)
0111 #define MECIS               BIT(0)
0112 #define MTL_ECC_INT_ENABLE      0x00000cc8
0113 #define RPCEIE              BIT(12)
0114 #define ECEIE               BIT(8)
0115 #define RXCEIE              BIT(4)
0116 #define TXCEIE              BIT(0)
0117 #define MTL_ECC_INT_STATUS      0x00000ccc
0118 #define MTL_DPP_CONTROL         0x00000ce0
0119 #define EPSI                BIT(2)
0120 #define OPE             BIT(1)
0121 #define EDPP                BIT(0)
0122
0123 #define DMA_SAFETY_INT_STATUS       0x00001080
0124 #define MSUIS               BIT(29)
0125 #define MSCIS               BIT(28)
0126 #define DEUIS               BIT(1)
0127 #define DECIS               BIT(0)
0128 #define DMA_ECC_INT_ENABLE      0x00001084
0129 #define TCEIE               BIT(0)
0130 #define DMA_ECC_INT_STATUS      0x00001088
0131
0132 /* EQoS version 5.xx VLAN Tag Filter Fail Packets Queuing */
0133 #define GMAC_RXQ_CTRL4          0x00000094
0134 #define GMAC_RXQCTRL_VFFQ_MASK      GENMASK(19, 17)
0135 #define GMAC_RXQCTRL_VFFQ_SHIFT     17
0136 #define GMAC_RXQCTRL_VFFQE      BIT(16)
0137
0138 #define GMAC_INT_FPE_EN         BIT(17)
0139
0140 int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp,
0141                   struct stmmac_safety_feature_cfg *safety_cfg);
0142 int dwmac5_safety_feat_irq_status(struct net_device *ndev,
0143         void __iomem *ioaddr, unsigned int asp,
0144         struct stmmac_safety_stats *stats);
0145 int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,
0146             int index, unsigned long *count, const char **desc);
0147 int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,
0148               unsigned int count);
0149 int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,
0150                struct stmmac_pps_cfg *cfg, bool enable,
0151                u32 sub_second_inc, u32 systime_flags);
0152 int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
0153              unsigned int ptp_rate);
0154 void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
0155                struct stmmac_extra_stats *x, u32 txqcnt);
0156 void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
0157               bool enable);
0158 void dwmac5_fpe_send_mpacket(void __iomem *ioaddr,
0159                  enum stmmac_mpacket_type type);
0160 int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev);
0161
0162 #endif /* __DWMAC5_H__ */