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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
0004  * DWC Ether MAC version 4.xx  has been used for  developing this code.
0005  *
0006  * This contains the functions to handle the dma.
0007  *
0008  * Copyright (C) 2015  STMicroelectronics Ltd
0009  *
0010  * Author: Alexandre Torgue <alexandre.torgue@st.com>
0011  */
0012 
0013 #include <linux/io.h>
0014 #include "dwmac4.h"
0015 #include "dwmac4_dma.h"
0016 
0017 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
0018 {
0019     u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
0020     int i;
0021 
0022     pr_info("dwmac4: Master AXI performs %s burst length\n",
0023         (value & DMA_SYS_BUS_FB) ? "fixed" : "any");
0024 
0025     if (axi->axi_lpi_en)
0026         value |= DMA_AXI_EN_LPI;
0027     if (axi->axi_xit_frm)
0028         value |= DMA_AXI_LPI_XIT_FRM;
0029 
0030     value &= ~DMA_AXI_WR_OSR_LMT;
0031     value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
0032          DMA_AXI_WR_OSR_LMT_SHIFT;
0033 
0034     value &= ~DMA_AXI_RD_OSR_LMT;
0035     value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
0036          DMA_AXI_RD_OSR_LMT_SHIFT;
0037 
0038     /* Depending on the UNDEF bit the Master AXI will perform any burst
0039      * length according to the BLEN programmed (by default all BLEN are
0040      * set).
0041      */
0042     for (i = 0; i < AXI_BLEN; i++) {
0043         switch (axi->axi_blen[i]) {
0044         case 256:
0045             value |= DMA_AXI_BLEN256;
0046             break;
0047         case 128:
0048             value |= DMA_AXI_BLEN128;
0049             break;
0050         case 64:
0051             value |= DMA_AXI_BLEN64;
0052             break;
0053         case 32:
0054             value |= DMA_AXI_BLEN32;
0055             break;
0056         case 16:
0057             value |= DMA_AXI_BLEN16;
0058             break;
0059         case 8:
0060             value |= DMA_AXI_BLEN8;
0061             break;
0062         case 4:
0063             value |= DMA_AXI_BLEN4;
0064             break;
0065         }
0066     }
0067 
0068     writel(value, ioaddr + DMA_SYS_BUS_MODE);
0069 }
0070 
0071 static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
0072                     struct stmmac_dma_cfg *dma_cfg,
0073                     dma_addr_t dma_rx_phy, u32 chan)
0074 {
0075     u32 value;
0076     u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
0077 
0078     value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
0079     value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
0080     writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
0081 
0082     if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
0083         writel(upper_32_bits(dma_rx_phy),
0084                ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan));
0085 
0086     writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
0087 }
0088 
0089 static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
0090                     struct stmmac_dma_cfg *dma_cfg,
0091                     dma_addr_t dma_tx_phy, u32 chan)
0092 {
0093     u32 value;
0094     u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
0095 
0096     value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
0097     value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);
0098 
0099     /* Enable OSP to get best performance */
0100     value |= DMA_CONTROL_OSP;
0101 
0102     writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
0103 
0104     if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
0105         writel(upper_32_bits(dma_tx_phy),
0106                ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan));
0107 
0108     writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
0109 }
0110 
0111 static void dwmac4_dma_init_channel(void __iomem *ioaddr,
0112                     struct stmmac_dma_cfg *dma_cfg, u32 chan)
0113 {
0114     u32 value;
0115 
0116     /* common channel control register config */
0117     value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
0118     if (dma_cfg->pblx8)
0119         value = value | DMA_BUS_MODE_PBL;
0120     writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
0121 
0122     /* Mask interrupts by writing to CSR7 */
0123     writel(DMA_CHAN_INTR_DEFAULT_MASK,
0124            ioaddr + DMA_CHAN_INTR_ENA(chan));
0125 }
0126 
0127 static void dwmac410_dma_init_channel(void __iomem *ioaddr,
0128                       struct stmmac_dma_cfg *dma_cfg, u32 chan)
0129 {
0130     u32 value;
0131 
0132     /* common channel control register config */
0133     value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
0134     if (dma_cfg->pblx8)
0135         value = value | DMA_BUS_MODE_PBL;
0136 
0137     writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
0138 
0139     /* Mask interrupts by writing to CSR7 */
0140     writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
0141            ioaddr + DMA_CHAN_INTR_ENA(chan));
0142 }
0143 
0144 static void dwmac4_dma_init(void __iomem *ioaddr,
0145                 struct stmmac_dma_cfg *dma_cfg, int atds)
0146 {
0147     u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
0148 
0149     /* Set the Fixed burst mode */
0150     if (dma_cfg->fixed_burst)
0151         value |= DMA_SYS_BUS_FB;
0152 
0153     /* Mixed Burst has no effect when fb is set */
0154     if (dma_cfg->mixed_burst)
0155         value |= DMA_SYS_BUS_MB;
0156 
0157     if (dma_cfg->aal)
0158         value |= DMA_SYS_BUS_AAL;
0159 
0160     if (dma_cfg->eame)
0161         value |= DMA_SYS_BUS_EAME;
0162 
0163     writel(value, ioaddr + DMA_SYS_BUS_MODE);
0164 
0165     value = readl(ioaddr + DMA_BUS_MODE);
0166 
0167     if (dma_cfg->multi_msi_en) {
0168         value &= ~DMA_BUS_MODE_INTM_MASK;
0169         value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT);
0170     }
0171 
0172     if (dma_cfg->dche)
0173         value |= DMA_BUS_MODE_DCHE;
0174 
0175     writel(value, ioaddr + DMA_BUS_MODE);
0176 
0177 }
0178 
0179 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
0180                   u32 *reg_space)
0181 {
0182     reg_space[DMA_CHAN_CONTROL(channel) / 4] =
0183         readl(ioaddr + DMA_CHAN_CONTROL(channel));
0184     reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
0185         readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
0186     reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
0187         readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
0188     reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
0189         readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
0190     reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
0191         readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
0192     reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
0193         readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
0194     reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
0195         readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
0196     reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
0197         readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
0198     reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
0199         readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
0200     reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
0201         readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
0202     reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
0203         readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
0204     reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
0205         readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
0206     reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
0207         readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
0208     reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
0209         readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
0210     reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
0211         readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
0212     reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
0213         readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
0214     reg_space[DMA_CHAN_STATUS(channel) / 4] =
0215         readl(ioaddr + DMA_CHAN_STATUS(channel));
0216 }
0217 
0218 static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
0219 {
0220     int i;
0221 
0222     for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
0223         _dwmac4_dump_dma_regs(ioaddr, i, reg_space);
0224 }
0225 
0226 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 queue)
0227 {
0228     writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue));
0229 }
0230 
0231 static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
0232                        u32 channel, int fifosz, u8 qmode)
0233 {
0234     unsigned int rqs = fifosz / 256 - 1;
0235     u32 mtl_rx_op;
0236 
0237     mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
0238 
0239     if (mode == SF_DMA_MODE) {
0240         pr_debug("GMAC: enable RX store and forward mode\n");
0241         mtl_rx_op |= MTL_OP_MODE_RSF;
0242     } else {
0243         pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
0244         mtl_rx_op &= ~MTL_OP_MODE_RSF;
0245         mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
0246         if (mode <= 32)
0247             mtl_rx_op |= MTL_OP_MODE_RTC_32;
0248         else if (mode <= 64)
0249             mtl_rx_op |= MTL_OP_MODE_RTC_64;
0250         else if (mode <= 96)
0251             mtl_rx_op |= MTL_OP_MODE_RTC_96;
0252         else
0253             mtl_rx_op |= MTL_OP_MODE_RTC_128;
0254     }
0255 
0256     mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
0257     mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;
0258 
0259     /* Enable flow control only if each channel gets 4 KiB or more FIFO and
0260      * only if channel is not an AVB channel.
0261      */
0262     if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
0263         unsigned int rfd, rfa;
0264 
0265         mtl_rx_op |= MTL_OP_MODE_EHFC;
0266 
0267         /* Set Threshold for Activating Flow Control to min 2 frames,
0268          * i.e. 1500 * 2 = 3000 bytes.
0269          *
0270          * Set Threshold for Deactivating Flow Control to min 1 frame,
0271          * i.e. 1500 bytes.
0272          */
0273         switch (fifosz) {
0274         case 4096:
0275             /* This violates the above formula because of FIFO size
0276              * limit therefore overflow may occur in spite of this.
0277              */
0278             rfd = 0x03; /* Full-2.5K */
0279             rfa = 0x01; /* Full-1.5K */
0280             break;
0281 
0282         default:
0283             rfd = 0x07; /* Full-4.5K */
0284             rfa = 0x04; /* Full-3K */
0285             break;
0286         }
0287 
0288         mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
0289         mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;
0290 
0291         mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
0292         mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;
0293     }
0294 
0295     writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
0296 }
0297 
0298 static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
0299                        u32 channel, int fifosz, u8 qmode)
0300 {
0301     u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
0302     unsigned int tqs = fifosz / 256 - 1;
0303 
0304     if (mode == SF_DMA_MODE) {
0305         pr_debug("GMAC: enable TX store and forward mode\n");
0306         /* Transmit COE type 2 cannot be done in cut-through mode. */
0307         mtl_tx_op |= MTL_OP_MODE_TSF;
0308     } else {
0309         pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
0310         mtl_tx_op &= ~MTL_OP_MODE_TSF;
0311         mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
0312         /* Set the transmit threshold */
0313         if (mode <= 32)
0314             mtl_tx_op |= MTL_OP_MODE_TTC_32;
0315         else if (mode <= 64)
0316             mtl_tx_op |= MTL_OP_MODE_TTC_64;
0317         else if (mode <= 96)
0318             mtl_tx_op |= MTL_OP_MODE_TTC_96;
0319         else if (mode <= 128)
0320             mtl_tx_op |= MTL_OP_MODE_TTC_128;
0321         else if (mode <= 192)
0322             mtl_tx_op |= MTL_OP_MODE_TTC_192;
0323         else if (mode <= 256)
0324             mtl_tx_op |= MTL_OP_MODE_TTC_256;
0325         else if (mode <= 384)
0326             mtl_tx_op |= MTL_OP_MODE_TTC_384;
0327         else
0328             mtl_tx_op |= MTL_OP_MODE_TTC_512;
0329     }
0330     /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
0331      * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
0332      * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
0333      * with reset values: TXQEN off, TQS 256 bytes.
0334      *
0335      * TXQEN must be written for multi-channel operation and TQS must
0336      * reflect the available fifo size per queue (total fifo size / number
0337      * of enabled queues).
0338      */
0339     mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
0340     if (qmode != MTL_QUEUE_AVB)
0341         mtl_tx_op |= MTL_OP_MODE_TXQEN;
0342     else
0343         mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
0344     mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
0345     mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;
0346 
0347     writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
0348 }
0349 
0350 static int dwmac4_get_hw_feature(void __iomem *ioaddr,
0351                  struct dma_features *dma_cap)
0352 {
0353     u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
0354 
0355     /*  MAC HW feature0 */
0356     dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
0357     dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
0358     dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
0359     dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
0360     dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
0361     dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
0362     dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
0363     dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
0364     dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
0365     /* MMC */
0366     dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
0367     /* IEEE 1588-2008 */
0368     dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
0369     /* 802.3az - Energy-Efficient Ethernet (EEE) */
0370     dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
0371     /* TX and RX csum */
0372     dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
0373     dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
0374     dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
0375     dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
0376 
0377     /* MAC HW feature1 */
0378     hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
0379     dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;
0380     dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
0381     dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
0382     dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
0383     dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
0384 
0385     dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
0386     switch (dma_cap->addr64) {
0387     case 0:
0388         dma_cap->addr64 = 32;
0389         break;
0390     case 1:
0391         dma_cap->addr64 = 40;
0392         break;
0393     case 2:
0394         dma_cap->addr64 = 48;
0395         break;
0396     default:
0397         dma_cap->addr64 = 32;
0398         break;
0399     }
0400 
0401     /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
0402      * shifting and store the sizes in bytes.
0403      */
0404     dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
0405     dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
0406     /* MAC HW feature2 */
0407     hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
0408     /* TX and RX number of channels */
0409     dma_cap->number_rx_channel =
0410         ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
0411     dma_cap->number_tx_channel =
0412         ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
0413     /* TX and RX number of queues */
0414     dma_cap->number_rx_queues =
0415         ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
0416     dma_cap->number_tx_queues =
0417         ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
0418     /* PPS output */
0419     dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;
0420 
0421     /* IEEE 1588-2002 */
0422     dma_cap->time_stamp = 0;
0423     /* Number of Auxiliary Snapshot Inputs */
0424     dma_cap->aux_snapshot_n = (hw_cap & GMAC_HW_FEAT_AUXSNAPNUM) >> 28;
0425 
0426     /* MAC HW feature3 */
0427     hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);
0428 
0429     /* 5.10 Features */
0430     dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
0431     dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;
0432     dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;
0433     dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;
0434     dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;
0435     dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;
0436     dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
0437     dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
0438     dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
0439     dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
0440 
0441     return 0;
0442 }
0443 
0444 /* Enable/disable TSO feature and set MSS */
0445 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
0446 {
0447     u32 value;
0448 
0449     if (en) {
0450         /* enable TSO */
0451         value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
0452         writel(value | DMA_CONTROL_TSE,
0453                ioaddr + DMA_CHAN_TX_CONTROL(chan));
0454     } else {
0455         /* enable TSO */
0456         value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
0457         writel(value & ~DMA_CONTROL_TSE,
0458                ioaddr + DMA_CHAN_TX_CONTROL(chan));
0459     }
0460 }
0461 
0462 static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
0463 {
0464     u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
0465 
0466     mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
0467     if (qmode != MTL_QUEUE_AVB)
0468         mtl_tx_op |= MTL_OP_MODE_TXQEN;
0469     else
0470         mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
0471 
0472     writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
0473 }
0474 
0475 static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
0476 {
0477     u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
0478 
0479     value &= ~DMA_RBSZ_MASK;
0480     value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;
0481 
0482     writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
0483 }
0484 
0485 static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
0486 {
0487     u32 value = readl(ioaddr + GMAC_EXT_CONFIG);
0488 
0489     value &= ~GMAC_CONFIG_HDSMS;
0490     value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
0491     writel(value, ioaddr + GMAC_EXT_CONFIG);
0492 
0493     value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
0494     if (en)
0495         value |= DMA_CONTROL_SPH;
0496     else
0497         value &= ~DMA_CONTROL_SPH;
0498     writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
0499 }
0500 
0501 static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
0502 {
0503     u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
0504 
0505     if (en)
0506         value |= DMA_CONTROL_EDSE;
0507     else
0508         value &= ~DMA_CONTROL_EDSE;
0509 
0510     writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
0511 
0512     value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE;
0513     if (en && !value)
0514         return -EIO;
0515 
0516     writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);
0517     return 0;
0518 }
0519 
0520 const struct stmmac_dma_ops dwmac4_dma_ops = {
0521     .reset = dwmac4_dma_reset,
0522     .init = dwmac4_dma_init,
0523     .init_chan = dwmac4_dma_init_channel,
0524     .init_rx_chan = dwmac4_dma_init_rx_chan,
0525     .init_tx_chan = dwmac4_dma_init_tx_chan,
0526     .axi = dwmac4_dma_axi,
0527     .dump_regs = dwmac4_dump_dma_regs,
0528     .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
0529     .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
0530     .enable_dma_irq = dwmac4_enable_dma_irq,
0531     .disable_dma_irq = dwmac4_disable_dma_irq,
0532     .start_tx = dwmac4_dma_start_tx,
0533     .stop_tx = dwmac4_dma_stop_tx,
0534     .start_rx = dwmac4_dma_start_rx,
0535     .stop_rx = dwmac4_dma_stop_rx,
0536     .dma_interrupt = dwmac4_dma_interrupt,
0537     .get_hw_feature = dwmac4_get_hw_feature,
0538     .rx_watchdog = dwmac4_rx_watchdog,
0539     .set_rx_ring_len = dwmac4_set_rx_ring_len,
0540     .set_tx_ring_len = dwmac4_set_tx_ring_len,
0541     .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
0542     .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
0543     .enable_tso = dwmac4_enable_tso,
0544     .qmode = dwmac4_qmode,
0545     .set_bfsize = dwmac4_set_bfsize,
0546     .enable_sph = dwmac4_enable_sph,
0547 };
0548 
0549 const struct stmmac_dma_ops dwmac410_dma_ops = {
0550     .reset = dwmac4_dma_reset,
0551     .init = dwmac4_dma_init,
0552     .init_chan = dwmac410_dma_init_channel,
0553     .init_rx_chan = dwmac4_dma_init_rx_chan,
0554     .init_tx_chan = dwmac4_dma_init_tx_chan,
0555     .axi = dwmac4_dma_axi,
0556     .dump_regs = dwmac4_dump_dma_regs,
0557     .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
0558     .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
0559     .enable_dma_irq = dwmac410_enable_dma_irq,
0560     .disable_dma_irq = dwmac4_disable_dma_irq,
0561     .start_tx = dwmac4_dma_start_tx,
0562     .stop_tx = dwmac4_dma_stop_tx,
0563     .start_rx = dwmac4_dma_start_rx,
0564     .stop_rx = dwmac4_dma_stop_rx,
0565     .dma_interrupt = dwmac4_dma_interrupt,
0566     .get_hw_feature = dwmac4_get_hw_feature,
0567     .rx_watchdog = dwmac4_rx_watchdog,
0568     .set_rx_ring_len = dwmac4_set_rx_ring_len,
0569     .set_tx_ring_len = dwmac4_set_tx_ring_len,
0570     .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
0571     .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
0572     .enable_tso = dwmac4_enable_tso,
0573     .qmode = dwmac4_qmode,
0574     .set_bfsize = dwmac4_set_bfsize,
0575     .enable_sph = dwmac4_enable_sph,
0576     .enable_tbs = dwmac4_enable_tbs,
0577 };
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