stmicro/stmmac/dwmac4_descs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Header File to describe the DMA descriptors and related definitions specific
0004  * for DesignWare databook 4.xx.
0005  *
0006  * Copyright (C) 2015  STMicroelectronics Ltd
0007  *
0008  * Author: Alexandre Torgue <alexandre.torgue@st.com>
0009  */
0010
0011 #ifndef __DWMAC4_DESCS_H__
0012 #define __DWMAC4_DESCS_H__
0013
0014 #include <linux/bitops.h>
0015
0016 /* Normal transmit descriptor defines (without split feature) */
0017
0018 /* TDES2 (read format) */
0019 #define TDES2_BUFFER1_SIZE_MASK     GENMASK(13, 0)
0020 #define TDES2_VLAN_TAG_MASK     GENMASK(15, 14)
0021 #define TDES2_VLAN_TAG_SHIFT        14
0022 #define TDES2_BUFFER2_SIZE_MASK     GENMASK(29, 16)
0023 #define TDES2_BUFFER2_SIZE_MASK_SHIFT   16
0024 #define TDES3_IVTIR_MASK        GENMASK(19, 18)
0025 #define TDES3_IVTIR_SHIFT       18
0026 #define TDES3_IVLTV         BIT(17)
0027 #define TDES2_TIMESTAMP_ENABLE      BIT(30)
0028 #define TDES2_IVT_MASK          GENMASK(31, 16)
0029 #define TDES2_IVT_SHIFT         16
0030 #define TDES2_INTERRUPT_ON_COMPLETION   BIT(31)
0031
0032 /* TDES3 (read format) */
0033 #define TDES3_PACKET_SIZE_MASK      GENMASK(14, 0)
0034 #define TDES3_VLAN_TAG          GENMASK(15, 0)
0035 #define TDES3_VLTV          BIT(16)
0036 #define TDES3_CHECKSUM_INSERTION_MASK   GENMASK(17, 16)
0037 #define TDES3_CHECKSUM_INSERTION_SHIFT  16
0038 #define TDES3_TCP_PKT_PAYLOAD_MASK  GENMASK(17, 0)
0039 #define TDES3_TCP_SEGMENTATION_ENABLE   BIT(18)
0040 #define TDES3_HDR_LEN_SHIFT     19
0041 #define TDES3_SLOT_NUMBER_MASK      GENMASK(22, 19)
0042 #define TDES3_SA_INSERT_CTRL_MASK   GENMASK(25, 23)
0043 #define TDES3_SA_INSERT_CTRL_SHIFT  23
0044 #define TDES3_CRC_PAD_CTRL_MASK     GENMASK(27, 26)
0045
0046 /* TDES3 (write back format) */
0047 #define TDES3_IP_HDR_ERROR      BIT(0)
0048 #define TDES3_DEFERRED          BIT(1)
0049 #define TDES3_UNDERFLOW_ERROR       BIT(2)
0050 #define TDES3_EXCESSIVE_DEFERRAL    BIT(3)
0051 #define TDES3_COLLISION_COUNT_MASK  GENMASK(7, 4)
0052 #define TDES3_COLLISION_COUNT_SHIFT 4
0053 #define TDES3_EXCESSIVE_COLLISION   BIT(8)
0054 #define TDES3_LATE_COLLISION        BIT(9)
0055 #define TDES3_NO_CARRIER        BIT(10)
0056 #define TDES3_LOSS_CARRIER      BIT(11)
0057 #define TDES3_PAYLOAD_ERROR     BIT(12)
0058 #define TDES3_PACKET_FLUSHED        BIT(13)
0059 #define TDES3_JABBER_TIMEOUT        BIT(14)
0060 #define TDES3_ERROR_SUMMARY     BIT(15)
0061 #define TDES3_TIMESTAMP_STATUS      BIT(17)
0062 #define TDES3_TIMESTAMP_STATUS_SHIFT    17
0063
0064 /* TDES3 context */
0065 #define TDES3_CTXT_TCMSSV       BIT(26)
0066
0067 /* TDES3 Common */
0068 #define TDES3_RS1V          BIT(26)
0069 #define TDES3_RS1V_SHIFT        26
0070 #define TDES3_LAST_DESCRIPTOR       BIT(28)
0071 #define TDES3_LAST_DESCRIPTOR_SHIFT 28
0072 #define TDES3_FIRST_DESCRIPTOR      BIT(29)
0073 #define TDES3_CONTEXT_TYPE      BIT(30)
0074 #define TDES3_CONTEXT_TYPE_SHIFT    30
0075
0076 /* TDES4 */
0077 #define TDES4_LTV           BIT(31)
0078 #define TDES4_LT            GENMASK(7, 0)
0079
0080 /* TDES5 */
0081 #define TDES5_LT            GENMASK(31, 8)
0082
0083 /* TDS3 use for both format (read and write back) */
0084 #define TDES3_OWN           BIT(31)
0085 #define TDES3_OWN_SHIFT         31
0086
0087 /* Normal receive descriptor defines (without split feature) */
0088
0089 /* RDES0 (write back format) */
0090 #define RDES0_VLAN_TAG_MASK     GENMASK(15, 0)
0091
0092 /* RDES1 (write back format) */
0093 #define RDES1_IP_PAYLOAD_TYPE_MASK  GENMASK(2, 0)
0094 #define RDES1_IP_HDR_ERROR      BIT(3)
0095 #define RDES1_IPV4_HEADER       BIT(4)
0096 #define RDES1_IPV6_HEADER       BIT(5)
0097 #define RDES1_IP_CSUM_BYPASSED      BIT(6)
0098 #define RDES1_IP_CSUM_ERROR     BIT(7)
0099 #define RDES1_PTP_MSG_TYPE_MASK     GENMASK(11, 8)
0100 #define RDES1_PTP_PACKET_TYPE       BIT(12)
0101 #define RDES1_PTP_VER           BIT(13)
0102 #define RDES1_TIMESTAMP_AVAILABLE   BIT(14)
0103 #define RDES1_TIMESTAMP_AVAILABLE_SHIFT 14
0104 #define RDES1_TIMESTAMP_DROPPED     BIT(15)
0105 #define RDES1_IP_TYPE1_CSUM_MASK    GENMASK(31, 16)
0106
0107 /* RDES2 (write back format) */
0108 #define RDES2_L3_L4_HEADER_SIZE_MASK    GENMASK(9, 0)
0109 #define RDES2_VLAN_FILTER_STATUS    BIT(15)
0110 #define RDES2_SA_FILTER_FAIL        BIT(16)
0111 #define RDES2_DA_FILTER_FAIL        BIT(17)
0112 #define RDES2_HASH_FILTER_STATUS    BIT(18)
0113 #define RDES2_MAC_ADDR_MATCH_MASK   GENMASK(26, 19)
0114 #define RDES2_HASH_VALUE_MATCH_MASK GENMASK(26, 19)
0115 #define RDES2_L3_FILTER_MATCH       BIT(27)
0116 #define RDES2_L4_FILTER_MATCH       BIT(28)
0117 #define RDES2_L3_L4_FILT_NB_MATCH_MASK  GENMASK(27, 26)
0118 #define RDES2_L3_L4_FILT_NB_MATCH_SHIFT 26
0119 #define RDES2_HL            GENMASK(9, 0)
0120
0121 /* RDES3 (write back format) */
0122 #define RDES3_PACKET_SIZE_MASK      GENMASK(14, 0)
0123 #define RDES3_ERROR_SUMMARY     BIT(15)
0124 #define RDES3_PACKET_LEN_TYPE_MASK  GENMASK(18, 16)
0125 #define RDES3_DRIBBLE_ERROR     BIT(19)
0126 #define RDES3_RECEIVE_ERROR     BIT(20)
0127 #define RDES3_OVERFLOW_ERROR        BIT(21)
0128 #define RDES3_RECEIVE_WATCHDOG      BIT(22)
0129 #define RDES3_GIANT_PACKET      BIT(23)
0130 #define RDES3_CRC_ERROR         BIT(24)
0131 #define RDES3_RDES0_VALID       BIT(25)
0132 #define RDES3_RDES1_VALID       BIT(26)
0133 #define RDES3_RDES2_VALID       BIT(27)
0134 #define RDES3_LAST_DESCRIPTOR       BIT(28)
0135 #define RDES3_FIRST_DESCRIPTOR      BIT(29)
0136 #define RDES3_CONTEXT_DESCRIPTOR    BIT(30)
0137 #define RDES3_CONTEXT_DESCRIPTOR_SHIFT  30
0138
0139 /* RDES3 (read format) */
0140 #define RDES3_BUFFER1_VALID_ADDR    BIT(24)
0141 #define RDES3_BUFFER2_VALID_ADDR    BIT(25)
0142 #define RDES3_INT_ON_COMPLETION_EN  BIT(30)
0143
0144 /* TDS3 use for both format (read and write back) */
0145 #define RDES3_OWN           BIT(31)
0146
0147 #endif /* __DWMAC4_DESCS_H__ */