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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
0004  * DWC Ether MAC version 4.00  has been used for developing this code.
0005  *
0006  * This only implements the mac core functions for this chip.
0007  *
0008  * Copyright (C) 2015  STMicroelectronics Ltd
0009  *
0010  * Author: Alexandre Torgue <alexandre.torgue@st.com>
0011  */
0012 
0013 #include <linux/crc32.h>
0014 #include <linux/slab.h>
0015 #include <linux/ethtool.h>
0016 #include <linux/io.h>
0017 #include <net/dsa.h>
0018 #include "stmmac.h"
0019 #include "stmmac_pcs.h"
0020 #include "dwmac4.h"
0021 #include "dwmac5.h"
0022 
0023 static void dwmac4_core_init(struct mac_device_info *hw,
0024                  struct net_device *dev)
0025 {
0026     struct stmmac_priv *priv = netdev_priv(dev);
0027     void __iomem *ioaddr = hw->pcsr;
0028     u32 value = readl(ioaddr + GMAC_CONFIG);
0029 
0030     value |= GMAC_CORE_INIT;
0031 
0032     if (hw->ps) {
0033         value |= GMAC_CONFIG_TE;
0034 
0035         value &= hw->link.speed_mask;
0036         switch (hw->ps) {
0037         case SPEED_1000:
0038             value |= hw->link.speed1000;
0039             break;
0040         case SPEED_100:
0041             value |= hw->link.speed100;
0042             break;
0043         case SPEED_10:
0044             value |= hw->link.speed10;
0045             break;
0046         }
0047     }
0048 
0049     writel(value, ioaddr + GMAC_CONFIG);
0050 
0051     /* Enable GMAC interrupts */
0052     value = GMAC_INT_DEFAULT_ENABLE;
0053 
0054     if (hw->pcs)
0055         value |= GMAC_PCS_IRQ_DEFAULT;
0056 
0057     /* Enable FPE interrupt */
0058     if ((GMAC_HW_FEAT_FPESEL & readl(ioaddr + GMAC_HW_FEATURE3)) >> 26)
0059         value |= GMAC_INT_FPE_EN;
0060 
0061     writel(value, ioaddr + GMAC_INT_EN);
0062 
0063     if (GMAC_INT_DEFAULT_ENABLE & GMAC_INT_TSIE)
0064         init_waitqueue_head(&priv->tstamp_busy_wait);
0065 }
0066 
0067 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
0068                    u8 mode, u32 queue)
0069 {
0070     void __iomem *ioaddr = hw->pcsr;
0071     u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
0072 
0073     value &= GMAC_RX_QUEUE_CLEAR(queue);
0074     if (mode == MTL_QUEUE_AVB)
0075         value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
0076     else if (mode == MTL_QUEUE_DCB)
0077         value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
0078 
0079     writel(value, ioaddr + GMAC_RXQ_CTRL0);
0080 }
0081 
0082 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
0083                      u32 prio, u32 queue)
0084 {
0085     void __iomem *ioaddr = hw->pcsr;
0086     u32 base_register;
0087     u32 value;
0088 
0089     base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
0090     if (queue >= 4)
0091         queue -= 4;
0092 
0093     value = readl(ioaddr + base_register);
0094 
0095     value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
0096     value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
0097                         GMAC_RXQCTRL_PSRQX_MASK(queue);
0098     writel(value, ioaddr + base_register);
0099 }
0100 
0101 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
0102                      u32 prio, u32 queue)
0103 {
0104     void __iomem *ioaddr = hw->pcsr;
0105     u32 base_register;
0106     u32 value;
0107 
0108     base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
0109     if (queue >= 4)
0110         queue -= 4;
0111 
0112     value = readl(ioaddr + base_register);
0113 
0114     value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
0115     value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
0116                         GMAC_TXQCTRL_PSTQX_MASK(queue);
0117 
0118     writel(value, ioaddr + base_register);
0119 }
0120 
0121 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
0122                     u8 packet, u32 queue)
0123 {
0124     void __iomem *ioaddr = hw->pcsr;
0125     u32 value;
0126 
0127     static const struct stmmac_rx_routing route_possibilities[] = {
0128         { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
0129         { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
0130         { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
0131         { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
0132         { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
0133     };
0134 
0135     value = readl(ioaddr + GMAC_RXQ_CTRL1);
0136 
0137     /* routing configuration */
0138     value &= ~route_possibilities[packet - 1].reg_mask;
0139     value |= (queue << route_possibilities[packet-1].reg_shift) &
0140          route_possibilities[packet - 1].reg_mask;
0141 
0142     /* some packets require extra ops */
0143     if (packet == PACKET_AVCPQ) {
0144         value &= ~GMAC_RXQCTRL_TACPQE;
0145         value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
0146     } else if (packet == PACKET_MCBCQ) {
0147         value &= ~GMAC_RXQCTRL_MCBCQEN;
0148         value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
0149     }
0150 
0151     writel(value, ioaddr + GMAC_RXQ_CTRL1);
0152 }
0153 
0154 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
0155                       u32 rx_alg)
0156 {
0157     void __iomem *ioaddr = hw->pcsr;
0158     u32 value = readl(ioaddr + MTL_OPERATION_MODE);
0159 
0160     value &= ~MTL_OPERATION_RAA;
0161     switch (rx_alg) {
0162     case MTL_RX_ALGORITHM_SP:
0163         value |= MTL_OPERATION_RAA_SP;
0164         break;
0165     case MTL_RX_ALGORITHM_WSP:
0166         value |= MTL_OPERATION_RAA_WSP;
0167         break;
0168     default:
0169         break;
0170     }
0171 
0172     writel(value, ioaddr + MTL_OPERATION_MODE);
0173 }
0174 
0175 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
0176                       u32 tx_alg)
0177 {
0178     void __iomem *ioaddr = hw->pcsr;
0179     u32 value = readl(ioaddr + MTL_OPERATION_MODE);
0180 
0181     value &= ~MTL_OPERATION_SCHALG_MASK;
0182     switch (tx_alg) {
0183     case MTL_TX_ALGORITHM_WRR:
0184         value |= MTL_OPERATION_SCHALG_WRR;
0185         break;
0186     case MTL_TX_ALGORITHM_WFQ:
0187         value |= MTL_OPERATION_SCHALG_WFQ;
0188         break;
0189     case MTL_TX_ALGORITHM_DWRR:
0190         value |= MTL_OPERATION_SCHALG_DWRR;
0191         break;
0192     case MTL_TX_ALGORITHM_SP:
0193         value |= MTL_OPERATION_SCHALG_SP;
0194         break;
0195     default:
0196         break;
0197     }
0198 
0199     writel(value, ioaddr + MTL_OPERATION_MODE);
0200 }
0201 
0202 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
0203                        u32 weight, u32 queue)
0204 {
0205     void __iomem *ioaddr = hw->pcsr;
0206     u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
0207 
0208     value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
0209     value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
0210     writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
0211 }
0212 
0213 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
0214 {
0215     void __iomem *ioaddr = hw->pcsr;
0216     u32 value;
0217 
0218     if (queue < 4)
0219         value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
0220     else
0221         value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
0222 
0223     if (queue == 0 || queue == 4) {
0224         value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
0225         value |= MTL_RXQ_DMA_Q04MDMACH(chan);
0226     } else if (queue > 4) {
0227         value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
0228         value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
0229     } else {
0230         value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
0231         value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
0232     }
0233 
0234     if (queue < 4)
0235         writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
0236     else
0237         writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
0238 }
0239 
0240 static void dwmac4_config_cbs(struct mac_device_info *hw,
0241                   u32 send_slope, u32 idle_slope,
0242                   u32 high_credit, u32 low_credit, u32 queue)
0243 {
0244     void __iomem *ioaddr = hw->pcsr;
0245     u32 value;
0246 
0247     pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
0248     pr_debug("\tsend_slope: 0x%08x\n", send_slope);
0249     pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
0250     pr_debug("\thigh_credit: 0x%08x\n", high_credit);
0251     pr_debug("\tlow_credit: 0x%08x\n", low_credit);
0252 
0253     /* enable AV algorithm */
0254     value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
0255     value |= MTL_ETS_CTRL_AVALG;
0256     value |= MTL_ETS_CTRL_CC;
0257     writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
0258 
0259     /* configure send slope */
0260     value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
0261     value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
0262     value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
0263     writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
0264 
0265     /* configure idle slope (same register as tx weight) */
0266     dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
0267 
0268     /* configure high credit */
0269     value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
0270     value &= ~MTL_HIGH_CRED_HC_MASK;
0271     value |= high_credit & MTL_HIGH_CRED_HC_MASK;
0272     writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
0273 
0274     /* configure high credit */
0275     value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
0276     value &= ~MTL_HIGH_CRED_LC_MASK;
0277     value |= low_credit & MTL_HIGH_CRED_LC_MASK;
0278     writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
0279 }
0280 
0281 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
0282 {
0283     void __iomem *ioaddr = hw->pcsr;
0284     int i;
0285 
0286     for (i = 0; i < GMAC_REG_NUM; i++)
0287         reg_space[i] = readl(ioaddr + i * 4);
0288 }
0289 
0290 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
0291 {
0292     void __iomem *ioaddr = hw->pcsr;
0293     u32 value = readl(ioaddr + GMAC_CONFIG);
0294 
0295     if (hw->rx_csum)
0296         value |= GMAC_CONFIG_IPC;
0297     else
0298         value &= ~GMAC_CONFIG_IPC;
0299 
0300     writel(value, ioaddr + GMAC_CONFIG);
0301 
0302     value = readl(ioaddr + GMAC_CONFIG);
0303 
0304     return !!(value & GMAC_CONFIG_IPC);
0305 }
0306 
0307 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
0308 {
0309     void __iomem *ioaddr = hw->pcsr;
0310     unsigned int pmt = 0;
0311     u32 config;
0312 
0313     if (mode & WAKE_MAGIC) {
0314         pr_debug("GMAC: WOL Magic frame\n");
0315         pmt |= power_down | magic_pkt_en;
0316     }
0317     if (mode & WAKE_UCAST) {
0318         pr_debug("GMAC: WOL on global unicast\n");
0319         pmt |= power_down | global_unicast | wake_up_frame_en;
0320     }
0321 
0322     if (pmt) {
0323         /* The receiver must be enabled for WOL before powering down */
0324         config = readl(ioaddr + GMAC_CONFIG);
0325         config |= GMAC_CONFIG_RE;
0326         writel(config, ioaddr + GMAC_CONFIG);
0327     }
0328     writel(pmt, ioaddr + GMAC_PMT);
0329 }
0330 
0331 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
0332                  const unsigned char *addr, unsigned int reg_n)
0333 {
0334     void __iomem *ioaddr = hw->pcsr;
0335 
0336     stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
0337                    GMAC_ADDR_LOW(reg_n));
0338 }
0339 
0340 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
0341                  unsigned char *addr, unsigned int reg_n)
0342 {
0343     void __iomem *ioaddr = hw->pcsr;
0344 
0345     stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
0346                    GMAC_ADDR_LOW(reg_n));
0347 }
0348 
0349 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
0350                 bool en_tx_lpi_clockgating)
0351 {
0352     void __iomem *ioaddr = hw->pcsr;
0353     u32 value;
0354 
0355     /* Enable the link status receive on RGMII, SGMII ore SMII
0356      * receive path and instruct the transmit to enter in LPI
0357      * state.
0358      */
0359     value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
0360     value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
0361 
0362     if (en_tx_lpi_clockgating)
0363         value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
0364 
0365     writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
0366 }
0367 
0368 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
0369 {
0370     void __iomem *ioaddr = hw->pcsr;
0371     u32 value;
0372 
0373     value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
0374     value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
0375     writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
0376 }
0377 
0378 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
0379 {
0380     void __iomem *ioaddr = hw->pcsr;
0381     u32 value;
0382 
0383     value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
0384 
0385     if (link)
0386         value |= GMAC4_LPI_CTRL_STATUS_PLS;
0387     else
0388         value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
0389 
0390     writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
0391 }
0392 
0393 static void dwmac4_set_eee_lpi_entry_timer(struct mac_device_info *hw, int et)
0394 {
0395     void __iomem *ioaddr = hw->pcsr;
0396     int value = et & STMMAC_ET_MAX;
0397     int regval;
0398 
0399     /* Program LPI entry timer value into register */
0400     writel(value, ioaddr + GMAC4_LPI_ENTRY_TIMER);
0401 
0402     /* Enable/disable LPI entry timer */
0403     regval = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
0404     regval |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
0405 
0406     if (et)
0407         regval |= GMAC4_LPI_CTRL_STATUS_LPIATE;
0408     else
0409         regval &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;
0410 
0411     writel(regval, ioaddr + GMAC4_LPI_CTRL_STATUS);
0412 }
0413 
0414 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
0415 {
0416     void __iomem *ioaddr = hw->pcsr;
0417     int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
0418 
0419     /* Program the timers in the LPI timer control register:
0420      * LS: minimum time (ms) for which the link
0421      *  status from PHY should be ok before transmitting
0422      *  the LPI pattern.
0423      * TW: minimum time (us) for which the core waits
0424      *  after it has stopped transmitting the LPI pattern.
0425      */
0426     writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
0427 }
0428 
0429 static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
0430 {
0431     void __iomem *ioaddr = (void __iomem *)dev->base_addr;
0432     u32 val;
0433 
0434     val = readl(ioaddr + GMAC_VLAN_TAG);
0435     val &= ~GMAC_VLAN_TAG_VID;
0436     val |= GMAC_VLAN_TAG_ETV | vid;
0437 
0438     writel(val, ioaddr + GMAC_VLAN_TAG);
0439 }
0440 
0441 static int dwmac4_write_vlan_filter(struct net_device *dev,
0442                     struct mac_device_info *hw,
0443                     u8 index, u32 data)
0444 {
0445     void __iomem *ioaddr = (void __iomem *)dev->base_addr;
0446     int i, timeout = 10;
0447     u32 val;
0448 
0449     if (index >= hw->num_vlan)
0450         return -EINVAL;
0451 
0452     writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
0453 
0454     val = readl(ioaddr + GMAC_VLAN_TAG);
0455     val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
0456         GMAC_VLAN_TAG_CTRL_CT |
0457         GMAC_VLAN_TAG_CTRL_OB);
0458     val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
0459 
0460     writel(val, ioaddr + GMAC_VLAN_TAG);
0461 
0462     for (i = 0; i < timeout; i++) {
0463         val = readl(ioaddr + GMAC_VLAN_TAG);
0464         if (!(val & GMAC_VLAN_TAG_CTRL_OB))
0465             return 0;
0466         udelay(1);
0467     }
0468 
0469     netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
0470 
0471     return -EBUSY;
0472 }
0473 
0474 static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
0475                       struct mac_device_info *hw,
0476                       __be16 proto, u16 vid)
0477 {
0478     int index = -1;
0479     u32 val = 0;
0480     int i, ret;
0481 
0482     if (vid > 4095)
0483         return -EINVAL;
0484 
0485     if (hw->promisc) {
0486         netdev_err(dev,
0487                "Adding VLAN in promisc mode not supported\n");
0488         return -EPERM;
0489     }
0490 
0491     /* Single Rx VLAN Filter */
0492     if (hw->num_vlan == 1) {
0493         /* For single VLAN filter, VID 0 means VLAN promiscuous */
0494         if (vid == 0) {
0495             netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
0496             return -EPERM;
0497         }
0498 
0499         if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
0500             netdev_err(dev, "Only single VLAN ID supported\n");
0501             return -EPERM;
0502         }
0503 
0504         hw->vlan_filter[0] = vid;
0505         dwmac4_write_single_vlan(dev, vid);
0506 
0507         return 0;
0508     }
0509 
0510     /* Extended Rx VLAN Filter Enable */
0511     val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
0512 
0513     for (i = 0; i < hw->num_vlan; i++) {
0514         if (hw->vlan_filter[i] == val)
0515             return 0;
0516         else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
0517             index = i;
0518     }
0519 
0520     if (index == -1) {
0521         netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
0522                hw->num_vlan);
0523         return -EPERM;
0524     }
0525 
0526     ret = dwmac4_write_vlan_filter(dev, hw, index, val);
0527 
0528     if (!ret)
0529         hw->vlan_filter[index] = val;
0530 
0531     return ret;
0532 }
0533 
0534 static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
0535                       struct mac_device_info *hw,
0536                       __be16 proto, u16 vid)
0537 {
0538     int i, ret = 0;
0539 
0540     if (hw->promisc) {
0541         netdev_err(dev,
0542                "Deleting VLAN in promisc mode not supported\n");
0543         return -EPERM;
0544     }
0545 
0546     /* Single Rx VLAN Filter */
0547     if (hw->num_vlan == 1) {
0548         if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
0549             hw->vlan_filter[0] = 0;
0550             dwmac4_write_single_vlan(dev, 0);
0551         }
0552         return 0;
0553     }
0554 
0555     /* Extended Rx VLAN Filter Enable */
0556     for (i = 0; i < hw->num_vlan; i++) {
0557         if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
0558             ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
0559 
0560             if (!ret)
0561                 hw->vlan_filter[i] = 0;
0562             else
0563                 return ret;
0564         }
0565     }
0566 
0567     return ret;
0568 }
0569 
0570 static void dwmac4_vlan_promisc_enable(struct net_device *dev,
0571                        struct mac_device_info *hw)
0572 {
0573     void __iomem *ioaddr = hw->pcsr;
0574     u32 value;
0575     u32 hash;
0576     u32 val;
0577     int i;
0578 
0579     /* Single Rx VLAN Filter */
0580     if (hw->num_vlan == 1) {
0581         dwmac4_write_single_vlan(dev, 0);
0582         return;
0583     }
0584 
0585     /* Extended Rx VLAN Filter Enable */
0586     for (i = 0; i < hw->num_vlan; i++) {
0587         if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
0588             val = hw->vlan_filter[i] & ~GMAC_VLAN_TAG_DATA_VEN;
0589             dwmac4_write_vlan_filter(dev, hw, i, val);
0590         }
0591     }
0592 
0593     hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
0594     if (hash & GMAC_VLAN_VLHT) {
0595         value = readl(ioaddr + GMAC_VLAN_TAG);
0596         if (value & GMAC_VLAN_VTHM) {
0597             value &= ~GMAC_VLAN_VTHM;
0598             writel(value, ioaddr + GMAC_VLAN_TAG);
0599         }
0600     }
0601 }
0602 
0603 static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
0604                        struct mac_device_info *hw)
0605 {
0606     void __iomem *ioaddr = hw->pcsr;
0607     u32 value;
0608     u32 hash;
0609     u32 val;
0610     int i;
0611 
0612     /* Single Rx VLAN Filter */
0613     if (hw->num_vlan == 1) {
0614         dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
0615         return;
0616     }
0617 
0618     /* Extended Rx VLAN Filter Enable */
0619     for (i = 0; i < hw->num_vlan; i++) {
0620         if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
0621             val = hw->vlan_filter[i];
0622             dwmac4_write_vlan_filter(dev, hw, i, val);
0623         }
0624     }
0625 
0626     hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
0627     if (hash & GMAC_VLAN_VLHT) {
0628         value = readl(ioaddr + GMAC_VLAN_TAG);
0629         value |= GMAC_VLAN_VTHM;
0630         writel(value, ioaddr + GMAC_VLAN_TAG);
0631     }
0632 }
0633 
0634 static void dwmac4_set_filter(struct mac_device_info *hw,
0635                   struct net_device *dev)
0636 {
0637     void __iomem *ioaddr = (void __iomem *)dev->base_addr;
0638     int numhashregs = (hw->multicast_filter_bins >> 5);
0639     int mcbitslog2 = hw->mcast_bits_log2;
0640     unsigned int value;
0641     u32 mc_filter[8];
0642     int i;
0643 
0644     memset(mc_filter, 0, sizeof(mc_filter));
0645 
0646     value = readl(ioaddr + GMAC_PACKET_FILTER);
0647     value &= ~GMAC_PACKET_FILTER_HMC;
0648     value &= ~GMAC_PACKET_FILTER_HPF;
0649     value &= ~GMAC_PACKET_FILTER_PCF;
0650     value &= ~GMAC_PACKET_FILTER_PM;
0651     value &= ~GMAC_PACKET_FILTER_PR;
0652     value &= ~GMAC_PACKET_FILTER_RA;
0653     if (dev->flags & IFF_PROMISC) {
0654         /* VLAN Tag Filter Fail Packets Queuing */
0655         if (hw->vlan_fail_q_en) {
0656             value = readl(ioaddr + GMAC_RXQ_CTRL4);
0657             value &= ~GMAC_RXQCTRL_VFFQ_MASK;
0658             value |= GMAC_RXQCTRL_VFFQE |
0659                  (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
0660             writel(value, ioaddr + GMAC_RXQ_CTRL4);
0661             value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
0662         } else {
0663             value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
0664         }
0665 
0666     } else if ((dev->flags & IFF_ALLMULTI) ||
0667            (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
0668         /* Pass all multi */
0669         value |= GMAC_PACKET_FILTER_PM;
0670         /* Set all the bits of the HASH tab */
0671         memset(mc_filter, 0xff, sizeof(mc_filter));
0672     } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
0673         struct netdev_hw_addr *ha;
0674 
0675         /* Hash filter for multicast */
0676         value |= GMAC_PACKET_FILTER_HMC;
0677 
0678         netdev_for_each_mc_addr(ha, dev) {
0679             /* The upper n bits of the calculated CRC are used to
0680              * index the contents of the hash table. The number of
0681              * bits used depends on the hardware configuration
0682              * selected at core configuration time.
0683              */
0684             u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
0685                     ETH_ALEN)) >> (32 - mcbitslog2);
0686             /* The most significant bit determines the register to
0687              * use (H/L) while the other 5 bits determine the bit
0688              * within the register.
0689              */
0690             mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
0691         }
0692     }
0693 
0694     for (i = 0; i < numhashregs; i++)
0695         writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
0696 
0697     value |= GMAC_PACKET_FILTER_HPF;
0698 
0699     /* Handle multiple unicast addresses */
0700     if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
0701         /* Switch to promiscuous mode if more than 128 addrs
0702          * are required
0703          */
0704         value |= GMAC_PACKET_FILTER_PR;
0705     } else {
0706         struct netdev_hw_addr *ha;
0707         int reg = 1;
0708 
0709         netdev_for_each_uc_addr(ha, dev) {
0710             dwmac4_set_umac_addr(hw, ha->addr, reg);
0711             reg++;
0712         }
0713 
0714         while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
0715             writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
0716             writel(0, ioaddr + GMAC_ADDR_LOW(reg));
0717             reg++;
0718         }
0719     }
0720 
0721     /* VLAN filtering */
0722     if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
0723         value |= GMAC_PACKET_FILTER_VTFE;
0724 
0725     writel(value, ioaddr + GMAC_PACKET_FILTER);
0726 
0727     if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en) {
0728         if (!hw->promisc) {
0729             hw->promisc = 1;
0730             dwmac4_vlan_promisc_enable(dev, hw);
0731         }
0732     } else {
0733         if (hw->promisc) {
0734             hw->promisc = 0;
0735             dwmac4_restore_hw_vlan_rx_fltr(dev, hw);
0736         }
0737     }
0738 }
0739 
0740 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
0741                  unsigned int fc, unsigned int pause_time,
0742                  u32 tx_cnt)
0743 {
0744     void __iomem *ioaddr = hw->pcsr;
0745     unsigned int flow = 0;
0746     u32 queue = 0;
0747 
0748     pr_debug("GMAC Flow-Control:\n");
0749     if (fc & FLOW_RX) {
0750         pr_debug("\tReceive Flow-Control ON\n");
0751         flow |= GMAC_RX_FLOW_CTRL_RFE;
0752     }
0753     writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
0754 
0755     if (fc & FLOW_TX) {
0756         pr_debug("\tTransmit Flow-Control ON\n");
0757 
0758         if (duplex)
0759             pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
0760 
0761         for (queue = 0; queue < tx_cnt; queue++) {
0762             flow = GMAC_TX_FLOW_CTRL_TFE;
0763 
0764             if (duplex)
0765                 flow |=
0766                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
0767 
0768             writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
0769         }
0770     } else {
0771         for (queue = 0; queue < tx_cnt; queue++)
0772             writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
0773     }
0774 }
0775 
0776 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
0777                 bool loopback)
0778 {
0779     dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
0780 }
0781 
0782 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
0783 {
0784     dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
0785 }
0786 
0787 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
0788 {
0789     dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
0790 }
0791 
0792 /* RGMII or SMII interface */
0793 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
0794 {
0795     u32 status;
0796 
0797     status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
0798     x->irq_rgmii_n++;
0799 
0800     /* Check the link status */
0801     if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
0802         int speed_value;
0803 
0804         x->pcs_link = 1;
0805 
0806         speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
0807                    GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
0808         if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
0809             x->pcs_speed = SPEED_1000;
0810         else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
0811             x->pcs_speed = SPEED_100;
0812         else
0813             x->pcs_speed = SPEED_10;
0814 
0815         x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
0816 
0817         pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
0818             x->pcs_duplex ? "Full" : "Half");
0819     } else {
0820         x->pcs_link = 0;
0821         pr_info("Link is Down\n");
0822     }
0823 }
0824 
0825 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
0826 {
0827     void __iomem *ioaddr = hw->pcsr;
0828     u32 mtl_int_qx_status;
0829     int ret = 0;
0830 
0831     mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
0832 
0833     /* Check MTL Interrupt */
0834     if (mtl_int_qx_status & MTL_INT_QX(chan)) {
0835         /* read Queue x Interrupt status */
0836         u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
0837 
0838         if (status & MTL_RX_OVERFLOW_INT) {
0839             /*  clear Interrupt */
0840             writel(status | MTL_RX_OVERFLOW_INT,
0841                    ioaddr + MTL_CHAN_INT_CTRL(chan));
0842             ret = CORE_IRQ_MTL_RX_OVERFLOW;
0843         }
0844     }
0845 
0846     return ret;
0847 }
0848 
0849 static int dwmac4_irq_status(struct mac_device_info *hw,
0850                  struct stmmac_extra_stats *x)
0851 {
0852     void __iomem *ioaddr = hw->pcsr;
0853     u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
0854     u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
0855     int ret = 0;
0856 
0857     /* Discard disabled bits */
0858     intr_status &= intr_enable;
0859 
0860     /* Not used events (e.g. MMC interrupts) are not handled. */
0861     if ((intr_status & mmc_tx_irq))
0862         x->mmc_tx_irq_n++;
0863     if (unlikely(intr_status & mmc_rx_irq))
0864         x->mmc_rx_irq_n++;
0865     if (unlikely(intr_status & mmc_rx_csum_offload_irq))
0866         x->mmc_rx_csum_offload_irq_n++;
0867     /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
0868     if (unlikely(intr_status & pmt_irq)) {
0869         readl(ioaddr + GMAC_PMT);
0870         x->irq_receive_pmt_irq_n++;
0871     }
0872 
0873     /* MAC tx/rx EEE LPI entry/exit interrupts */
0874     if (intr_status & lpi_irq) {
0875         /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
0876         u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
0877 
0878         if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
0879             ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
0880             x->irq_tx_path_in_lpi_mode_n++;
0881         }
0882         if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
0883             ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
0884             x->irq_tx_path_exit_lpi_mode_n++;
0885         }
0886         if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
0887             x->irq_rx_path_in_lpi_mode_n++;
0888         if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
0889             x->irq_rx_path_exit_lpi_mode_n++;
0890     }
0891 
0892     dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
0893     if (intr_status & PCS_RGSMIIIS_IRQ)
0894         dwmac4_phystatus(ioaddr, x);
0895 
0896     return ret;
0897 }
0898 
0899 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
0900              u32 rx_queues, u32 tx_queues)
0901 {
0902     u32 value;
0903     u32 queue;
0904 
0905     for (queue = 0; queue < tx_queues; queue++) {
0906         value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
0907 
0908         if (value & MTL_DEBUG_TXSTSFSTS)
0909             x->mtl_tx_status_fifo_full++;
0910         if (value & MTL_DEBUG_TXFSTS)
0911             x->mtl_tx_fifo_not_empty++;
0912         if (value & MTL_DEBUG_TWCSTS)
0913             x->mmtl_fifo_ctrl++;
0914         if (value & MTL_DEBUG_TRCSTS_MASK) {
0915             u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
0916                      >> MTL_DEBUG_TRCSTS_SHIFT;
0917             if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
0918                 x->mtl_tx_fifo_read_ctrl_write++;
0919             else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
0920                 x->mtl_tx_fifo_read_ctrl_wait++;
0921             else if (trcsts == MTL_DEBUG_TRCSTS_READ)
0922                 x->mtl_tx_fifo_read_ctrl_read++;
0923             else
0924                 x->mtl_tx_fifo_read_ctrl_idle++;
0925         }
0926         if (value & MTL_DEBUG_TXPAUSED)
0927             x->mac_tx_in_pause++;
0928     }
0929 
0930     for (queue = 0; queue < rx_queues; queue++) {
0931         value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
0932 
0933         if (value & MTL_DEBUG_RXFSTS_MASK) {
0934             u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
0935                      >> MTL_DEBUG_RRCSTS_SHIFT;
0936 
0937             if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
0938                 x->mtl_rx_fifo_fill_level_full++;
0939             else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
0940                 x->mtl_rx_fifo_fill_above_thresh++;
0941             else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
0942                 x->mtl_rx_fifo_fill_below_thresh++;
0943             else
0944                 x->mtl_rx_fifo_fill_level_empty++;
0945         }
0946         if (value & MTL_DEBUG_RRCSTS_MASK) {
0947             u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
0948                      MTL_DEBUG_RRCSTS_SHIFT;
0949 
0950             if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
0951                 x->mtl_rx_fifo_read_ctrl_flush++;
0952             else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
0953                 x->mtl_rx_fifo_read_ctrl_read_data++;
0954             else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
0955                 x->mtl_rx_fifo_read_ctrl_status++;
0956             else
0957                 x->mtl_rx_fifo_read_ctrl_idle++;
0958         }
0959         if (value & MTL_DEBUG_RWCSTS)
0960             x->mtl_rx_fifo_ctrl_active++;
0961     }
0962 
0963     /* GMAC debug */
0964     value = readl(ioaddr + GMAC_DEBUG);
0965 
0966     if (value & GMAC_DEBUG_TFCSTS_MASK) {
0967         u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
0968                   >> GMAC_DEBUG_TFCSTS_SHIFT;
0969 
0970         if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
0971             x->mac_tx_frame_ctrl_xfer++;
0972         else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
0973             x->mac_tx_frame_ctrl_pause++;
0974         else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
0975             x->mac_tx_frame_ctrl_wait++;
0976         else
0977             x->mac_tx_frame_ctrl_idle++;
0978     }
0979     if (value & GMAC_DEBUG_TPESTS)
0980         x->mac_gmii_tx_proto_engine++;
0981     if (value & GMAC_DEBUG_RFCFCSTS_MASK)
0982         x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
0983                         >> GMAC_DEBUG_RFCFCSTS_SHIFT;
0984     if (value & GMAC_DEBUG_RPESTS)
0985         x->mac_gmii_rx_proto_engine++;
0986 }
0987 
0988 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
0989 {
0990     u32 value = readl(ioaddr + GMAC_CONFIG);
0991 
0992     if (enable)
0993         value |= GMAC_CONFIG_LM;
0994     else
0995         value &= ~GMAC_CONFIG_LM;
0996 
0997     writel(value, ioaddr + GMAC_CONFIG);
0998 }
0999 
1000 static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
1001                     __le16 perfect_match, bool is_double)
1002 {
1003     void __iomem *ioaddr = hw->pcsr;
1004     u32 value;
1005 
1006     writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
1007 
1008     value = readl(ioaddr + GMAC_VLAN_TAG);
1009 
1010     if (hash) {
1011         value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
1012         if (is_double) {
1013             value |= GMAC_VLAN_EDVLP;
1014             value |= GMAC_VLAN_ESVL;
1015             value |= GMAC_VLAN_DOVLTC;
1016         }
1017 
1018         writel(value, ioaddr + GMAC_VLAN_TAG);
1019     } else if (perfect_match) {
1020         u32 value = GMAC_VLAN_ETV;
1021 
1022         if (is_double) {
1023             value |= GMAC_VLAN_EDVLP;
1024             value |= GMAC_VLAN_ESVL;
1025             value |= GMAC_VLAN_DOVLTC;
1026         }
1027 
1028         writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
1029     } else {
1030         value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
1031         value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
1032         value &= ~GMAC_VLAN_DOVLTC;
1033         value &= ~GMAC_VLAN_VID;
1034 
1035         writel(value, ioaddr + GMAC_VLAN_TAG);
1036     }
1037 }
1038 
1039 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
1040 {
1041     u32 value = readl(ioaddr + GMAC_CONFIG);
1042 
1043     value &= ~GMAC_CONFIG_SARC;
1044     value |= val << GMAC_CONFIG_SARC_SHIFT;
1045 
1046     writel(value, ioaddr + GMAC_CONFIG);
1047 }
1048 
1049 static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
1050 {
1051     void __iomem *ioaddr = hw->pcsr;
1052     u32 value;
1053 
1054     value = readl(ioaddr + GMAC_VLAN_INCL);
1055     value |= GMAC_VLAN_VLTI;
1056     value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
1057     value &= ~GMAC_VLAN_VLC;
1058     value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
1059     writel(value, ioaddr + GMAC_VLAN_INCL);
1060 }
1061 
1062 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
1063                    u32 addr)
1064 {
1065     void __iomem *ioaddr = hw->pcsr;
1066     u32 value;
1067 
1068     writel(addr, ioaddr + GMAC_ARP_ADDR);
1069 
1070     value = readl(ioaddr + GMAC_CONFIG);
1071     if (en)
1072         value |= GMAC_CONFIG_ARPEN;
1073     else
1074         value &= ~GMAC_CONFIG_ARPEN;
1075     writel(value, ioaddr + GMAC_CONFIG);
1076 }
1077 
1078 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1079                    bool en, bool ipv6, bool sa, bool inv,
1080                    u32 match)
1081 {
1082     void __iomem *ioaddr = hw->pcsr;
1083     u32 value;
1084 
1085     value = readl(ioaddr + GMAC_PACKET_FILTER);
1086     value |= GMAC_PACKET_FILTER_IPFE;
1087     writel(value, ioaddr + GMAC_PACKET_FILTER);
1088 
1089     value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1090 
1091     /* For IPv6 not both SA/DA filters can be active */
1092     if (ipv6) {
1093         value |= GMAC_L3PEN0;
1094         value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
1095         value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
1096         if (sa) {
1097             value |= GMAC_L3SAM0;
1098             if (inv)
1099                 value |= GMAC_L3SAIM0;
1100         } else {
1101             value |= GMAC_L3DAM0;
1102             if (inv)
1103                 value |= GMAC_L3DAIM0;
1104         }
1105     } else {
1106         value &= ~GMAC_L3PEN0;
1107         if (sa) {
1108             value |= GMAC_L3SAM0;
1109             if (inv)
1110                 value |= GMAC_L3SAIM0;
1111         } else {
1112             value |= GMAC_L3DAM0;
1113             if (inv)
1114                 value |= GMAC_L3DAIM0;
1115         }
1116     }
1117 
1118     writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1119 
1120     if (sa) {
1121         writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
1122     } else {
1123         writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
1124     }
1125 
1126     if (!en)
1127         writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1128 
1129     return 0;
1130 }
1131 
1132 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1133                    bool en, bool udp, bool sa, bool inv,
1134                    u32 match)
1135 {
1136     void __iomem *ioaddr = hw->pcsr;
1137     u32 value;
1138 
1139     value = readl(ioaddr + GMAC_PACKET_FILTER);
1140     value |= GMAC_PACKET_FILTER_IPFE;
1141     writel(value, ioaddr + GMAC_PACKET_FILTER);
1142 
1143     value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1144     if (udp) {
1145         value |= GMAC_L4PEN0;
1146     } else {
1147         value &= ~GMAC_L4PEN0;
1148     }
1149 
1150     value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
1151     value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
1152     if (sa) {
1153         value |= GMAC_L4SPM0;
1154         if (inv)
1155             value |= GMAC_L4SPIM0;
1156     } else {
1157         value |= GMAC_L4DPM0;
1158         if (inv)
1159             value |= GMAC_L4DPIM0;
1160     }
1161 
1162     writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1163 
1164     if (sa) {
1165         value = match & GMAC_L4SP0;
1166     } else {
1167         value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
1168     }
1169 
1170     writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
1171 
1172     if (!en)
1173         writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1174 
1175     return 0;
1176 }
1177 
1178 const struct stmmac_ops dwmac4_ops = {
1179     .core_init = dwmac4_core_init,
1180     .set_mac = stmmac_set_mac,
1181     .rx_ipc = dwmac4_rx_ipc_enable,
1182     .rx_queue_enable = dwmac4_rx_queue_enable,
1183     .rx_queue_prio = dwmac4_rx_queue_priority,
1184     .tx_queue_prio = dwmac4_tx_queue_priority,
1185     .rx_queue_routing = dwmac4_rx_queue_routing,
1186     .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1187     .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1188     .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1189     .map_mtl_to_dma = dwmac4_map_mtl_dma,
1190     .config_cbs = dwmac4_config_cbs,
1191     .dump_regs = dwmac4_dump_regs,
1192     .host_irq_status = dwmac4_irq_status,
1193     .host_mtl_irq_status = dwmac4_irq_mtl_status,
1194     .flow_ctrl = dwmac4_flow_ctrl,
1195     .pmt = dwmac4_pmt,
1196     .set_umac_addr = dwmac4_set_umac_addr,
1197     .get_umac_addr = dwmac4_get_umac_addr,
1198     .set_eee_mode = dwmac4_set_eee_mode,
1199     .reset_eee_mode = dwmac4_reset_eee_mode,
1200     .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1201     .set_eee_timer = dwmac4_set_eee_timer,
1202     .set_eee_pls = dwmac4_set_eee_pls,
1203     .pcs_ctrl_ane = dwmac4_ctrl_ane,
1204     .pcs_rane = dwmac4_rane,
1205     .pcs_get_adv_lp = dwmac4_get_adv_lp,
1206     .debug = dwmac4_debug,
1207     .set_filter = dwmac4_set_filter,
1208     .set_mac_loopback = dwmac4_set_mac_loopback,
1209     .update_vlan_hash = dwmac4_update_vlan_hash,
1210     .sarc_configure = dwmac4_sarc_configure,
1211     .enable_vlan = dwmac4_enable_vlan,
1212     .set_arp_offload = dwmac4_set_arp_offload,
1213     .config_l3_filter = dwmac4_config_l3_filter,
1214     .config_l4_filter = dwmac4_config_l4_filter,
1215     .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1216     .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1217     .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1218 };
1219 
1220 const struct stmmac_ops dwmac410_ops = {
1221     .core_init = dwmac4_core_init,
1222     .set_mac = stmmac_dwmac4_set_mac,
1223     .rx_ipc = dwmac4_rx_ipc_enable,
1224     .rx_queue_enable = dwmac4_rx_queue_enable,
1225     .rx_queue_prio = dwmac4_rx_queue_priority,
1226     .tx_queue_prio = dwmac4_tx_queue_priority,
1227     .rx_queue_routing = dwmac4_rx_queue_routing,
1228     .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1229     .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1230     .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1231     .map_mtl_to_dma = dwmac4_map_mtl_dma,
1232     .config_cbs = dwmac4_config_cbs,
1233     .dump_regs = dwmac4_dump_regs,
1234     .host_irq_status = dwmac4_irq_status,
1235     .host_mtl_irq_status = dwmac4_irq_mtl_status,
1236     .flow_ctrl = dwmac4_flow_ctrl,
1237     .pmt = dwmac4_pmt,
1238     .set_umac_addr = dwmac4_set_umac_addr,
1239     .get_umac_addr = dwmac4_get_umac_addr,
1240     .set_eee_mode = dwmac4_set_eee_mode,
1241     .reset_eee_mode = dwmac4_reset_eee_mode,
1242     .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1243     .set_eee_timer = dwmac4_set_eee_timer,
1244     .set_eee_pls = dwmac4_set_eee_pls,
1245     .pcs_ctrl_ane = dwmac4_ctrl_ane,
1246     .pcs_rane = dwmac4_rane,
1247     .pcs_get_adv_lp = dwmac4_get_adv_lp,
1248     .debug = dwmac4_debug,
1249     .set_filter = dwmac4_set_filter,
1250     .flex_pps_config = dwmac5_flex_pps_config,
1251     .set_mac_loopback = dwmac4_set_mac_loopback,
1252     .update_vlan_hash = dwmac4_update_vlan_hash,
1253     .sarc_configure = dwmac4_sarc_configure,
1254     .enable_vlan = dwmac4_enable_vlan,
1255     .set_arp_offload = dwmac4_set_arp_offload,
1256     .config_l3_filter = dwmac4_config_l3_filter,
1257     .config_l4_filter = dwmac4_config_l4_filter,
1258     .est_configure = dwmac5_est_configure,
1259     .est_irq_status = dwmac5_est_irq_status,
1260     .fpe_configure = dwmac5_fpe_configure,
1261     .fpe_send_mpacket = dwmac5_fpe_send_mpacket,
1262     .fpe_irq_status = dwmac5_fpe_irq_status,
1263     .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1264     .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1265     .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1266 };
1267 
1268 const struct stmmac_ops dwmac510_ops = {
1269     .core_init = dwmac4_core_init,
1270     .set_mac = stmmac_dwmac4_set_mac,
1271     .rx_ipc = dwmac4_rx_ipc_enable,
1272     .rx_queue_enable = dwmac4_rx_queue_enable,
1273     .rx_queue_prio = dwmac4_rx_queue_priority,
1274     .tx_queue_prio = dwmac4_tx_queue_priority,
1275     .rx_queue_routing = dwmac4_rx_queue_routing,
1276     .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1277     .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1278     .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1279     .map_mtl_to_dma = dwmac4_map_mtl_dma,
1280     .config_cbs = dwmac4_config_cbs,
1281     .dump_regs = dwmac4_dump_regs,
1282     .host_irq_status = dwmac4_irq_status,
1283     .host_mtl_irq_status = dwmac4_irq_mtl_status,
1284     .flow_ctrl = dwmac4_flow_ctrl,
1285     .pmt = dwmac4_pmt,
1286     .set_umac_addr = dwmac4_set_umac_addr,
1287     .get_umac_addr = dwmac4_get_umac_addr,
1288     .set_eee_mode = dwmac4_set_eee_mode,
1289     .reset_eee_mode = dwmac4_reset_eee_mode,
1290     .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1291     .set_eee_timer = dwmac4_set_eee_timer,
1292     .set_eee_pls = dwmac4_set_eee_pls,
1293     .pcs_ctrl_ane = dwmac4_ctrl_ane,
1294     .pcs_rane = dwmac4_rane,
1295     .pcs_get_adv_lp = dwmac4_get_adv_lp,
1296     .debug = dwmac4_debug,
1297     .set_filter = dwmac4_set_filter,
1298     .safety_feat_config = dwmac5_safety_feat_config,
1299     .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1300     .safety_feat_dump = dwmac5_safety_feat_dump,
1301     .rxp_config = dwmac5_rxp_config,
1302     .flex_pps_config = dwmac5_flex_pps_config,
1303     .set_mac_loopback = dwmac4_set_mac_loopback,
1304     .update_vlan_hash = dwmac4_update_vlan_hash,
1305     .sarc_configure = dwmac4_sarc_configure,
1306     .enable_vlan = dwmac4_enable_vlan,
1307     .set_arp_offload = dwmac4_set_arp_offload,
1308     .config_l3_filter = dwmac4_config_l3_filter,
1309     .config_l4_filter = dwmac4_config_l4_filter,
1310     .est_configure = dwmac5_est_configure,
1311     .est_irq_status = dwmac5_est_irq_status,
1312     .fpe_configure = dwmac5_fpe_configure,
1313     .fpe_send_mpacket = dwmac5_fpe_send_mpacket,
1314     .fpe_irq_status = dwmac5_fpe_irq_status,
1315     .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1316     .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1317     .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1318 };
1319 
1320 static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
1321 {
1322     u32 val, num_vlan;
1323 
1324     val = readl(ioaddr + GMAC_HW_FEATURE3);
1325     switch (val & GMAC_HW_FEAT_NRVF) {
1326     case 0:
1327         num_vlan = 1;
1328         break;
1329     case 1:
1330         num_vlan = 4;
1331         break;
1332     case 2:
1333         num_vlan = 8;
1334         break;
1335     case 3:
1336         num_vlan = 16;
1337         break;
1338     case 4:
1339         num_vlan = 24;
1340         break;
1341     case 5:
1342         num_vlan = 32;
1343         break;
1344     default:
1345         num_vlan = 1;
1346     }
1347 
1348     return num_vlan;
1349 }
1350 
1351 int dwmac4_setup(struct stmmac_priv *priv)
1352 {
1353     struct mac_device_info *mac = priv->hw;
1354 
1355     dev_info(priv->device, "\tDWMAC4/5\n");
1356 
1357     priv->dev->priv_flags |= IFF_UNICAST_FLT;
1358     mac->pcsr = priv->ioaddr;
1359     mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1360     mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1361     mac->mcast_bits_log2 = 0;
1362 
1363     if (mac->multicast_filter_bins)
1364         mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1365 
1366     mac->link.duplex = GMAC_CONFIG_DM;
1367     mac->link.speed10 = GMAC_CONFIG_PS;
1368     mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1369     mac->link.speed1000 = 0;
1370     mac->link.speed2500 = GMAC_CONFIG_FES;
1371     mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1372     mac->mii.addr = GMAC_MDIO_ADDR;
1373     mac->mii.data = GMAC_MDIO_DATA;
1374     mac->mii.addr_shift = 21;
1375     mac->mii.addr_mask = GENMASK(25, 21);
1376     mac->mii.reg_shift = 16;
1377     mac->mii.reg_mask = GENMASK(20, 16);
1378     mac->mii.clk_csr_shift = 8;
1379     mac->mii.clk_csr_mask = GENMASK(11, 8);
1380     mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);
1381 
1382     return 0;
1383 }
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