stmicro/stmmac/dwmac100_dma.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*******************************************************************************
0003   This is the driver for the MAC 10/100 on-chip Ethernet controller
0004   currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
0005
0006   DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
0007   this code.
0008
0009   This contains the functions to handle the dma.
0010
0011   Copyright (C) 2007-2009  STMicroelectronics Ltd
0012
0013
0014   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0015 *******************************************************************************/
0016
0017 #include <asm/io.h>
0018 #include "dwmac100.h"
0019 #include "dwmac_dma.h"
0020
0021 static void dwmac100_dma_init(void __iomem *ioaddr,
0022                   struct stmmac_dma_cfg *dma_cfg, int atds)
0023 {
0024     /* Enable Application Access by writing to DMA CSR0 */
0025     writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
0026            ioaddr + DMA_BUS_MODE);
0027
0028     /* Mask interrupts by writing to CSR7 */
0029     writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
0030 }
0031
0032 static void dwmac100_dma_init_rx(void __iomem *ioaddr,
0033                  struct stmmac_dma_cfg *dma_cfg,
0034                  dma_addr_t dma_rx_phy, u32 chan)
0035 {
0036     /* RX descriptor base addr lists must be written into DMA CSR3 */
0037     writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
0038 }
0039
0040 static void dwmac100_dma_init_tx(void __iomem *ioaddr,
0041                  struct stmmac_dma_cfg *dma_cfg,
0042                  dma_addr_t dma_tx_phy, u32 chan)
0043 {
0044     /* TX descriptor base addr lists must be written into DMA CSR4 */
0045     writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
0046 }
0047
0048 /* Store and Forward capability is not used at all.
0049  *
0050  * The transmit threshold can be programmed by setting the TTC bits in the DMA
0051  * control register.
0052  */
0053 static void dwmac100_dma_operation_mode_tx(void __iomem *ioaddr, int mode,
0054                        u32 channel, int fifosz, u8 qmode)
0055 {
0056     u32 csr6 = readl(ioaddr + DMA_CONTROL);
0057
0058     if (mode <= 32)
0059         csr6 |= DMA_CONTROL_TTC_32;
0060     else if (mode <= 64)
0061         csr6 |= DMA_CONTROL_TTC_64;
0062     else
0063         csr6 |= DMA_CONTROL_TTC_128;
0064
0065     writel(csr6, ioaddr + DMA_CONTROL);
0066 }
0067
0068 static void dwmac100_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
0069 {
0070     int i;
0071
0072     for (i = 0; i < NUM_DWMAC100_DMA_REGS; i++)
0073         reg_space[DMA_BUS_MODE / 4 + i] =
0074             readl(ioaddr + DMA_BUS_MODE + i * 4);
0075
0076     reg_space[DMA_CUR_TX_BUF_ADDR / 4] =
0077         readl(ioaddr + DMA_CUR_TX_BUF_ADDR);
0078     reg_space[DMA_CUR_RX_BUF_ADDR / 4] =
0079         readl(ioaddr + DMA_CUR_RX_BUF_ADDR);
0080 }
0081
0082 /* DMA controller has two counters to track the number of the missed frames. */
0083 static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
0084                        void __iomem *ioaddr)
0085 {
0086     struct net_device_stats *stats = (struct net_device_stats *)data;
0087     u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);
0088
0089     if (unlikely(csr8)) {
0090         if (csr8 & DMA_MISSED_FRAME_OVE) {
0091             stats->rx_over_errors += 0x800;
0092             x->rx_overflow_cntr += 0x800;
0093         } else {
0094             unsigned int ove_cntr;
0095             ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
0096             stats->rx_over_errors += ove_cntr;
0097             x->rx_overflow_cntr += ove_cntr;
0098         }
0099
0100         if (csr8 & DMA_MISSED_FRAME_OVE_M) {
0101             stats->rx_missed_errors += 0xffff;
0102             x->rx_missed_cntr += 0xffff;
0103         } else {
0104             unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
0105             stats->rx_missed_errors += miss_f;
0106             x->rx_missed_cntr += miss_f;
0107         }
0108     }
0109 }
0110
0111 const struct stmmac_dma_ops dwmac100_dma_ops = {
0112     .reset = dwmac_dma_reset,
0113     .init = dwmac100_dma_init,
0114     .init_rx_chan = dwmac100_dma_init_rx,
0115     .init_tx_chan = dwmac100_dma_init_tx,
0116     .dump_regs = dwmac100_dump_dma_regs,
0117     .dma_tx_mode = dwmac100_dma_operation_mode_tx,
0118     .dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
0119     .enable_dma_transmission = dwmac_enable_dma_transmission,
0120     .enable_dma_irq = dwmac_enable_dma_irq,
0121     .disable_dma_irq = dwmac_disable_dma_irq,
0122     .start_tx = dwmac_dma_start_tx,
0123     .stop_tx = dwmac_dma_stop_tx,
0124     .start_rx = dwmac_dma_start_rx,
0125     .stop_rx = dwmac_dma_stop_rx,
0126     .dma_interrupt = dwmac_dma_interrupt,
0127 };