stmicro/stmmac/dwmac100_core.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*******************************************************************************
0003   This is the driver for the MAC 10/100 on-chip Ethernet controller
0004   currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
0005
0006   DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
0007   this code.
0008
0009   This only implements the mac core functions for this chip.
0010
0011   Copyright (C) 2007-2009  STMicroelectronics Ltd
0012
0013
0014   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0015 *******************************************************************************/
0016
0017 #include <linux/crc32.h>
0018 #include <net/dsa.h>
0019 #include <asm/io.h>
0020 #include "stmmac.h"
0021 #include "dwmac100.h"
0022
0023 static void dwmac100_core_init(struct mac_device_info *hw,
0024                    struct net_device *dev)
0025 {
0026     void __iomem *ioaddr = hw->pcsr;
0027     u32 value = readl(ioaddr + MAC_CONTROL);
0028
0029     value |= MAC_CORE_INIT;
0030
0031     /* Clear ASTP bit because Ethernet switch tagging formats such as
0032      * Broadcom tags can look like invalid LLC/SNAP packets and cause the
0033      * hardware to truncate packets on reception.
0034      */
0035     if (netdev_uses_dsa(dev))
0036         value &= ~MAC_CONTROL_ASTP;
0037
0038     writel(value, ioaddr + MAC_CONTROL);
0039
0040 #ifdef STMMAC_VLAN_TAG_USED
0041     writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
0042 #endif
0043 }
0044
0045 static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)
0046 {
0047     void __iomem *ioaddr = hw->pcsr;
0048
0049     reg_space[MAC_CONTROL / 4] = readl(ioaddr + MAC_CONTROL);
0050     reg_space[MAC_ADDR_HIGH / 4] = readl(ioaddr + MAC_ADDR_HIGH);
0051     reg_space[MAC_ADDR_LOW / 4] = readl(ioaddr + MAC_ADDR_LOW);
0052     reg_space[MAC_HASH_HIGH / 4] = readl(ioaddr + MAC_HASH_HIGH);
0053     reg_space[MAC_HASH_LOW / 4] = readl(ioaddr + MAC_HASH_LOW);
0054     reg_space[MAC_FLOW_CTRL / 4] = readl(ioaddr + MAC_FLOW_CTRL);
0055     reg_space[MAC_VLAN1 / 4] = readl(ioaddr + MAC_VLAN1);
0056     reg_space[MAC_VLAN2 / 4] = readl(ioaddr + MAC_VLAN2);
0057 }
0058
0059 static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
0060 {
0061     return 0;
0062 }
0063
0064 static int dwmac100_irq_status(struct mac_device_info *hw,
0065                    struct stmmac_extra_stats *x)
0066 {
0067     return 0;
0068 }
0069
0070 static void dwmac100_set_umac_addr(struct mac_device_info *hw,
0071                    const unsigned char *addr,
0072                    unsigned int reg_n)
0073 {
0074     void __iomem *ioaddr = hw->pcsr;
0075     stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
0076 }
0077
0078 static void dwmac100_get_umac_addr(struct mac_device_info *hw,
0079                    unsigned char *addr,
0080                    unsigned int reg_n)
0081 {
0082     void __iomem *ioaddr = hw->pcsr;
0083     stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
0084 }
0085
0086 static void dwmac100_set_filter(struct mac_device_info *hw,
0087                 struct net_device *dev)
0088 {
0089     void __iomem *ioaddr = (void __iomem *)dev->base_addr;
0090     u32 value = readl(ioaddr + MAC_CONTROL);
0091
0092     if (dev->flags & IFF_PROMISC) {
0093         value |= MAC_CONTROL_PR;
0094         value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
0095                MAC_CONTROL_HP);
0096     } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
0097            || (dev->flags & IFF_ALLMULTI)) {
0098         value |= MAC_CONTROL_PM;
0099         value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
0100         writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
0101         writel(0xffffffff, ioaddr + MAC_HASH_LOW);
0102     } else if (netdev_mc_empty(dev)) {  /* no multicast */
0103         value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
0104                MAC_CONTROL_HO | MAC_CONTROL_HP);
0105     } else {
0106         u32 mc_filter[2];
0107         struct netdev_hw_addr *ha;
0108
0109         /* Perfect filter mode for physical address and Hash
0110          * filter for multicast
0111          */
0112         value |= MAC_CONTROL_HP;
0113         value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
0114                MAC_CONTROL_IF | MAC_CONTROL_HO);
0115
0116         memset(mc_filter, 0, sizeof(mc_filter));
0117         netdev_for_each_mc_addr(ha, dev) {
0118             /* The upper 6 bits of the calculated CRC are used to
0119              * index the contens of the hash table
0120              */
0121             int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
0122             /* The most significant bit determines the register to
0123              * use (H/L) while the other 5 bits determine the bit
0124              * within the register.
0125              */
0126             mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
0127         }
0128         writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
0129         writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
0130     }
0131
0132     writel(value, ioaddr + MAC_CONTROL);
0133 }
0134
0135 static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
0136                    unsigned int fc, unsigned int pause_time,
0137                    u32 tx_cnt)
0138 {
0139     void __iomem *ioaddr = hw->pcsr;
0140     unsigned int flow = MAC_FLOW_CTRL_ENABLE;
0141
0142     if (duplex)
0143         flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
0144     writel(flow, ioaddr + MAC_FLOW_CTRL);
0145 }
0146
0147 /* No PMT module supported on ST boards with this Eth chip. */
0148 static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
0149 {
0150     return;
0151 }
0152
0153 static void dwmac100_set_mac_loopback(void __iomem *ioaddr, bool enable)
0154 {
0155     u32 value = readl(ioaddr + MAC_CONTROL);
0156
0157     if (enable)
0158         value |= MAC_CONTROL_OM;
0159     else
0160         value &= ~MAC_CONTROL_OM;
0161
0162     writel(value, ioaddr + MAC_CONTROL);
0163 }
0164
0165 const struct stmmac_ops dwmac100_ops = {
0166     .core_init = dwmac100_core_init,
0167     .set_mac = stmmac_set_mac,
0168     .rx_ipc = dwmac100_rx_ipc_enable,
0169     .dump_regs = dwmac100_dump_mac_regs,
0170     .host_irq_status = dwmac100_irq_status,
0171     .set_filter = dwmac100_set_filter,
0172     .flow_ctrl = dwmac100_flow_ctrl,
0173     .pmt = dwmac100_pmt,
0174     .set_umac_addr = dwmac100_set_umac_addr,
0175     .get_umac_addr = dwmac100_get_umac_addr,
0176     .set_mac_loopback = dwmac100_set_mac_loopback,
0177 };
0178
0179 int dwmac100_setup(struct stmmac_priv *priv)
0180 {
0181     struct mac_device_info *mac = priv->hw;
0182
0183     dev_info(priv->device, "\tDWMAC100\n");
0184
0185     mac->pcsr = priv->ioaddr;
0186     mac->link.duplex = MAC_CONTROL_F;
0187     mac->link.speed10 = 0;
0188     mac->link.speed100 = 0;
0189     mac->link.speed1000 = 0;
0190     mac->link.speed_mask = MAC_CONTROL_PS;
0191     mac->mii.addr = MAC_MII_ADDR;
0192     mac->mii.data = MAC_MII_DATA;
0193     mac->mii.addr_shift = 11;
0194     mac->mii.addr_mask = 0x0000F800;
0195     mac->mii.reg_shift = 6;
0196     mac->mii.reg_mask = 0x000007C0;
0197     mac->mii.clk_csr_shift = 2;
0198     mac->mii.clk_csr_mask = GENMASK(5, 2);
0199
0200     return 0;
0201 }