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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*******************************************************************************
0003   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
0004   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
0005   developing this code.
0006 
0007   This only implements the mac core functions for this chip.
0008 
0009   Copyright (C) 2007-2009  STMicroelectronics Ltd
0010 
0011 
0012   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0013 *******************************************************************************/
0014 
0015 #include <linux/crc32.h>
0016 #include <linux/slab.h>
0017 #include <linux/ethtool.h>
0018 #include <net/dsa.h>
0019 #include <asm/io.h>
0020 #include "stmmac.h"
0021 #include "stmmac_pcs.h"
0022 #include "dwmac1000.h"
0023 
0024 static void dwmac1000_core_init(struct mac_device_info *hw,
0025                 struct net_device *dev)
0026 {
0027     struct stmmac_priv *priv = netdev_priv(dev);
0028     void __iomem *ioaddr = hw->pcsr;
0029     u32 value = readl(ioaddr + GMAC_CONTROL);
0030     int mtu = dev->mtu;
0031 
0032     /* Configure GMAC core */
0033     value |= GMAC_CORE_INIT;
0034 
0035     /* Clear ACS bit because Ethernet switch tagging formats such as
0036      * Broadcom tags can look like invalid LLC/SNAP packets and cause the
0037      * hardware to truncate packets on reception.
0038      */
0039     if (netdev_uses_dsa(dev) || !priv->plat->enh_desc)
0040         value &= ~GMAC_CONTROL_ACS;
0041 
0042     if (mtu > 1500)
0043         value |= GMAC_CONTROL_2K;
0044     if (mtu > 2000)
0045         value |= GMAC_CONTROL_JE;
0046 
0047     if (hw->ps) {
0048         value |= GMAC_CONTROL_TE;
0049 
0050         value &= ~hw->link.speed_mask;
0051         switch (hw->ps) {
0052         case SPEED_1000:
0053             value |= hw->link.speed1000;
0054             break;
0055         case SPEED_100:
0056             value |= hw->link.speed100;
0057             break;
0058         case SPEED_10:
0059             value |= hw->link.speed10;
0060             break;
0061         }
0062     }
0063 
0064     writel(value, ioaddr + GMAC_CONTROL);
0065 
0066     /* Mask GMAC interrupts */
0067     value = GMAC_INT_DEFAULT_MASK;
0068 
0069     if (hw->pcs)
0070         value &= ~GMAC_INT_DISABLE_PCS;
0071 
0072     writel(value, ioaddr + GMAC_INT_MASK);
0073 
0074 #ifdef STMMAC_VLAN_TAG_USED
0075     /* Tag detection without filtering */
0076     writel(0x0, ioaddr + GMAC_VLAN_TAG);
0077 #endif
0078 }
0079 
0080 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
0081 {
0082     void __iomem *ioaddr = hw->pcsr;
0083     u32 value = readl(ioaddr + GMAC_CONTROL);
0084 
0085     if (hw->rx_csum)
0086         value |= GMAC_CONTROL_IPC;
0087     else
0088         value &= ~GMAC_CONTROL_IPC;
0089 
0090     writel(value, ioaddr + GMAC_CONTROL);
0091 
0092     value = readl(ioaddr + GMAC_CONTROL);
0093 
0094     return !!(value & GMAC_CONTROL_IPC);
0095 }
0096 
0097 static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
0098 {
0099     void __iomem *ioaddr = hw->pcsr;
0100     int i;
0101 
0102     for (i = 0; i < 55; i++)
0103         reg_space[i] = readl(ioaddr + i * 4);
0104 }
0105 
0106 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
0107                     const unsigned char *addr,
0108                     unsigned int reg_n)
0109 {
0110     void __iomem *ioaddr = hw->pcsr;
0111     stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
0112                 GMAC_ADDR_LOW(reg_n));
0113 }
0114 
0115 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
0116                     unsigned char *addr,
0117                     unsigned int reg_n)
0118 {
0119     void __iomem *ioaddr = hw->pcsr;
0120     stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
0121                 GMAC_ADDR_LOW(reg_n));
0122 }
0123 
0124 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
0125                  int mcbitslog2)
0126 {
0127     int numhashregs, regs;
0128 
0129     switch (mcbitslog2) {
0130     case 6:
0131         writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
0132         writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
0133         return;
0134     case 7:
0135         numhashregs = 4;
0136         break;
0137     case 8:
0138         numhashregs = 8;
0139         break;
0140     default:
0141         pr_debug("STMMAC: err in setting multicast filter\n");
0142         return;
0143     }
0144     for (regs = 0; regs < numhashregs; regs++)
0145         writel(mcfilterbits[regs],
0146                ioaddr + GMAC_EXTHASH_BASE + regs * 4);
0147 }
0148 
0149 static void dwmac1000_set_filter(struct mac_device_info *hw,
0150                  struct net_device *dev)
0151 {
0152     void __iomem *ioaddr = (void __iomem *)dev->base_addr;
0153     unsigned int value = 0;
0154     unsigned int perfect_addr_number = hw->unicast_filter_entries;
0155     u32 mc_filter[8];
0156     int mcbitslog2 = hw->mcast_bits_log2;
0157 
0158     pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
0159          netdev_mc_count(dev), netdev_uc_count(dev));
0160 
0161     memset(mc_filter, 0, sizeof(mc_filter));
0162 
0163     if (dev->flags & IFF_PROMISC) {
0164         value = GMAC_FRAME_FILTER_PR | GMAC_FRAME_FILTER_PCF;
0165     } else if (dev->flags & IFF_ALLMULTI) {
0166         value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
0167     } else if (!netdev_mc_empty(dev) && (mcbitslog2 == 0)) {
0168         /* Fall back to all multicast if we've no filter */
0169         value = GMAC_FRAME_FILTER_PM;
0170     } else if (!netdev_mc_empty(dev)) {
0171         struct netdev_hw_addr *ha;
0172 
0173         /* Hash filter for multicast */
0174         value = GMAC_FRAME_FILTER_HMC;
0175 
0176         netdev_for_each_mc_addr(ha, dev) {
0177             /* The upper n bits of the calculated CRC are used to
0178              * index the contents of the hash table. The number of
0179              * bits used depends on the hardware configuration
0180              * selected at core configuration time.
0181              */
0182             int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
0183                           ETH_ALEN)) >>
0184                           (32 - mcbitslog2);
0185             /* The most significant bit determines the register to
0186              * use (H/L) while the other 5 bits determine the bit
0187              * within the register.
0188              */
0189             mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
0190         }
0191     }
0192 
0193     value |= GMAC_FRAME_FILTER_HPF;
0194     dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
0195 
0196     /* Handle multiple unicast addresses (perfect filtering) */
0197     if (netdev_uc_count(dev) > perfect_addr_number)
0198         /* Switch to promiscuous mode if more than unicast
0199          * addresses are requested than supported by hardware.
0200          */
0201         value |= GMAC_FRAME_FILTER_PR;
0202     else {
0203         int reg = 1;
0204         struct netdev_hw_addr *ha;
0205 
0206         netdev_for_each_uc_addr(ha, dev) {
0207             stmmac_set_mac_addr(ioaddr, ha->addr,
0208                         GMAC_ADDR_HIGH(reg),
0209                         GMAC_ADDR_LOW(reg));
0210             reg++;
0211         }
0212 
0213         while (reg < perfect_addr_number) {
0214             writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
0215             writel(0, ioaddr + GMAC_ADDR_LOW(reg));
0216             reg++;
0217         }
0218     }
0219 
0220 #ifdef FRAME_FILTER_DEBUG
0221     /* Enable Receive all mode (to debug filtering_fail errors) */
0222     value |= GMAC_FRAME_FILTER_RA;
0223 #endif
0224     writel(value, ioaddr + GMAC_FRAME_FILTER);
0225 }
0226 
0227 
0228 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
0229                 unsigned int fc, unsigned int pause_time,
0230                 u32 tx_cnt)
0231 {
0232     void __iomem *ioaddr = hw->pcsr;
0233     /* Set flow such that DZPQ in Mac Register 6 is 0,
0234      * and unicast pause detect is enabled.
0235      */
0236     unsigned int flow = GMAC_FLOW_CTRL_UP;
0237 
0238     pr_debug("GMAC Flow-Control:\n");
0239     if (fc & FLOW_RX) {
0240         pr_debug("\tReceive Flow-Control ON\n");
0241         flow |= GMAC_FLOW_CTRL_RFE;
0242     }
0243     if (fc & FLOW_TX) {
0244         pr_debug("\tTransmit Flow-Control ON\n");
0245         flow |= GMAC_FLOW_CTRL_TFE;
0246     }
0247 
0248     if (duplex) {
0249         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
0250         flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
0251     }
0252 
0253     writel(flow, ioaddr + GMAC_FLOW_CTRL);
0254 }
0255 
0256 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
0257 {
0258     void __iomem *ioaddr = hw->pcsr;
0259     unsigned int pmt = 0;
0260 
0261     if (mode & WAKE_MAGIC) {
0262         pr_debug("GMAC: WOL Magic frame\n");
0263         pmt |= power_down | magic_pkt_en;
0264     }
0265     if (mode & WAKE_UCAST) {
0266         pr_debug("GMAC: WOL on global unicast\n");
0267         pmt |= power_down | global_unicast | wake_up_frame_en;
0268     }
0269 
0270     writel(pmt, ioaddr + GMAC_PMT);
0271 }
0272 
0273 /* RGMII or SMII interface */
0274 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
0275 {
0276     u32 status;
0277 
0278     status = readl(ioaddr + GMAC_RGSMIIIS);
0279     x->irq_rgmii_n++;
0280 
0281     /* Check the link status */
0282     if (status & GMAC_RGSMIIIS_LNKSTS) {
0283         int speed_value;
0284 
0285         x->pcs_link = 1;
0286 
0287         speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
0288                    GMAC_RGSMIIIS_SPEED_SHIFT);
0289         if (speed_value == GMAC_RGSMIIIS_SPEED_125)
0290             x->pcs_speed = SPEED_1000;
0291         else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
0292             x->pcs_speed = SPEED_100;
0293         else
0294             x->pcs_speed = SPEED_10;
0295 
0296         x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
0297 
0298         pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
0299             x->pcs_duplex ? "Full" : "Half");
0300     } else {
0301         x->pcs_link = 0;
0302         pr_info("Link is Down\n");
0303     }
0304 }
0305 
0306 static int dwmac1000_irq_status(struct mac_device_info *hw,
0307                 struct stmmac_extra_stats *x)
0308 {
0309     void __iomem *ioaddr = hw->pcsr;
0310     u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
0311     u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
0312     int ret = 0;
0313 
0314     /* Discard masked bits */
0315     intr_status &= ~intr_mask;
0316 
0317     /* Not used events (e.g. MMC interrupts) are not handled. */
0318     if ((intr_status & GMAC_INT_STATUS_MMCTIS))
0319         x->mmc_tx_irq_n++;
0320     if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
0321         x->mmc_rx_irq_n++;
0322     if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
0323         x->mmc_rx_csum_offload_irq_n++;
0324     if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
0325         /* clear the PMT bits 5 and 6 by reading the PMT status reg */
0326         readl(ioaddr + GMAC_PMT);
0327         x->irq_receive_pmt_irq_n++;
0328     }
0329 
0330     /* MAC tx/rx EEE LPI entry/exit interrupts */
0331     if (intr_status & GMAC_INT_STATUS_LPIIS) {
0332         /* Clean LPI interrupt by reading the Reg 12 */
0333         ret = readl(ioaddr + LPI_CTRL_STATUS);
0334 
0335         if (ret & LPI_CTRL_STATUS_TLPIEN)
0336             x->irq_tx_path_in_lpi_mode_n++;
0337         if (ret & LPI_CTRL_STATUS_TLPIEX)
0338             x->irq_tx_path_exit_lpi_mode_n++;
0339         if (ret & LPI_CTRL_STATUS_RLPIEN)
0340             x->irq_rx_path_in_lpi_mode_n++;
0341         if (ret & LPI_CTRL_STATUS_RLPIEX)
0342             x->irq_rx_path_exit_lpi_mode_n++;
0343     }
0344 
0345     dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
0346 
0347     if (intr_status & PCS_RGSMIIIS_IRQ)
0348         dwmac1000_rgsmii(ioaddr, x);
0349 
0350     return ret;
0351 }
0352 
0353 static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
0354                    bool en_tx_lpi_clockgating)
0355 {
0356     void __iomem *ioaddr = hw->pcsr;
0357     u32 value;
0358 
0359     /*TODO - en_tx_lpi_clockgating treatment */
0360 
0361     /* Enable the link status receive on RGMII, SGMII ore SMII
0362      * receive path and instruct the transmit to enter in LPI
0363      * state.
0364      */
0365     value = readl(ioaddr + LPI_CTRL_STATUS);
0366     value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
0367     writel(value, ioaddr + LPI_CTRL_STATUS);
0368 }
0369 
0370 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
0371 {
0372     void __iomem *ioaddr = hw->pcsr;
0373     u32 value;
0374 
0375     value = readl(ioaddr + LPI_CTRL_STATUS);
0376     value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
0377     writel(value, ioaddr + LPI_CTRL_STATUS);
0378 }
0379 
0380 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
0381 {
0382     void __iomem *ioaddr = hw->pcsr;
0383     u32 value;
0384 
0385     value = readl(ioaddr + LPI_CTRL_STATUS);
0386 
0387     if (link)
0388         value |= LPI_CTRL_STATUS_PLS;
0389     else
0390         value &= ~LPI_CTRL_STATUS_PLS;
0391 
0392     writel(value, ioaddr + LPI_CTRL_STATUS);
0393 }
0394 
0395 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
0396 {
0397     void __iomem *ioaddr = hw->pcsr;
0398     int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
0399 
0400     /* Program the timers in the LPI timer control register:
0401      * LS: minimum time (ms) for which the link
0402      *  status from PHY should be ok before transmitting
0403      *  the LPI pattern.
0404      * TW: minimum time (us) for which the core waits
0405      *  after it has stopped transmitting the LPI pattern.
0406      */
0407     writel(value, ioaddr + LPI_TIMER_CTRL);
0408 }
0409 
0410 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
0411                    bool loopback)
0412 {
0413     dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
0414 }
0415 
0416 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
0417 {
0418     dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
0419 }
0420 
0421 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
0422 {
0423     dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
0424 }
0425 
0426 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
0427                 u32 rx_queues, u32 tx_queues)
0428 {
0429     u32 value = readl(ioaddr + GMAC_DEBUG);
0430 
0431     if (value & GMAC_DEBUG_TXSTSFSTS)
0432         x->mtl_tx_status_fifo_full++;
0433     if (value & GMAC_DEBUG_TXFSTS)
0434         x->mtl_tx_fifo_not_empty++;
0435     if (value & GMAC_DEBUG_TWCSTS)
0436         x->mmtl_fifo_ctrl++;
0437     if (value & GMAC_DEBUG_TRCSTS_MASK) {
0438         u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
0439                  >> GMAC_DEBUG_TRCSTS_SHIFT;
0440         if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
0441             x->mtl_tx_fifo_read_ctrl_write++;
0442         else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
0443             x->mtl_tx_fifo_read_ctrl_wait++;
0444         else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
0445             x->mtl_tx_fifo_read_ctrl_read++;
0446         else
0447             x->mtl_tx_fifo_read_ctrl_idle++;
0448     }
0449     if (value & GMAC_DEBUG_TXPAUSED)
0450         x->mac_tx_in_pause++;
0451     if (value & GMAC_DEBUG_TFCSTS_MASK) {
0452         u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
0453                   >> GMAC_DEBUG_TFCSTS_SHIFT;
0454 
0455         if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
0456             x->mac_tx_frame_ctrl_xfer++;
0457         else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
0458             x->mac_tx_frame_ctrl_pause++;
0459         else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
0460             x->mac_tx_frame_ctrl_wait++;
0461         else
0462             x->mac_tx_frame_ctrl_idle++;
0463     }
0464     if (value & GMAC_DEBUG_TPESTS)
0465         x->mac_gmii_tx_proto_engine++;
0466     if (value & GMAC_DEBUG_RXFSTS_MASK) {
0467         u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
0468                  >> GMAC_DEBUG_RRCSTS_SHIFT;
0469 
0470         if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
0471             x->mtl_rx_fifo_fill_level_full++;
0472         else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
0473             x->mtl_rx_fifo_fill_above_thresh++;
0474         else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
0475             x->mtl_rx_fifo_fill_below_thresh++;
0476         else
0477             x->mtl_rx_fifo_fill_level_empty++;
0478     }
0479     if (value & GMAC_DEBUG_RRCSTS_MASK) {
0480         u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
0481                  GMAC_DEBUG_RRCSTS_SHIFT;
0482 
0483         if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
0484             x->mtl_rx_fifo_read_ctrl_flush++;
0485         else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
0486             x->mtl_rx_fifo_read_ctrl_read_data++;
0487         else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
0488             x->mtl_rx_fifo_read_ctrl_status++;
0489         else
0490             x->mtl_rx_fifo_read_ctrl_idle++;
0491     }
0492     if (value & GMAC_DEBUG_RWCSTS)
0493         x->mtl_rx_fifo_ctrl_active++;
0494     if (value & GMAC_DEBUG_RFCFCSTS_MASK)
0495         x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
0496                         >> GMAC_DEBUG_RFCFCSTS_SHIFT;
0497     if (value & GMAC_DEBUG_RPESTS)
0498         x->mac_gmii_rx_proto_engine++;
0499 }
0500 
0501 static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
0502 {
0503     u32 value = readl(ioaddr + GMAC_CONTROL);
0504 
0505     if (enable)
0506         value |= GMAC_CONTROL_LM;
0507     else
0508         value &= ~GMAC_CONTROL_LM;
0509 
0510     writel(value, ioaddr + GMAC_CONTROL);
0511 }
0512 
0513 const struct stmmac_ops dwmac1000_ops = {
0514     .core_init = dwmac1000_core_init,
0515     .set_mac = stmmac_set_mac,
0516     .rx_ipc = dwmac1000_rx_ipc_enable,
0517     .dump_regs = dwmac1000_dump_regs,
0518     .host_irq_status = dwmac1000_irq_status,
0519     .set_filter = dwmac1000_set_filter,
0520     .flow_ctrl = dwmac1000_flow_ctrl,
0521     .pmt = dwmac1000_pmt,
0522     .set_umac_addr = dwmac1000_set_umac_addr,
0523     .get_umac_addr = dwmac1000_get_umac_addr,
0524     .set_eee_mode = dwmac1000_set_eee_mode,
0525     .reset_eee_mode = dwmac1000_reset_eee_mode,
0526     .set_eee_timer = dwmac1000_set_eee_timer,
0527     .set_eee_pls = dwmac1000_set_eee_pls,
0528     .debug = dwmac1000_debug,
0529     .pcs_ctrl_ane = dwmac1000_ctrl_ane,
0530     .pcs_rane = dwmac1000_rane,
0531     .pcs_get_adv_lp = dwmac1000_get_adv_lp,
0532     .set_mac_loopback = dwmac1000_set_mac_loopback,
0533 };
0534 
0535 int dwmac1000_setup(struct stmmac_priv *priv)
0536 {
0537     struct mac_device_info *mac = priv->hw;
0538 
0539     dev_info(priv->device, "\tDWMAC1000\n");
0540 
0541     priv->dev->priv_flags |= IFF_UNICAST_FLT;
0542     mac->pcsr = priv->ioaddr;
0543     mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
0544     mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
0545     mac->mcast_bits_log2 = 0;
0546 
0547     if (mac->multicast_filter_bins)
0548         mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
0549 
0550     mac->link.duplex = GMAC_CONTROL_DM;
0551     mac->link.speed10 = GMAC_CONTROL_PS;
0552     mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
0553     mac->link.speed1000 = 0;
0554     mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
0555     mac->mii.addr = GMAC_MII_ADDR;
0556     mac->mii.data = GMAC_MII_DATA;
0557     mac->mii.addr_shift = 11;
0558     mac->mii.addr_mask = 0x0000F800;
0559     mac->mii.reg_shift = 6;
0560     mac->mii.reg_mask = 0x000007C0;
0561     mac->mii.clk_csr_shift = 2;
0562     mac->mii.clk_csr_mask = GENMASK(5, 2);
0563 
0564     return 0;
0565 }
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