stmicro/stmmac/dwmac1000.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*******************************************************************************
0003   Copyright (C) 2007-2009  STMicroelectronics Ltd
0004
0005
0006   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0007 *******************************************************************************/
0008 #ifndef __DWMAC1000_H__
0009 #define __DWMAC1000_H__
0010
0011 #include <linux/phy.h>
0012 #include "common.h"
0013
0014 #define GMAC_CONTROL        0x00000000  /* Configuration */
0015 #define GMAC_FRAME_FILTER   0x00000004  /* Frame Filter */
0016 #define GMAC_HASH_HIGH      0x00000008  /* Multicast Hash Table High */
0017 #define GMAC_HASH_LOW       0x0000000c  /* Multicast Hash Table Low */
0018 #define GMAC_MII_ADDR       0x00000010  /* MII Address */
0019 #define GMAC_MII_DATA       0x00000014  /* MII Data */
0020 #define GMAC_FLOW_CTRL      0x00000018  /* Flow Control */
0021 #define GMAC_VLAN_TAG       0x0000001c  /* VLAN Tag */
0022 #define GMAC_DEBUG      0x00000024  /* GMAC debug register */
0023 #define GMAC_WAKEUP_FILTER  0x00000028  /* Wake-up Frame Filter */
0024
0025 #define GMAC_INT_STATUS     0x00000038  /* interrupt status register */
0026 #define GMAC_INT_STATUS_PMT BIT(3)
0027 #define GMAC_INT_STATUS_MMCIS   BIT(4)
0028 #define GMAC_INT_STATUS_MMCRIS  BIT(5)
0029 #define GMAC_INT_STATUS_MMCTIS  BIT(6)
0030 #define GMAC_INT_STATUS_MMCCSUM BIT(7)
0031 #define GMAC_INT_STATUS_TSTAMP  BIT(9)
0032 #define GMAC_INT_STATUS_LPIIS   BIT(10)
0033
0034 /* interrupt mask register */
0035 #define GMAC_INT_MASK       0x0000003c
0036 #define GMAC_INT_DISABLE_RGMII      BIT(0)
0037 #define GMAC_INT_DISABLE_PCSLINK    BIT(1)
0038 #define GMAC_INT_DISABLE_PCSAN      BIT(2)
0039 #define GMAC_INT_DISABLE_PMT        BIT(3)
0040 #define GMAC_INT_DISABLE_TIMESTAMP  BIT(9)
0041 #define GMAC_INT_DISABLE_PCS    (GMAC_INT_DISABLE_RGMII | \
0042                  GMAC_INT_DISABLE_PCSLINK | \
0043                  GMAC_INT_DISABLE_PCSAN)
0044 #define GMAC_INT_DEFAULT_MASK   (GMAC_INT_DISABLE_TIMESTAMP | \
0045                  GMAC_INT_DISABLE_PCS)
0046
0047 /* PMT Control and Status */
0048 #define GMAC_PMT        0x0000002c
0049 enum power_event {
0050     pointer_reset = 0x80000000,
0051     global_unicast = 0x00000200,
0052     wake_up_rx_frame = 0x00000040,
0053     magic_frame = 0x00000020,
0054     wake_up_frame_en = 0x00000004,
0055     magic_pkt_en = 0x00000002,
0056     power_down = 0x00000001,
0057 };
0058
0059 /* Energy Efficient Ethernet (EEE)
0060  *
0061  * LPI status, timer and control register offset
0062  */
0063 #define LPI_CTRL_STATUS 0x0030
0064 #define LPI_TIMER_CTRL  0x0034
0065
0066 /* LPI control and status defines */
0067 #define LPI_CTRL_STATUS_LPITXA  0x00080000  /* Enable LPI TX Automate */
0068 #define LPI_CTRL_STATUS_PLSEN   0x00040000  /* Enable PHY Link Status */
0069 #define LPI_CTRL_STATUS_PLS 0x00020000  /* PHY Link Status */
0070 #define LPI_CTRL_STATUS_LPIEN   0x00010000  /* LPI Enable */
0071 #define LPI_CTRL_STATUS_RLPIST  0x00000200  /* Receive LPI state */
0072 #define LPI_CTRL_STATUS_TLPIST  0x00000100  /* Transmit LPI state */
0073 #define LPI_CTRL_STATUS_RLPIEX  0x00000008  /* Receive LPI Exit */
0074 #define LPI_CTRL_STATUS_RLPIEN  0x00000004  /* Receive LPI Entry */
0075 #define LPI_CTRL_STATUS_TLPIEX  0x00000002  /* Transmit LPI Exit */
0076 #define LPI_CTRL_STATUS_TLPIEN  0x00000001  /* Transmit LPI Entry */
0077
0078 /* GMAC HW ADDR regs */
0079 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
0080                  0x00000040 + (reg * 8))
0081 #define GMAC_ADDR_LOW(reg)  ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
0082                  0x00000044 + (reg * 8))
0083 #define GMAC_MAX_PERFECT_ADDRESSES  1
0084
0085 #define GMAC_PCS_BASE       0x000000c0  /* PCS register base */
0086 #define GMAC_RGSMIIIS       0x000000d8  /* RGMII/SMII status */
0087
0088 /* SGMII/RGMII status register */
0089 #define GMAC_RGSMIIIS_LNKMODE       BIT(0)
0090 #define GMAC_RGSMIIIS_SPEED     GENMASK(2, 1)
0091 #define GMAC_RGSMIIIS_SPEED_SHIFT   1
0092 #define GMAC_RGSMIIIS_LNKSTS        BIT(3)
0093 #define GMAC_RGSMIIIS_JABTO     BIT(4)
0094 #define GMAC_RGSMIIIS_FALSECARDET   BIT(5)
0095 #define GMAC_RGSMIIIS_SMIDRXS       BIT(16)
0096 /* LNKMOD */
0097 #define GMAC_RGSMIIIS_LNKMOD_MASK   0x1
0098 /* LNKSPEED */
0099 #define GMAC_RGSMIIIS_SPEED_125     0x2
0100 #define GMAC_RGSMIIIS_SPEED_25      0x1
0101 #define GMAC_RGSMIIIS_SPEED_2_5     0x0
0102
0103 /* GMAC Configuration defines */
0104 #define GMAC_CONTROL_2K 0x08000000  /* IEEE 802.3as 2K packets */
0105 #define GMAC_CONTROL_TC 0x01000000  /* Transmit Conf. in RGMII/SGMII */
0106 #define GMAC_CONTROL_WD 0x00800000  /* Disable Watchdog on receive */
0107 #define GMAC_CONTROL_JD 0x00400000  /* Jabber disable */
0108 #define GMAC_CONTROL_BE 0x00200000  /* Frame Burst Enable */
0109 #define GMAC_CONTROL_JE 0x00100000  /* Jumbo frame */
0110 enum inter_frame_gap {
0111     GMAC_CONTROL_IFG_88 = 0x00040000,
0112     GMAC_CONTROL_IFG_80 = 0x00020000,
0113     GMAC_CONTROL_IFG_40 = 0x000e0000,
0114 };
0115 #define GMAC_CONTROL_DCRS   0x00010000  /* Disable carrier sense */
0116 #define GMAC_CONTROL_PS     0x00008000  /* Port Select 0:GMI 1:MII */
0117 #define GMAC_CONTROL_FES    0x00004000  /* Speed 0:10 1:100 */
0118 #define GMAC_CONTROL_DO     0x00002000  /* Disable Rx Own */
0119 #define GMAC_CONTROL_LM     0x00001000  /* Loop-back mode */
0120 #define GMAC_CONTROL_DM     0x00000800  /* Duplex Mode */
0121 #define GMAC_CONTROL_IPC    0x00000400  /* Checksum Offload */
0122 #define GMAC_CONTROL_DR     0x00000200  /* Disable Retry */
0123 #define GMAC_CONTROL_LUD    0x00000100  /* Link up/down */
0124 #define GMAC_CONTROL_ACS    0x00000080  /* Auto Pad/FCS Stripping */
0125 #define GMAC_CONTROL_DC     0x00000010  /* Deferral Check */
0126 #define GMAC_CONTROL_TE     0x00000008  /* Transmitter Enable */
0127 #define GMAC_CONTROL_RE     0x00000004  /* Receiver Enable */
0128
0129 #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \
0130             GMAC_CONTROL_BE | GMAC_CONTROL_DCRS)
0131
0132 /* GMAC Frame Filter defines */
0133 #define GMAC_FRAME_FILTER_PR    0x00000001  /* Promiscuous Mode */
0134 #define GMAC_FRAME_FILTER_HUC   0x00000002  /* Hash Unicast */
0135 #define GMAC_FRAME_FILTER_HMC   0x00000004  /* Hash Multicast */
0136 #define GMAC_FRAME_FILTER_DAIF  0x00000008  /* DA Inverse Filtering */
0137 #define GMAC_FRAME_FILTER_PM    0x00000010  /* Pass all multicast */
0138 #define GMAC_FRAME_FILTER_DBF   0x00000020  /* Disable Broadcast frames */
0139 #define GMAC_FRAME_FILTER_PCF   0x00000080  /* Pass Control frames */
0140 #define GMAC_FRAME_FILTER_SAIF  0x00000100  /* Inverse Filtering */
0141 #define GMAC_FRAME_FILTER_SAF   0x00000200  /* Source Address Filter */
0142 #define GMAC_FRAME_FILTER_HPF   0x00000400  /* Hash or perfect Filter */
0143 #define GMAC_FRAME_FILTER_RA    0x80000000  /* Receive all mode */
0144 /* GMII ADDR  defines */
0145 #define GMAC_MII_ADDR_WRITE 0x00000002  /* MII Write */
0146 #define GMAC_MII_ADDR_BUSY  0x00000001  /* MII Busy */
0147 /* GMAC FLOW CTRL defines */
0148 #define GMAC_FLOW_CTRL_PT_MASK  0xffff0000  /* Pause Time Mask */
0149 #define GMAC_FLOW_CTRL_PT_SHIFT 16
0150 #define GMAC_FLOW_CTRL_UP   0x00000008  /* Unicast pause frame enable */
0151 #define GMAC_FLOW_CTRL_RFE  0x00000004  /* Rx Flow Control Enable */
0152 #define GMAC_FLOW_CTRL_TFE  0x00000002  /* Tx Flow Control Enable */
0153 #define GMAC_FLOW_CTRL_FCB_BPA  0x00000001  /* Flow Control Busy ... */
0154
0155 /* DEBUG Register defines */
0156 /* MTL TxStatus FIFO */
0157 #define GMAC_DEBUG_TXSTSFSTS    BIT(25) /* MTL TxStatus FIFO Full Status */
0158 #define GMAC_DEBUG_TXFSTS   BIT(24) /* MTL Tx FIFO Not Empty Status */
0159 #define GMAC_DEBUG_TWCSTS   BIT(22) /* MTL Tx FIFO Write Controller */
0160 /* MTL Tx FIFO Read Controller Status */
0161 #define GMAC_DEBUG_TRCSTS_MASK  GENMASK(21, 20)
0162 #define GMAC_DEBUG_TRCSTS_SHIFT 20
0163 #define GMAC_DEBUG_TRCSTS_IDLE  0
0164 #define GMAC_DEBUG_TRCSTS_READ  1
0165 #define GMAC_DEBUG_TRCSTS_TXW   2
0166 #define GMAC_DEBUG_TRCSTS_WRITE 3
0167 #define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */
0168 /* MAC Transmit Frame Controller Status */
0169 #define GMAC_DEBUG_TFCSTS_MASK  GENMASK(18, 17)
0170 #define GMAC_DEBUG_TFCSTS_SHIFT 17
0171 #define GMAC_DEBUG_TFCSTS_IDLE  0
0172 #define GMAC_DEBUG_TFCSTS_WAIT  1
0173 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
0174 #define GMAC_DEBUG_TFCSTS_XFER  3
0175 /* MAC GMII or MII Transmit Protocol Engine Status */
0176 #define GMAC_DEBUG_TPESTS   BIT(16)
0177 #define GMAC_DEBUG_RXFSTS_MASK  GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
0178 #define GMAC_DEBUG_RXFSTS_SHIFT 8
0179 #define GMAC_DEBUG_RXFSTS_EMPTY 0
0180 #define GMAC_DEBUG_RXFSTS_BT    1
0181 #define GMAC_DEBUG_RXFSTS_AT    2
0182 #define GMAC_DEBUG_RXFSTS_FULL  3
0183 #define GMAC_DEBUG_RRCSTS_MASK  GENMASK(6, 5) /* MTL Rx FIFO Read Controller */
0184 #define GMAC_DEBUG_RRCSTS_SHIFT 5
0185 #define GMAC_DEBUG_RRCSTS_IDLE  0
0186 #define GMAC_DEBUG_RRCSTS_RDATA 1
0187 #define GMAC_DEBUG_RRCSTS_RSTAT 2
0188 #define GMAC_DEBUG_RRCSTS_FLUSH 3
0189 #define GMAC_DEBUG_RWCSTS   BIT(4) /* MTL Rx FIFO Write Controller Active */
0190 /* MAC Receive Frame Controller FIFO Status */
0191 #define GMAC_DEBUG_RFCFCSTS_MASK    GENMASK(2, 1)
0192 #define GMAC_DEBUG_RFCFCSTS_SHIFT   1
0193 /* MAC GMII or MII Receive Protocol Engine Status */
0194 #define GMAC_DEBUG_RPESTS   BIT(0)
0195
0196 /*--- DMA BLOCK defines ---*/
0197 /* DMA Bus Mode register defines */
0198 #define DMA_BUS_MODE_DA     0x00000002  /* Arbitration scheme */
0199 #define DMA_BUS_MODE_DSL_MASK   0x0000007c  /* Descriptor Skip Length */
0200 #define DMA_BUS_MODE_DSL_SHIFT  2       /*   (in DWORDS)      */
0201 /* Programmable burst length (passed thorugh platform)*/
0202 #define DMA_BUS_MODE_PBL_MASK   0x00003f00  /* Programmable Burst Len */
0203 #define DMA_BUS_MODE_PBL_SHIFT  8
0204 #define DMA_BUS_MODE_ATDS   0x00000080  /* Alternate Descriptor Size */
0205
0206 enum rx_tx_priority_ratio {
0207     double_ratio = 0x00004000,  /* 2:1 */
0208     triple_ratio = 0x00008000,  /* 3:1 */
0209     quadruple_ratio = 0x0000c000,   /* 4:1 */
0210 };
0211
0212 #define DMA_BUS_MODE_FB     0x00010000  /* Fixed burst */
0213 #define DMA_BUS_MODE_MB     0x04000000  /* Mixed burst */
0214 #define DMA_BUS_MODE_RPBL_MASK  0x007e0000  /* Rx-Programmable Burst Len */
0215 #define DMA_BUS_MODE_RPBL_SHIFT 17
0216 #define DMA_BUS_MODE_USP    0x00800000
0217 #define DMA_BUS_MODE_MAXPBL 0x01000000
0218 #define DMA_BUS_MODE_AAL    0x02000000
0219
0220 /* DMA CRS Control and Status Register Mapping */
0221 #define DMA_HOST_TX_DESC      0x00001048    /* Current Host Tx descriptor */
0222 #define DMA_HOST_RX_DESC      0x0000104c    /* Current Host Rx descriptor */
0223 /*  DMA Bus Mode register defines */
0224 #define DMA_BUS_PR_RATIO_MASK     0x0000c000    /* Rx/Tx priority ratio */
0225 #define DMA_BUS_PR_RATIO_SHIFT    14
0226 #define DMA_BUS_FB        0x00010000    /* Fixed Burst */
0227
0228 /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
0229 /* Disable Drop TCP/IP csum error */
0230 #define DMA_CONTROL_DT      0x04000000
0231 #define DMA_CONTROL_RSF     0x02000000  /* Receive Store and Forward */
0232 #define DMA_CONTROL_DFF     0x01000000  /* Disaable flushing */
0233 /* Threshold for Activating the FC */
0234 enum rfa {
0235     act_full_minus_1 = 0x00800000,
0236     act_full_minus_2 = 0x00800200,
0237     act_full_minus_3 = 0x00800400,
0238     act_full_minus_4 = 0x00800600,
0239 };
0240 /* Threshold for Deactivating the FC */
0241 enum rfd {
0242     deac_full_minus_1 = 0x00400000,
0243     deac_full_minus_2 = 0x00400800,
0244     deac_full_minus_3 = 0x00401000,
0245     deac_full_minus_4 = 0x00401800,
0246 };
0247 #define DMA_CONTROL_TSF 0x00200000  /* Transmit  Store and Forward */
0248
0249 enum ttc_control {
0250     DMA_CONTROL_TTC_64 = 0x00000000,
0251     DMA_CONTROL_TTC_128 = 0x00004000,
0252     DMA_CONTROL_TTC_192 = 0x00008000,
0253     DMA_CONTROL_TTC_256 = 0x0000c000,
0254     DMA_CONTROL_TTC_40 = 0x00010000,
0255     DMA_CONTROL_TTC_32 = 0x00014000,
0256     DMA_CONTROL_TTC_24 = 0x00018000,
0257     DMA_CONTROL_TTC_16 = 0x0001c000,
0258 };
0259 #define DMA_CONTROL_TC_TX_MASK  0xfffe3fff
0260
0261 #define DMA_CONTROL_EFC     0x00000100
0262 #define DMA_CONTROL_FEF     0x00000080
0263 #define DMA_CONTROL_FUF     0x00000040
0264
0265 /* Receive flow control activation field
0266  * RFA field in DMA control register, bits 23,10:9
0267  */
0268 #define DMA_CONTROL_RFA_MASK    0x00800600
0269
0270 /* Receive flow control deactivation field
0271  * RFD field in DMA control register, bits 22,12:11
0272  */
0273 #define DMA_CONTROL_RFD_MASK    0x00401800
0274
0275 /* RFD and RFA fields are encoded as follows
0276  *
0277  *   Bit Field
0278  *   0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
0279  *   0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
0280  *   0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
0281  *   0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
0282  *   1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
0283  *   1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
0284  *   1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
0285  *   1,11 - Reserved
0286  *
0287  * RFD should always be > RFA for a given FIFO size. RFD == RFA may work,
0288  * but packet throughput performance may not be as expected.
0289  *
0290  * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame
0291  * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause
0292  * Description).
0293  *
0294  * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),
0295  * is set to 0. This allows pause frames with a quanta of 0 to be sent
0296  * as an XOFF message to the link peer.
0297  */
0298
0299 #define RFA_FULL_MINUS_1K   0x00000000
0300 #define RFA_FULL_MINUS_2K   0x00000200
0301 #define RFA_FULL_MINUS_3K   0x00000400
0302 #define RFA_FULL_MINUS_4K   0x00000600
0303 #define RFA_FULL_MINUS_5K   0x00800000
0304 #define RFA_FULL_MINUS_6K   0x00800200
0305 #define RFA_FULL_MINUS_7K   0x00800400
0306
0307 #define RFD_FULL_MINUS_1K   0x00000000
0308 #define RFD_FULL_MINUS_2K   0x00000800
0309 #define RFD_FULL_MINUS_3K   0x00001000
0310 #define RFD_FULL_MINUS_4K   0x00001800
0311 #define RFD_FULL_MINUS_5K   0x00400000
0312 #define RFD_FULL_MINUS_6K   0x00400800
0313 #define RFD_FULL_MINUS_7K   0x00401000
0314
0315 enum rtc_control {
0316     DMA_CONTROL_RTC_64 = 0x00000000,
0317     DMA_CONTROL_RTC_32 = 0x00000008,
0318     DMA_CONTROL_RTC_96 = 0x00000010,
0319     DMA_CONTROL_RTC_128 = 0x00000018,
0320 };
0321 #define DMA_CONTROL_TC_RX_MASK  0xffffffe7
0322
0323 #define DMA_CONTROL_OSF 0x00000004  /* Operate on second frame */
0324
0325 /* MMC registers offset */
0326 #define GMAC_MMC_CTRL      0x100
0327 #define GMAC_MMC_RX_INTR   0x104
0328 #define GMAC_MMC_TX_INTR   0x108
0329 #define GMAC_MMC_RX_CSUM_OFFLOAD   0x208
0330 #define GMAC_EXTHASH_BASE  0x500
0331
0332 extern const struct stmmac_dma_ops dwmac1000_dma_ops;
0333 #endif /* __DWMAC1000_H__ */