stmicro/stmmac/dwmac100.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*******************************************************************************
0003   MAC 10/100 Header File
0004
0005   Copyright (C) 2007-2009  STMicroelectronics Ltd
0006
0007
0008   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0009 *******************************************************************************/
0010
0011 #ifndef __DWMAC100_H__
0012 #define __DWMAC100_H__
0013
0014 #include <linux/phy.h>
0015 #include "common.h"
0016
0017 /*----------------------------------------------------------------------------
0018  *              MAC BLOCK defines
0019  *---------------------------------------------------------------------------*/
0020 /* MAC CSR offset */
0021 #define MAC_CONTROL 0x00000000  /* MAC Control */
0022 #define MAC_ADDR_HIGH   0x00000004  /* MAC Address High */
0023 #define MAC_ADDR_LOW    0x00000008  /* MAC Address Low */
0024 #define MAC_HASH_HIGH   0x0000000c  /* Multicast Hash Table High */
0025 #define MAC_HASH_LOW    0x00000010  /* Multicast Hash Table Low */
0026 #define MAC_MII_ADDR    0x00000014  /* MII Address */
0027 #define MAC_MII_DATA    0x00000018  /* MII Data */
0028 #define MAC_FLOW_CTRL   0x0000001c  /* Flow Control */
0029 #define MAC_VLAN1   0x00000020  /* VLAN1 Tag */
0030 #define MAC_VLAN2   0x00000024  /* VLAN2 Tag */
0031
0032 /* MAC CTRL defines */
0033 #define MAC_CONTROL_RA  0x80000000  /* Receive All Mode */
0034 #define MAC_CONTROL_BLE 0x40000000  /* Endian Mode */
0035 #define MAC_CONTROL_HBD 0x10000000  /* Heartbeat Disable */
0036 #define MAC_CONTROL_PS  0x08000000  /* Port Select */
0037 #define MAC_CONTROL_DRO 0x00800000  /* Disable Receive Own */
0038 #define MAC_CONTROL_EXT_LOOPBACK 0x00400000 /* Reserved (ext loopback?) */
0039 #define MAC_CONTROL_OM  0x00200000  /* Loopback Operating Mode */
0040 #define MAC_CONTROL_F   0x00100000  /* Full Duplex Mode */
0041 #define MAC_CONTROL_PM  0x00080000  /* Pass All Multicast */
0042 #define MAC_CONTROL_PR  0x00040000  /* Promiscuous Mode */
0043 #define MAC_CONTROL_IF  0x00020000  /* Inverse Filtering */
0044 #define MAC_CONTROL_PB  0x00010000  /* Pass Bad Frames */
0045 #define MAC_CONTROL_HO  0x00008000  /* Hash Only Filtering Mode */
0046 #define MAC_CONTROL_HP  0x00002000  /* Hash/Perfect Filtering Mode */
0047 #define MAC_CONTROL_LCC 0x00001000  /* Late Collision Control */
0048 #define MAC_CONTROL_DBF 0x00000800  /* Disable Broadcast Frames */
0049 #define MAC_CONTROL_DRTY    0x00000400  /* Disable Retry */
0050 #define MAC_CONTROL_ASTP    0x00000100  /* Automatic Pad Stripping */
0051 #define MAC_CONTROL_BOLMT_10    0x00000000  /* Back Off Limit 10 */
0052 #define MAC_CONTROL_BOLMT_8 0x00000040  /* Back Off Limit 8 */
0053 #define MAC_CONTROL_BOLMT_4 0x00000080  /* Back Off Limit 4 */
0054 #define MAC_CONTROL_BOLMT_1 0x000000c0  /* Back Off Limit 1 */
0055 #define MAC_CONTROL_DC      0x00000020  /* Deferral Check */
0056 #define MAC_CONTROL_TE      0x00000008  /* Transmitter Enable */
0057 #define MAC_CONTROL_RE      0x00000004  /* Receiver Enable */
0058
0059 #define MAC_CORE_INIT (MAC_CONTROL_HBD | MAC_CONTROL_ASTP)
0060
0061 /* MAC FLOW CTRL defines */
0062 #define MAC_FLOW_CTRL_PT_MASK   0xffff0000  /* Pause Time Mask */
0063 #define MAC_FLOW_CTRL_PT_SHIFT  16
0064 #define MAC_FLOW_CTRL_PASS  0x00000004  /* Pass Control Frames */
0065 #define MAC_FLOW_CTRL_ENABLE    0x00000002  /* Flow Control Enable */
0066 #define MAC_FLOW_CTRL_PAUSE 0x00000001  /* Flow Control Busy ... */
0067
0068 /* MII ADDR  defines */
0069 #define MAC_MII_ADDR_WRITE  0x00000002  /* MII Write */
0070 #define MAC_MII_ADDR_BUSY   0x00000001  /* MII Busy */
0071
0072 /*----------------------------------------------------------------------------
0073  *              DMA BLOCK defines
0074  *---------------------------------------------------------------------------*/
0075
0076 /* DMA Bus Mode register defines */
0077 #define DMA_BUS_MODE_DBO    0x00100000  /* Descriptor Byte Ordering */
0078 #define DMA_BUS_MODE_BLE    0x00000080  /* Big Endian/Little Endian */
0079 #define DMA_BUS_MODE_PBL_MASK   0x00003f00  /* Programmable Burst Len */
0080 #define DMA_BUS_MODE_PBL_SHIFT  8
0081 #define DMA_BUS_MODE_DSL_MASK   0x0000007c  /* Descriptor Skip Length */
0082 #define DMA_BUS_MODE_DSL_SHIFT  2   /*   (in DWORDS)      */
0083 #define DMA_BUS_MODE_BAR_BUS    0x00000002  /* Bar-Bus Arbitration */
0084 #define DMA_BUS_MODE_DEFAULT    0x00000000
0085
0086 /* DMA Control register defines */
0087 #define DMA_CONTROL_SF      0x00200000  /* Store And Forward */
0088
0089 /* Transmit Threshold Control */
0090 enum ttc_control {
0091     DMA_CONTROL_TTC_DEFAULT = 0x00000000,   /* Threshold is 32 DWORDS */
0092     DMA_CONTROL_TTC_64 = 0x00004000,    /* Threshold is 64 DWORDS */
0093     DMA_CONTROL_TTC_128 = 0x00008000,   /* Threshold is 128 DWORDS */
0094     DMA_CONTROL_TTC_256 = 0x0000c000,   /* Threshold is 256 DWORDS */
0095     DMA_CONTROL_TTC_18 = 0x00400000,    /* Threshold is 18 DWORDS */
0096     DMA_CONTROL_TTC_24 = 0x00404000,    /* Threshold is 24 DWORDS */
0097     DMA_CONTROL_TTC_32 = 0x00408000,    /* Threshold is 32 DWORDS */
0098     DMA_CONTROL_TTC_40 = 0x0040c000,    /* Threshold is 40 DWORDS */
0099     DMA_CONTROL_SE = 0x00000008,    /* Stop On Empty */
0100     DMA_CONTROL_OSF = 0x00000004,   /* Operate On 2nd Frame */
0101 };
0102
0103 /* STMAC110 DMA Missed Frame Counter register defines */
0104 #define DMA_MISSED_FRAME_OVE    0x10000000  /* FIFO Overflow Overflow */
0105 #define DMA_MISSED_FRAME_OVE_CNTR 0x0ffe0000    /* Overflow Frame Counter */
0106 #define DMA_MISSED_FRAME_OVE_M  0x00010000  /* Missed Frame Overflow */
0107 #define DMA_MISSED_FRAME_M_CNTR 0x0000ffff  /* Missed Frame Couinter */
0108
0109 extern const struct stmmac_dma_ops dwmac100_dma_ops;
0110
0111 #endif /* __DWMAC100_H__ */